forked from Minki/linux
ARM: imx: Add DMAMUX clock for Vybrid vf610 SoC
Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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@ -298,6 +298,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
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clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
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clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
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clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4));
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clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5));
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clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
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clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
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clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
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clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
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clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
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@ -160,6 +160,10 @@
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#define VF610_CLK_GPU2D 147
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#define VF610_CLK_ENET0 148
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#define VF610_CLK_ENET1 149
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#define VF610_CLK_END 150
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#define VF610_CLK_DMAMUX0 150
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#define VF610_CLK_DMAMUX1 151
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#define VF610_CLK_DMAMUX2 152
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#define VF610_CLK_DMAMUX3 153
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#define VF610_CLK_END 154
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#endif /* __DT_BINDINGS_CLOCK_VF610_H */
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