forked from Minki/linux
ptp: ptp_clockmatrix: Add support for pll_mode=0 and manual ref switch of WF and WP
Also correct how initialize_dco_operating_mode is called Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Min Li
David S. Miller
parent
794c3dffac
commit
da9facf1c1
@ -635,6 +635,10 @@
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#define STATE_MODE_SHIFT (0)
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#define STATE_MODE_MASK (0x7)
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/* Bit definitions for the DPLL_MANU_REF_CFG register */
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#define MANUAL_REFERENCE_SHIFT (0)
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#define MANUAL_REFERENCE_MASK (0x1f)
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/* Bit definitions for the GPIO_CFG_GBL register */
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#define SUPPLY_MODE_SHIFT (0)
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#define SUPPLY_MODE_MASK (0x3)
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@ -33,6 +33,8 @@ module_param(firmware, charp, 0);
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#define SETTIME_CORRECTION (0)
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static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
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static int contains_full_configuration(struct idtcm *idtcm,
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const struct firmware *fw)
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{
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@ -657,8 +659,8 @@ static int idtcm_sync_pps_output(struct idtcm_channel *channel)
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}
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static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
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struct timespec64 const *ts,
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enum hw_tod_write_trig_sel wr_trig)
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struct timespec64 const *ts,
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enum hw_tod_write_trig_sel wr_trig)
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{
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struct idtcm *idtcm = channel->idtcm;
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u8 buf[TOD_BYTE_COUNT];
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@ -920,9 +922,9 @@ static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
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return err;
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}
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static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
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s32 offset_ns,
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u32 max_ffo_ppb)
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static int do_phase_pull_in_fw(struct idtcm_channel *channel,
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s32 offset_ns,
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u32 max_ffo_ppb)
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{
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int err;
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@ -991,7 +993,7 @@ static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta)
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s64 now;
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if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) {
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err = idtcm_do_phase_pull_in(channel, delta, 0);
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err = channel->do_phase_pull_in(channel, delta, 0);
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} else {
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idtcm->calculate_overhead_flag = 1;
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@ -1220,7 +1222,7 @@ static int idtcm_load_firmware(struct idtcm *idtcm,
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if (firmware) /* module parameter */
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snprintf(fname, sizeof(fname), "%s", firmware);
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dev_dbg(&idtcm->client->dev, "requesting firmware '%s'", fname);
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dev_info(&idtcm->client->dev, "firmware '%s'", fname);
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err = request_firmware(&fw, fname, dev);
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if (err) {
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@ -1354,7 +1356,7 @@ static int idtcm_perout_enable(struct idtcm_channel *channel,
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}
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static int idtcm_get_pll_mode(struct idtcm_channel *channel,
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enum pll_mode *pll_mode)
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enum pll_mode *mode)
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{
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struct idtcm *idtcm = channel->idtcm;
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int err;
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@ -1366,13 +1368,13 @@ static int idtcm_get_pll_mode(struct idtcm_channel *channel,
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if (err)
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return err;
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*pll_mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
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*mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
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return 0;
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}
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static int idtcm_set_pll_mode(struct idtcm_channel *channel,
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enum pll_mode pll_mode)
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enum pll_mode mode)
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{
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struct idtcm *idtcm = channel->idtcm;
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int err;
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@ -1386,23 +1388,298 @@ static int idtcm_set_pll_mode(struct idtcm_channel *channel,
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dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
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dpll_mode |= (pll_mode << PLL_MODE_SHIFT);
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channel->pll_mode = pll_mode;
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dpll_mode |= (mode << PLL_MODE_SHIFT);
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err = idtcm_write(idtcm, channel->dpll_n,
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IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
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&dpll_mode, sizeof(dpll_mode));
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return err;
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}
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static int idtcm_get_manual_reference(struct idtcm_channel *channel,
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enum manual_reference *ref)
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{
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struct idtcm *idtcm = channel->idtcm;
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u8 dpll_manu_ref_cfg;
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int err;
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err = idtcm_read(idtcm, channel->dpll_ctrl_n,
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DPLL_CTRL_DPLL_MANU_REF_CFG,
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&dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
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if (err)
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return err;
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dpll_manu_ref_cfg &= (MANUAL_REFERENCE_MASK << MANUAL_REFERENCE_SHIFT);
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*ref = dpll_manu_ref_cfg >> MANUAL_REFERENCE_SHIFT;
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return 0;
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}
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static int idtcm_set_manual_reference(struct idtcm_channel *channel,
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enum manual_reference ref)
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{
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struct idtcm *idtcm = channel->idtcm;
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u8 dpll_manu_ref_cfg;
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int err;
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err = idtcm_read(idtcm, channel->dpll_ctrl_n,
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DPLL_CTRL_DPLL_MANU_REF_CFG,
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&dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
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if (err)
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return err;
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dpll_manu_ref_cfg &= ~(MANUAL_REFERENCE_MASK << MANUAL_REFERENCE_SHIFT);
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dpll_manu_ref_cfg |= (ref << MANUAL_REFERENCE_SHIFT);
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err = idtcm_write(idtcm, channel->dpll_ctrl_n,
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DPLL_CTRL_DPLL_MANU_REF_CFG,
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&dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
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return err;
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}
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static int configure_dpll_mode_write_frequency(struct idtcm_channel *channel)
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{
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struct idtcm *idtcm = channel->idtcm;
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int err;
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err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
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if (err)
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dev_err(&idtcm->client->dev, "Failed to set pll mode to write frequency");
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else
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channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
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return err;
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}
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static int configure_dpll_mode_write_phase(struct idtcm_channel *channel)
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{
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struct idtcm *idtcm = channel->idtcm;
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int err;
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err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
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if (err)
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dev_err(&idtcm->client->dev, "Failed to set pll mode to write phase");
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else
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channel->mode = PTP_PLL_MODE_WRITE_PHASE;
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return err;
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}
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static int configure_manual_reference_write_frequency(struct idtcm_channel *channel)
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{
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struct idtcm *idtcm = channel->idtcm;
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int err;
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err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_FREQUENCY);
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if (err)
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dev_err(&idtcm->client->dev, "Failed to set manual reference to write frequency");
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else
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channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
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return err;
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}
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static int configure_manual_reference_write_phase(struct idtcm_channel *channel)
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{
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struct idtcm *idtcm = channel->idtcm;
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int err;
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err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_PHASE);
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if (err)
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dev_err(&idtcm->client->dev, "Failed to set manual reference to write phase");
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else
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channel->mode = PTP_PLL_MODE_WRITE_PHASE;
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return err;
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}
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static int idtcm_stop_phase_pull_in(struct idtcm_channel *channel)
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{
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int err;
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err = _idtcm_adjfine(channel, channel->current_freq_scaled_ppm);
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if (err)
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return err;
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channel->phase_pull_in = false;
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return 0;
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}
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static long idtcm_work_handler(struct ptp_clock_info *ptp)
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{
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struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
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struct idtcm *idtcm = channel->idtcm;
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mutex_lock(&idtcm->reg_lock);
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(void)idtcm_stop_phase_pull_in(channel);
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mutex_unlock(&idtcm->reg_lock);
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/* Return a negative value here to not reschedule */
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return -1;
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}
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static s32 phase_pull_in_scaled_ppm(s32 current_ppm, s32 phase_pull_in_ppb)
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{
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/* ppb = scaled_ppm * 125 / 2^13 */
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/* scaled_ppm = ppb * 2^13 / 125 */
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s64 max_scaled_ppm = (PHASE_PULL_IN_MAX_PPB << 13) / 125;
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s64 scaled_ppm = (phase_pull_in_ppb << 13) / 125;
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current_ppm += scaled_ppm;
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if (current_ppm > max_scaled_ppm)
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current_ppm = max_scaled_ppm;
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else if (current_ppm < -max_scaled_ppm)
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current_ppm = -max_scaled_ppm;
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return current_ppm;
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}
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static int do_phase_pull_in_sw(struct idtcm_channel *channel,
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s32 delta_ns,
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u32 max_ffo_ppb)
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{
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s32 current_ppm = channel->current_freq_scaled_ppm;
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u32 duration_ms = MSEC_PER_SEC;
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s32 delta_ppm;
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s32 ppb;
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int err;
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/* If the ToD correction is less than PHASE_PULL_IN_MIN_THRESHOLD_NS,
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* skip. The error introduced by the ToD adjustment procedure would
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* be bigger than the required ToD correction
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*/
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if (abs(delta_ns) < PHASE_PULL_IN_MIN_THRESHOLD_NS)
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return 0;
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if (max_ffo_ppb == 0)
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max_ffo_ppb = PHASE_PULL_IN_MAX_PPB;
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/* For most cases, keep phase pull-in duration 1 second */
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ppb = delta_ns;
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while (abs(ppb) > max_ffo_ppb) {
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duration_ms *= 2;
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ppb /= 2;
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}
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delta_ppm = phase_pull_in_scaled_ppm(current_ppm, ppb);
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err = _idtcm_adjfine(channel, delta_ppm);
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if (err)
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return err;
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/* schedule the worker to cancel phase pull-in */
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ptp_schedule_worker(channel->ptp_clock,
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msecs_to_jiffies(duration_ms) - 1);
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channel->phase_pull_in = true;
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return 0;
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}
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static int initialize_operating_mode_with_manual_reference(struct idtcm_channel *channel,
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enum manual_reference ref)
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{
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struct idtcm *idtcm = channel->idtcm;
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channel->mode = PTP_PLL_MODE_UNSUPPORTED;
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channel->configure_write_frequency = configure_manual_reference_write_frequency;
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channel->configure_write_phase = configure_manual_reference_write_phase;
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channel->do_phase_pull_in = do_phase_pull_in_sw;
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switch (ref) {
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case MANU_REF_WRITE_PHASE:
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channel->mode = PTP_PLL_MODE_WRITE_PHASE;
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break;
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case MANU_REF_WRITE_FREQUENCY:
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channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
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break;
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default:
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dev_warn(&idtcm->client->dev,
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"Unsupported MANUAL_REFERENCE: 0x%02x", ref);
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}
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return 0;
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}
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static int initialize_operating_mode_with_pll_mode(struct idtcm_channel *channel,
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enum pll_mode mode)
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{
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struct idtcm *idtcm = channel->idtcm;
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int err = 0;
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channel->mode = PTP_PLL_MODE_UNSUPPORTED;
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channel->configure_write_frequency = configure_dpll_mode_write_frequency;
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channel->configure_write_phase = configure_dpll_mode_write_phase;
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channel->do_phase_pull_in = do_phase_pull_in_fw;
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switch (mode) {
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case PLL_MODE_WRITE_PHASE:
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channel->mode = PTP_PLL_MODE_WRITE_PHASE;
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break;
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case PLL_MODE_WRITE_FREQUENCY:
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channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
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break;
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default:
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dev_err(&idtcm->client->dev,
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"Unsupported PLL_MODE: 0x%02x", mode);
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err = -EINVAL;
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}
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return err;
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}
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static int initialize_dco_operating_mode(struct idtcm_channel *channel)
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{
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enum manual_reference ref = MANU_REF_XO_DPLL;
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enum pll_mode mode = PLL_MODE_DISABLED;
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struct idtcm *idtcm = channel->idtcm;
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int err;
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channel->mode = PTP_PLL_MODE_UNSUPPORTED;
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err = idtcm_get_pll_mode(channel, &mode);
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if (err) {
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dev_err(&idtcm->client->dev, "Unable to read pll mode!");
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return err;
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}
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if (mode == PLL_MODE_PLL) {
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err = idtcm_get_manual_reference(channel, &ref);
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if (err) {
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dev_err(&idtcm->client->dev, "Unable to read manual reference!");
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return err;
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}
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err = initialize_operating_mode_with_manual_reference(channel, ref);
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} else {
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err = initialize_operating_mode_with_pll_mode(channel, mode);
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}
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if (channel->mode == PTP_PLL_MODE_WRITE_PHASE)
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channel->configure_write_frequency(channel);
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return err;
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}
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/* PTP Hardware Clock interface */
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/**
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* @brief Maximum absolute value for write phase offset in picoseconds
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* Maximum absolute value for write phase offset in picoseconds
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*
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* @channel: channel
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* @delta_ns: delta in nanoseconds
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*
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* Destination signed register is 32-bit register in resolution of 50ps
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*
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@ -1417,8 +1694,8 @@ static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
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s32 phase_50ps;
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s64 offset_ps;
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if (channel->pll_mode != PLL_MODE_WRITE_PHASE) {
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err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
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if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) {
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err = channel->configure_write_phase(channel);
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if (err)
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return err;
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}
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@ -1456,8 +1733,8 @@ static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
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u8 buf[6] = {0};
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s64 fcw;
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if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) {
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err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
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if (channel->mode != PTP_PLL_MODE_WRITE_FREQUENCY) {
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err = channel->configure_write_frequency(channel);
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if (err)
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return err;
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}
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@ -1574,29 +1851,29 @@ static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
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enum scsr_tod_write_type_sel type;
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int err;
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if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
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err = idtcm_do_phase_pull_in(channel, delta, 0);
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if (err)
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dev_err(&idtcm->client->dev,
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"Failed at line %d in %s!", __LINE__, __func__);
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return err;
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}
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if (delta >= 0) {
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ts = ns_to_timespec64(delta);
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type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
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} else {
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ts = ns_to_timespec64(-delta);
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type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
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}
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if (channel->phase_pull_in == true)
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return 0;
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mutex_lock(&idtcm->reg_lock);
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err = _idtcm_settime(channel, &ts, type);
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if (err)
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dev_err(&idtcm->client->dev,
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"Failed at line %d in %s!", __LINE__, __func__);
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if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
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err = channel->do_phase_pull_in(channel, delta, 0);
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if (err)
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dev_err(&idtcm->client->dev,
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"Failed at line %d in %s!", __LINE__, __func__);
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} else {
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if (delta >= 0) {
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ts = ns_to_timespec64(delta);
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type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
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} else {
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ts = ns_to_timespec64(-delta);
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type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
|
||||
}
|
||||
err = _idtcm_settime(channel, &ts, type);
|
||||
if (err)
|
||||
dev_err(&idtcm->client->dev,
|
||||
"Failed at line %d in %s!", __LINE__, __func__);
|
||||
}
|
||||
mutex_unlock(&idtcm->reg_lock);
|
||||
|
||||
return err;
|
||||
@ -1626,15 +1903,21 @@ static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
|
||||
struct idtcm *idtcm = channel->idtcm;
|
||||
int err;
|
||||
|
||||
if (channel->phase_pull_in == true)
|
||||
return 0;
|
||||
|
||||
if (scaled_ppm == channel->current_freq_scaled_ppm)
|
||||
return 0;
|
||||
|
||||
mutex_lock(&idtcm->reg_lock);
|
||||
|
||||
err = _idtcm_adjfine(channel, scaled_ppm);
|
||||
if (err)
|
||||
dev_err(&idtcm->client->dev,
|
||||
"Failed at line %d in %s!", __LINE__, __func__);
|
||||
|
||||
mutex_unlock(&idtcm->reg_lock);
|
||||
|
||||
if (!err)
|
||||
channel->current_freq_scaled_ppm = scaled_ppm;
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
@ -1746,6 +2029,7 @@ static const struct ptp_clock_info idtcm_caps = {
|
||||
.gettime64 = &idtcm_gettime,
|
||||
.settime64 = &idtcm_settime,
|
||||
.enable = &idtcm_enable,
|
||||
.do_aux_work = &idtcm_work_handler,
|
||||
};
|
||||
|
||||
static const struct ptp_clock_info idtcm_caps_deprecated = {
|
||||
@ -1758,6 +2042,7 @@ static const struct ptp_clock_info idtcm_caps_deprecated = {
|
||||
.gettime64 = &idtcm_gettime,
|
||||
.settime64 = &idtcm_settime_deprecated,
|
||||
.enable = &idtcm_enable,
|
||||
.do_aux_work = &idtcm_work_handler,
|
||||
};
|
||||
|
||||
static int configure_channel_pll(struct idtcm_channel *channel)
|
||||
@ -1847,7 +2132,9 @@ static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
|
||||
return -EINVAL;
|
||||
|
||||
channel = &idtcm->channel[index];
|
||||
|
||||
channel->idtcm = idtcm;
|
||||
channel->current_freq_scaled_ppm = 0;
|
||||
|
||||
/* Set pll addresses */
|
||||
err = configure_channel_pll(channel);
|
||||
@ -1892,13 +2179,9 @@ static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
|
||||
snprintf(channel->caps.name, sizeof(channel->caps.name),
|
||||
"IDT CM TOD%u", index);
|
||||
|
||||
/* Sync pll mode with hardware */
|
||||
err = idtcm_get_pll_mode(channel, &channel->pll_mode);
|
||||
if (err) {
|
||||
dev_err(&idtcm->client->dev,
|
||||
"Error: %s - Unable to read pll mode", __func__);
|
||||
err = initialize_dco_operating_mode(channel);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
err = idtcm_enable_tod(channel);
|
||||
if (err) {
|
||||
@ -1931,7 +2214,6 @@ static void ptp_clock_unregister_all(struct idtcm *idtcm)
|
||||
|
||||
for (i = 0; i < MAX_TOD; i++) {
|
||||
channel = &idtcm->channel[i];
|
||||
|
||||
if (channel->ptp_clock)
|
||||
ptp_clock_unregister(channel->ptp_clock);
|
||||
}
|
||||
|
||||
@ -57,15 +57,27 @@
|
||||
|
||||
#define IDTCM_MAX_WRITE_COUNT (512)
|
||||
|
||||
#define PHASE_PULL_IN_MAX_PPB (144000)
|
||||
#define PHASE_PULL_IN_MIN_THRESHOLD_NS (2)
|
||||
|
||||
/*
|
||||
* Return register address based on passed in firmware version
|
||||
*/
|
||||
#define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER))
|
||||
|
||||
/* PTP PLL Mode */
|
||||
enum ptp_pll_mode {
|
||||
PTP_PLL_MODE_MIN = 0,
|
||||
PTP_PLL_MODE_WRITE_FREQUENCY = PTP_PLL_MODE_MIN,
|
||||
PTP_PLL_MODE_WRITE_PHASE,
|
||||
PTP_PLL_MODE_UNSUPPORTED,
|
||||
PTP_PLL_MODE_MAX = PTP_PLL_MODE_UNSUPPORTED,
|
||||
};
|
||||
|
||||
/* Values of DPLL_N.DPLL_MODE.PLL_MODE */
|
||||
enum pll_mode {
|
||||
PLL_MODE_MIN = 0,
|
||||
PLL_MODE_NORMAL = PLL_MODE_MIN,
|
||||
PLL_MODE_PLL = PLL_MODE_MIN,
|
||||
PLL_MODE_WRITE_PHASE = 1,
|
||||
PLL_MODE_WRITE_FREQUENCY = 2,
|
||||
PLL_MODE_GPIO_INC_DEC = 3,
|
||||
@ -75,6 +87,31 @@ enum pll_mode {
|
||||
PLL_MODE_MAX = PLL_MODE_DISABLED,
|
||||
};
|
||||
|
||||
/* Values of DPLL_CTRL_n.DPLL_MANU_REF_CFG.MANUAL_REFERENCE */
|
||||
enum manual_reference {
|
||||
MANU_REF_MIN = 0,
|
||||
MANU_REF_CLK0 = MANU_REF_MIN,
|
||||
MANU_REF_CLK1,
|
||||
MANU_REF_CLK2,
|
||||
MANU_REF_CLK3,
|
||||
MANU_REF_CLK4,
|
||||
MANU_REF_CLK5,
|
||||
MANU_REF_CLK6,
|
||||
MANU_REF_CLK7,
|
||||
MANU_REF_CLK8,
|
||||
MANU_REF_CLK9,
|
||||
MANU_REF_CLK10,
|
||||
MANU_REF_CLK11,
|
||||
MANU_REF_CLK12,
|
||||
MANU_REF_CLK13,
|
||||
MANU_REF_CLK14,
|
||||
MANU_REF_CLK15,
|
||||
MANU_REF_WRITE_PHASE,
|
||||
MANU_REF_WRITE_FREQUENCY,
|
||||
MANU_REF_XO_DPLL,
|
||||
MANU_REF_MAX = MANU_REF_XO_DPLL,
|
||||
};
|
||||
|
||||
enum hw_tod_write_trig_sel {
|
||||
HW_TOD_WR_TRIG_SEL_MIN = 0,
|
||||
HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,
|
||||
@ -141,7 +178,13 @@ struct idtcm_channel {
|
||||
u16 tod_n;
|
||||
u16 hw_dpll_n;
|
||||
u8 sync_src;
|
||||
enum pll_mode pll_mode;
|
||||
enum ptp_pll_mode mode;
|
||||
int (*configure_write_frequency)(struct idtcm_channel *channel);
|
||||
int (*configure_write_phase)(struct idtcm_channel *channel);
|
||||
int (*do_phase_pull_in)(struct idtcm_channel *channel,
|
||||
s32 offset_ns, u32 max_ffo_ppb);
|
||||
s32 current_freq_scaled_ppm;
|
||||
bool phase_pull_in;
|
||||
u8 pll;
|
||||
u16 output_mask;
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user