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drm/amd/display: Use switch table for dc_to_smu_clock_type

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Using a static int array will cause errors if the given dm_pp_clk_type
is out-of-bounds. For robustness, use a switch table, with a default
case to handle all invalid values.

v2: 0 is a valid clock type for smu_clk_type. Return SMU_CLK_COUNT
    instead on invalid mapping.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leo Li 2019-07-25 13:12:24 -04:00 committed by Alex Deucher
parent d196bbbc28
commit d9ec5cfd5a
1 changed files with 23 additions and 10 deletions
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33
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
View File

@ -151,18 +151,31 @@ static void get_default_clock_levels(
static enum smu_clk_type dc_to_smu_clock_type( static enum smu_clk_type dc_to_smu_clock_type(
enum dm_pp_clock_type dm_pp_clk_type) enum dm_pp_clock_type dm_pp_clk_type)
{ {
#define DCCLK_MAP_SMUCLK(dcclk, smuclk) \ enum smu_clk_type smu_clk_type = SMU_CLK_COUNT;
[dcclk] = smuclk
static int dc_clk_type_map[] = { switch (dm_pp_clk_type) {
DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DISPLAY_CLK, SMU_DISPCLK), case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_ENGINE_CLK, SMU_GFXCLK), smu_clk_type = SMU_DISPCLK;
DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_MEMORY_CLK, SMU_MCLK), break;
DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DCEFCLK, SMU_DCEFCLK), case DM_PP_CLOCK_TYPE_ENGINE_CLK:
DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_SOCCLK, SMU_SOCCLK), smu_clk_type = SMU_GFXCLK;
}; break;
case DM_PP_CLOCK_TYPE_MEMORY_CLK:
smu_clk_type = SMU_MCLK;
break;
case DM_PP_CLOCK_TYPE_DCEFCLK:
smu_clk_type = SMU_DCEFCLK;
break;
case DM_PP_CLOCK_TYPE_SOCCLK:
smu_clk_type = SMU_SOCCLK;
break;
default:
DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
dm_pp_clk_type);
break;
}
return dc_clk_type_map[dm_pp_clk_type]; return smu_clk_type;
} }
static enum amd_pp_clock_type dc_to_pp_clock_type( static enum amd_pp_clock_type dc_to_pp_clock_type(