forked from Minki/linux
[ALSA] AZT3328 driver update
Modules: AZT3328 driver this is now an even much more reworked patch (#3) for my azt3328.c ALSA driver. IOW I spent another 4 evenings to get the sequencer timer to work properly (my head is still hurting) and do lots of other cleanups. Note that despite the extensive sequencer timer additions, the driver object is still only 2kB bigger than the previous version, due to those many optimizations... Changes in version #3: - fully working ALSA sequencer timer support for the card's 1024000Hz DirectX timer (downscaling adjustable via seqtimer_scaling module param) - an insane amount of code optimizations - many, many cleanups Changes in version #2: - FOUND the 1us DirectX timer area (yay!), made the code respect it properly - renamed some 'weird' mixer control names according to ControlNames.txt - cleanup unneeded debug messages, reformatting - improved I/O register documentation - constified many more structs Changes in version #1: - improves/fixes some fatal playback/recording interaction - improves IRQ handler performance (and actually fixes some weird code) - coalesces some I/O accesses - slightly improves I/O interface documentation - improves/fixes logging - defines out some less important debug code - constifies some data Signed-off-by: Andreas Mohr <andi@lisas.de> Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Andreas Mohr
Jaroslav Kysela
parent
fc20773329
commit
d91c64c827
File diff suppressed because it is too large
Load Diff
@ -1,19 +1,17 @@
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#ifndef __SOUND_AZF3328_H
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#define __SOUND_AZF3328_H
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#ifndef __SOUND_AZT3328_H
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#define __SOUND_AZT3328_H
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/* type argument to use for the I/O functions */
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#define WORD_VALUE 0x1000
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#define DWORD_VALUE 0x2000
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#define BYTE_VALUE 0x4000
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/* "PU" == "power-up value", as tested on PCI168 PCI rev. 10 */
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/*** main I/O area port indices ***/
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/* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */
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/* the driver initialisation suggests a layout of 3 main areas:
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* from 0x00 (playback), from 0x20 (recording) and from 0x40 (maybe DirectX
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* timer ???). and probably another area from 0x60 to 0x6f
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* (IRQ management, power management etc. ???). */
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/* playback area */
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#define IDX_IO_PLAY_FLAGS 0x00
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/* the driver initialisation suggests a layout of 4 main areas:
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* from 0x00 (playback), from 0x20 (recording) and from 0x40 (maybe MPU401??).
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* And another area from 0x60 to 0x6f (DirectX timer, IRQ management,
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* power management etc.???). */
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/** playback area **/
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#define IDX_IO_PLAY_FLAGS 0x00 /* PU:0x0000 */
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/* able to reactivate output after output muting due to 8/16bit
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* output change, just like 0x0002.
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* 0x0001 is the only bit that's able to start the DMA counter */
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@ -29,7 +27,7 @@
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#define DMA_EPILOGUE_SOMETHING 0x0010
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#define DMA_SOMETHING_ELSE 0x0020 /* ??? */
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#define SOMETHING_UNMODIFIABLE 0xffc0 /* unused ? not modifiable */
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#define IDX_IO_PLAY_IRQMASK 0x02
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#define IDX_IO_PLAY_IRQTYPE 0x02 /* PU:0x0001 */
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/* write back to flags in case flags are set, in order to ACK IRQ in handler
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* (bit 1 of port 0x64 indicates interrupt for one of these three types)
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* sometimes in this case it just writes 0xffff to globally ACK all IRQs
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@ -41,36 +39,39 @@
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#define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */
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#define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */
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#define IRQMASK_UNMODIFIABLE 0xffe0 /* unused ? not modifiable */
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#define IDX_IO_PLAY_DMA_START_1 0x04 /* start address of 1st DMA play area */
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#define IDX_IO_PLAY_DMA_START_2 0x08 /* start address of 2nd DMA play area */
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#define IDX_IO_PLAY_DMA_LEN_1 0x0c /* length of 1st DMA play area */
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#define IDX_IO_PLAY_DMA_LEN_2 0x0e /* length of 2nd DMA play area */
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#define IDX_IO_PLAY_DMA_CURRPOS 0x10 /* current DMA position */
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#define IDX_IO_PLAY_DMA_CURROFS 0x14 /* offset within current DMA play area */
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#define IDX_IO_PLAY_SOUNDFORMAT 0x16
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#define IDX_IO_PLAY_DMA_START_1 0x04 /* start address of 1st DMA play area, PU:0x00000000 */
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#define IDX_IO_PLAY_DMA_START_2 0x08 /* start address of 2nd DMA play area, PU:0x00000000 */
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#define IDX_IO_PLAY_DMA_LEN_1 0x0c /* length of 1st DMA play area, PU:0x0000 */
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#define IDX_IO_PLAY_DMA_LEN_2 0x0e /* length of 2nd DMA play area, PU:0x0000 */
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#define IDX_IO_PLAY_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */
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#define IDX_IO_PLAY_DMA_CURROFS 0x14 /* offset within current DMA play area, PU:0x0000 */
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#define IDX_IO_PLAY_SOUNDFORMAT 0x16 /* PU:0x0010 */
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/* all unspecified bits can't be modified */
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#define SOUNDFORMAT_FREQUENCY_MASK 0x000f
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#define SOUNDFORMAT_XTAL1 0x00
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#define SOUNDFORMAT_XTAL2 0x01
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/* all _SUSPECTED_ values are not used by Windows drivers, so we don't
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* have any hard facts, only rough measurements */
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#define SOUNDFORMAT_FREQ_SUSPECTED_4000 0x0c
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#define SOUNDFORMAT_FREQ_SUSPECTED_4800 0x0a
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#define SOUNDFORMAT_FREQ_5510 0x0d
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#define SOUNDFORMAT_FREQ_6620 0x0b
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#define SOUNDFORMAT_FREQ_8000 0x00 /* also 0x0e ? */
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#define SOUNDFORMAT_FREQ_9600 0x08
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#define SOUNDFORMAT_FREQ_SUSPECTED_12000 0x09
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#define SOUNDFORMAT_FREQ_11025 0x01 /* also 0x0f ? */
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#define SOUNDFORMAT_FREQ_16000 0x02
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#define SOUNDFORMAT_FREQ_22050 0x03
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#define SOUNDFORMAT_FREQ_32000 0x04
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#define SOUNDFORMAT_FREQ_44100 0x05
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#define SOUNDFORMAT_FREQ_48000 0x06
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#define SOUNDFORMAT_FREQ_SUSPECTED_64000 0x07
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#define SOUNDFORMAT_FREQ_SUSPECTED_4000 0x0c | SOUNDFORMAT_XTAL1
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#define SOUNDFORMAT_FREQ_SUSPECTED_4800 0x0a | SOUNDFORMAT_XTAL1
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#define SOUNDFORMAT_FREQ_5510 0x0c | SOUNDFORMAT_XTAL2
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#define SOUNDFORMAT_FREQ_6620 0x0a | SOUNDFORMAT_XTAL2
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#define SOUNDFORMAT_FREQ_8000 0x00 | SOUNDFORMAT_XTAL1 /* also 0x0e | SOUNDFORMAT_XTAL1? */
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#define SOUNDFORMAT_FREQ_9600 0x08 | SOUNDFORMAT_XTAL1
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#define SOUNDFORMAT_FREQ_11025 0x00 | SOUNDFORMAT_XTAL2 /* also 0x0e | SOUNDFORMAT_XTAL2? */
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#define SOUNDFORMAT_FREQ_SUSPECTED_13240 0x08 | SOUNDFORMAT_XTAL2 /* seems to be 6620 *2 */
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#define SOUNDFORMAT_FREQ_16000 0x02 | SOUNDFORMAT_XTAL1
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#define SOUNDFORMAT_FREQ_22050 0x02 | SOUNDFORMAT_XTAL2
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#define SOUNDFORMAT_FREQ_32000 0x04 | SOUNDFORMAT_XTAL1
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#define SOUNDFORMAT_FREQ_44100 0x04 | SOUNDFORMAT_XTAL2
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#define SOUNDFORMAT_FREQ_48000 0x06 | SOUNDFORMAT_XTAL1
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#define SOUNDFORMAT_FREQ_SUSPECTED_66200 0x06 | SOUNDFORMAT_XTAL2 /* 66200 (13240 * 5); 64000 may have been nicer :-\ */
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#define SOUNDFORMAT_FLAG_16BIT 0x0010
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#define SOUNDFORMAT_FLAG_2CHANNELS 0x0020
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/* recording area (see also: playback bit flag definitions) */
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#define IDX_IO_REC_FLAGS 0x20 /* ?? */
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#define IDX_IO_REC_IRQMASK 0x22 /* ?? */
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/** recording area (see also: playback bit flag definitions) **/
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#define IDX_IO_REC_FLAGS 0x20 /* ??, PU:0x0000 */
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#define IDX_IO_REC_IRQTYPE 0x22 /* ??, PU:0x0000 */
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#define IRQ_REC_SOMETHING 0x0001 /* something & ACK */
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#define IRQ_FINISHED_RECBUF_1 0x0002 /* 1st dmabuf finished & ACK */
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#define IRQ_FINISHED_RECBUF_2 0x0004 /* 2nd dmabuf finished & ACK */
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@ -78,39 +79,47 @@
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* but OTOH they are most likely at port 0x22 instead */
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#define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */
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#define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */
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#define IDX_IO_REC_DMA_START_1 0x24
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#define IDX_IO_REC_DMA_START_2 0x28
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#define IDX_IO_REC_DMA_LEN_1 0x2c
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#define IDX_IO_REC_DMA_LEN_2 0x2e
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#define IDX_IO_REC_DMA_CURRPOS 0x30
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#define IDX_IO_REC_DMA_CURROFS 0x34
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#define IDX_IO_REC_SOUNDFORMAT 0x36
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/* some third area ? (after playback and recording) */
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#define IDX_IO_SOMETHING_FLAGS 0x40 /* gets set to 0x34 just like port 0x0 and 0x20 on card init */
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#define IDX_IO_REC_DMA_START_1 0x24 /* PU:0x00000000 */
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#define IDX_IO_REC_DMA_START_2 0x28 /* PU:0x00000000 */
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#define IDX_IO_REC_DMA_LEN_1 0x2c /* PU:0x0000 */
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#define IDX_IO_REC_DMA_LEN_2 0x2e /* PU:0x0000 */
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#define IDX_IO_REC_DMA_CURRPOS 0x30 /* PU:0x00000000 */
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#define IDX_IO_REC_DMA_CURROFS 0x34 /* PU:0x00000000 */
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#define IDX_IO_REC_SOUNDFORMAT 0x36 /* PU:0x0000 */
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/** hmm, what is this I/O area for? MPU401?? (after playback, recording, ???, timer) **/
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#define IDX_IO_SOMETHING_FLAGS 0x40 /* gets set to 0x34 just like port 0x0 and 0x20 on card init, PU:0x0000 */
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/* general */
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#define IDX_IO_60H 0x60 /* writing 0xffff returns 0xffff */
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#define IDX_IO_62H 0x62 /* writing to WORD 0x0062 can hang the box ! --> responsible for IRQ management as a whole ?? */
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#define IDX_IO_IRQ63H 0x63 /* FIXME !! */
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#define IO_IRQ63H_SOMETHING 0x04 /* being set in IRQ handler in case port 0x00 had 0x0020 set upon IRQ handler */
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#define IDX_IO_42H 0x42 /* PU:0x0001 */
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/** DirectX timer, main interrupt area (FIXME: and something else?) **/
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#define IDX_IO_TIMER_VALUE 0x60 /* found this timer area by pure luck :-) */
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#define TIMER_VALUE_MASK 0x000fffffUL /* timer countdown value; triggers IRQ when timer is finished */
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#define TIMER_ENABLE_COUNTDOWN 0x01000000UL /* activate the timer countdown */
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#define TIMER_ENABLE_IRQ 0x02000000UL /* trigger timer IRQ on zero transition */
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#define TIMER_ACK_IRQ 0x04000000UL /* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?) had 0x0020 set upon IRQ handler */
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#define IDX_IO_IRQSTATUS 0x64
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#define IRQ_PLAYBACK 0x0001
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#define IRQ_RECORDING 0x0002
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#define IRQ_MPU401 0x0010
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#define IRQ_SOMEIRQ 0x0020 /* ???? */
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#define IRQ_WHO_KNOWS_UNUSED 0x00e0 /* probably unused */
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#define IRQ_TIMER 0x0020 /* DirectX timer */
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#define IRQ_UNKNOWN1 0x0040 /* probably unused */
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#define IRQ_UNKNOWN2 0x0080 /* probably unused */
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#define IDX_IO_66H 0x66 /* writing 0xffff returns 0x0000 */
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#define IDX_IO_SOME_VALUE 0x68 /* this is always set to 0x3ff, and writable; maybe some buffer limit, but I couldn't find out more */
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#define IDX_IO_6AH 0x6A /* this WORD can be set to have bits 0x0028 activated; actually inhibits PCM playback !!! maybe power management ?? */
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#define IDX_IO_6CH 0x6C /* this WORD can have all its bits activated ? */
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#define IDX_IO_SOME_VALUE 0x68 /* this is set to e.g. 0x3ff or 0x300, and writable; maybe some buffer limit, but I couldn't find out more, PU:0x00ff */
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#define IDX_IO_6AH 0x6A /* this WORD can be set to have bits 0x0028 activated; actually inhibits PCM playback!!! maybe power management?? */
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#define IDX_IO_6CH 0x6C
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#define IDX_IO_6EH 0x6E /* writing 0xffff returns 0x83fe */
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/* further I/O indices not saved/restored, so probably not used */
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/*** I/O 2 area port indices ***/
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/* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */
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#define IDX_IO2_LEGACY_ADDR 0x04
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#define LEGACY_SOMETHING 0x01 /* OPL3 ?? */
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#define LEGACY_SOMETHING 0x01 /* OPL3?? */
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#define LEGACY_JOY 0x08
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/*** mixer I/O area port indices ***/
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/* (only 0x22 of 0x40 bytes saved/restored by Windows driver)
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* generally spoken: AC97 register index = AZF3328 mixer reg index + 2
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@ -148,18 +157,18 @@
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/* unlisted bits are unmodifiable */
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#define MIXER_ADVCTL1_3DWIDTH_MASK 0x000e
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#define MIXER_ADVCTL1_HIFI3D_MASK 0x0300
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#define IDX_MIXER_ADVCTL2 0x20 /* resembles AC97_GENERAL_PURPOSE reg ! */
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#define IDX_MIXER_ADVCTL2 0x20 /* resembles AC97_GENERAL_PURPOSE reg! */
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/* unlisted bits are unmodifiable */
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#define MIXER_ADVCTL2_BIT7 0x0080 /* WaveOut 3D Bypass ? mutes WaveOut at LineOut */
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#define MIXER_ADVCTL2_BIT8 0x0100 /* is this Modem Out Select ? */
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#define MIXER_ADVCTL2_BIT9 0x0200 /* Mono Select Source ? */
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#define MIXER_ADVCTL2_BIT13 0x2000 /* 3D enable ? */
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#define MIXER_ADVCTL2_BIT7 0x0080 /* WaveOut 3D Bypass? mutes WaveOut at LineOut */
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#define MIXER_ADVCTL2_BIT8 0x0100 /* is this Modem Out Select? */
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#define MIXER_ADVCTL2_BIT9 0x0200 /* Mono Select Source? */
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#define MIXER_ADVCTL2_BIT13 0x2000 /* 3D enable? */
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#define MIXER_ADVCTL2_BIT15 0x8000 /* unknown */
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#define IDX_MIXER_SOMETHING30H 0x30 /* used, but unknown ??? */
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#define IDX_MIXER_SOMETHING30H 0x30 /* used, but unknown??? */
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/* driver internal flags */
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#define SET_CHAN_LEFT 1
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#define SET_CHAN_RIGHT 2
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#endif /* __SOUND_AZF3328_H */
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#endif /* __SOUND_AZT3328_H */
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