drm/radeon/kms: fill in GPU init for AMD Ontario Fusion APUs
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -1299,6 +1299,7 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
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switch (rdev->family) {
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case CHIP_CEDAR:
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case CHIP_REDWOOD:
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case CHIP_PALM:
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force_no_swizzle = false;
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break;
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case CHIP_CYPRESS:
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@ -1423,6 +1424,7 @@ static void evergreen_program_channel_remap(struct radeon_device *rdev)
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case CHIP_JUNIPER:
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case CHIP_REDWOOD:
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case CHIP_CEDAR:
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case CHIP_PALM:
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default:
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tcp_chan_steer_lo = 0x76543210;
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tcp_chan_steer_hi = 0x0000ba98;
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@ -1541,6 +1543,27 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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rdev->config.evergreen.max_hw_contexts = 4;
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rdev->config.evergreen.sq_num_cf_insts = 1;
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rdev->config.evergreen.sc_prim_fifo_size = 0x40;
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rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
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rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
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break;
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case CHIP_PALM:
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rdev->config.evergreen.num_ses = 1;
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rdev->config.evergreen.max_pipes = 2;
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rdev->config.evergreen.max_tile_pipes = 2;
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rdev->config.evergreen.max_simds = 2;
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rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
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rdev->config.evergreen.max_gprs = 256;
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rdev->config.evergreen.max_threads = 192;
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rdev->config.evergreen.max_gs_threads = 16;
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rdev->config.evergreen.max_stack_entries = 256;
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rdev->config.evergreen.sx_num_of_sets = 4;
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rdev->config.evergreen.sx_max_export_size = 128;
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rdev->config.evergreen.sx_max_export_pos_size = 32;
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rdev->config.evergreen.sx_max_export_smx_size = 96;
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rdev->config.evergreen.max_hw_contexts = 4;
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rdev->config.evergreen.sq_num_cf_insts = 1;
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rdev->config.evergreen.sc_prim_fifo_size = 0x40;
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rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
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rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
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@ -1821,9 +1844,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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GS_PRIO(2) |
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ES_PRIO(3));
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if (rdev->family == CHIP_CEDAR)
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switch (rdev->family) {
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case CHIP_CEDAR:
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case CHIP_PALM:
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/* no vertex cache */
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sq_config &= ~VC_ENABLE;
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break;
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default:
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break;
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}
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sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
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@ -1835,10 +1864,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
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sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
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if (rdev->family == CHIP_CEDAR)
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switch (rdev->family) {
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case CHIP_CEDAR:
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case CHIP_PALM:
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ps_thread_count = 96;
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else
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break;
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default:
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ps_thread_count = 128;
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break;
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}
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sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
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sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
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@ -1869,10 +1903,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
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FORCE_EOV_MAX_REZ_CNT(255)));
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if (rdev->family == CHIP_CEDAR)
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switch (rdev->family) {
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case CHIP_CEDAR:
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case CHIP_PALM:
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vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
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else
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break;
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default:
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vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
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break;
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}
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vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
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WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
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