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powerpc/time: Move timebase functions into new asm/vdso/timebase.h

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In order to easily use get_tb() from C VDSO, move timebase
functions into a new header named asm/vdso/timebase.h

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201126131006.2431205-3-mpe@ellerman.id.au
This commit is contained in:
Christophe Leroy
2020-11-27 00:10:00 +11:00
committed by Michael Ellerman
parent 8f8cffd9df
commit d26b3817d9
4 changed files with 73 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
arch/powerpc/include/asm/reg.h
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@@ -1419,37 +1419,6 @@ static inline void msr_check_and_clear(unsigned long bits)
__msr_check_and_clear(bits); __msr_check_and_clear(bits);
} }
#if defined(CONFIG_PPC_CELL) || defined(CONFIG_E500)
#define mftb() ({unsigned long rval; \
asm volatile( \
"90: mfspr %0, %2;\n" \
ASM_FTR_IFSET( \
"97: cmpwi %0,0;\n" \
" beq- 90b;\n", "", %1) \
: "=r" (rval) \
: "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
rval;})
#elif defined(CONFIG_PPC_8xx)
#define mftb() ({unsigned long rval; \
asm volatile("mftbl %0" : "=r" (rval)); rval;})
#else
#define mftb() ({unsigned long rval; \
asm volatile("mfspr %0, %1" : \
"=r" (rval) : "i" (SPRN_TBRL)); rval;})
#endif /* !CONFIG_PPC_CELL */
#if defined(CONFIG_PPC_8xx)
#define mftbu() ({unsigned long rval; \
asm volatile("mftbu %0" : "=r" (rval)); rval;})
#else
#define mftbu() ({unsigned long rval; \
asm volatile("mfspr %0, %1" : "=r" (rval) : \
"i" (SPRN_TBRU)); rval;})
#endif
#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
#ifdef CONFIG_PPC32 #ifdef CONFIG_PPC32
#define mfsrin(v) ({unsigned int rval; \ #define mfsrin(v) ({unsigned int rval; \
asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \ asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \

30
arch/powerpc/include/asm/time.h
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@@ -15,6 +15,7 @@
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/cpu_has_feature.h> #include <asm/cpu_has_feature.h>
#include <asm/vdso/timebase.h>
/* time.c */ /* time.c */
extern unsigned long tb_ticks_per_jiffy; extern unsigned long tb_ticks_per_jiffy;
@@ -38,12 +39,6 @@ struct div_result {
u64 result_low; u64 result_low;
}; };
/* For compatibility, get_tbl() is defined as get_tb() on ppc64 */
static inline unsigned long get_tbl(void)
{
return mftb();
}
static inline u64 get_vtb(void) static inline u64 get_vtb(void)
{ {
#ifdef CONFIG_PPC_BOOK3S_64 #ifdef CONFIG_PPC_BOOK3S_64
@@ -53,29 +48,6 @@ static inline u64 get_vtb(void)
return 0; return 0;
} }
static inline u64 get_tb(void)
{
unsigned int tbhi, tblo, tbhi2;
if (IS_ENABLED(CONFIG_PPC64))
return mftb();
do {
tbhi = mftbu();
tblo = mftb();
tbhi2 = mftbu();
} while (tbhi != tbhi2);
return ((u64)tbhi << 32) | tblo;
}
static inline void set_tb(unsigned int upper, unsigned int lower)
{
mtspr(SPRN_TBWL, 0);
mtspr(SPRN_TBWU, upper);
mtspr(SPRN_TBWL, lower);
}
/* Accessor functions for the decrementer register. /* Accessor functions for the decrementer register.
* The 4xx doesn't even have a decrementer. I tried to use the * The 4xx doesn't even have a decrementer. I tried to use the
* generic timer interrupt code, which seems OK, with the 4xx PIT * generic timer interrupt code, which seems OK, with the 4xx PIT

2
arch/powerpc/include/asm/timex.h
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@@ -9,7 +9,7 @@
*/ */
#include <asm/cputable.h> #include <asm/cputable.h>
#include <asm/reg.h> #include <asm/vdso/timebase.h>
#define CLOCK_TICK_RATE 1024000 /* Underlying HZ */ #define CLOCK_TICK_RATE 1024000 /* Underlying HZ */

71
arch/powerpc/include/asm/vdso/timebase.h Normal file
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@@ -0,0 +1,71 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Common timebase prototypes and such for all ppc machines.
*/
#ifndef _ASM_POWERPC_VDSO_TIMEBASE_H
#define _ASM_POWERPC_VDSO_TIMEBASE_H
#include <asm/reg.h>
#if defined(CONFIG_PPC_CELL) || defined(CONFIG_E500)
#define mftb() ({unsigned long rval; \
asm volatile( \
"90: mfspr %0, %2;\n" \
ASM_FTR_IFSET( \
"97: cmpwi %0,0;\n" \
" beq- 90b;\n", "", %1) \
: "=r" (rval) \
: "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
rval;})
#elif defined(CONFIG_PPC_8xx)
#define mftb() ({unsigned long rval; \
asm volatile("mftbl %0" : "=r" (rval)); rval;})
#else
#define mftb() ({unsigned long rval; \
asm volatile("mfspr %0, %1" : \
"=r" (rval) : "i" (SPRN_TBRL)); rval;})
#endif /* !CONFIG_PPC_CELL */
#if defined(CONFIG_PPC_8xx)
#define mftbu() ({unsigned long rval; \
asm volatile("mftbu %0" : "=r" (rval)); rval;})
#else
#define mftbu() ({unsigned long rval; \
asm volatile("mfspr %0, %1" : "=r" (rval) : \
"i" (SPRN_TBRU)); rval;})
#endif
#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
/* For compatibility, get_tbl() is defined as get_tb() on ppc64 */
static inline unsigned long get_tbl(void)
{
return mftb();
}
static inline u64 get_tb(void)
{
unsigned int tbhi, tblo, tbhi2;
if (IS_ENABLED(CONFIG_PPC64))
return mftb();
do {
tbhi = mftbu();
tblo = mftb();
tbhi2 = mftbu();
} while (tbhi != tbhi2);
return ((u64)tbhi << 32) | tblo;
}
static inline void set_tb(unsigned int upper, unsigned int lower)
{
mtspr(SPRN_TBWL, 0);
mtspr(SPRN_TBWU, upper);
mtspr(SPRN_TBWL, lower);
}
#endif /* _ASM_POWERPC_VDSO_TIMEBASE_H */