ASoC: tlv320aic32x4: Control clock gating with CCF
Control the clock gating to the various clock components to use the CCF. This allows us to prepare_enalbe only 3 clocks and the relationships assigned to them will cause upstream clockss to enable automatically. Additionally we can do this in a single call to the CCF. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -834,41 +834,25 @@ static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
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static int aic32x4_set_bias_level(struct snd_soc_component *component,
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enum snd_soc_bias_level level)
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{
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struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
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int ret;
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struct clk_bulk_data clocks[] = {
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{ .id = "madc" },
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{ .id = "mdac" },
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{ .id = "bdiv" },
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};
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ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
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if (ret)
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return ret;
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switch (level) {
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case SND_SOC_BIAS_ON:
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/* Switch on master clock */
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ret = clk_prepare_enable(aic32x4->mclk);
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ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
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if (ret) {
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dev_err(component->dev, "Failed to enable master clock\n");
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dev_err(component->dev, "Failed to enable clocks\n");
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return ret;
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}
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/* Switch on PLL */
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snd_soc_component_update_bits(component, AIC32X4_PLLPR,
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AIC32X4_PLLEN, AIC32X4_PLLEN);
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/* Switch on NDAC Divider */
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snd_soc_component_update_bits(component, AIC32X4_NDAC,
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AIC32X4_NDACEN, AIC32X4_NDACEN);
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/* Switch on MDAC Divider */
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snd_soc_component_update_bits(component, AIC32X4_MDAC,
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AIC32X4_MDACEN, AIC32X4_MDACEN);
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/* Switch on NADC Divider */
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snd_soc_component_update_bits(component, AIC32X4_NADC,
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AIC32X4_NADCEN, AIC32X4_NADCEN);
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/* Switch on MADC Divider */
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snd_soc_component_update_bits(component, AIC32X4_MADC,
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AIC32X4_MADCEN, AIC32X4_MADCEN);
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/* Switch on BCLK_N Divider */
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snd_soc_component_update_bits(component, AIC32X4_BCLKN,
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AIC32X4_BCLKEN, AIC32X4_BCLKEN);
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break;
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case SND_SOC_BIAS_PREPARE:
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break;
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@ -877,32 +861,7 @@ static int aic32x4_set_bias_level(struct snd_soc_component *component,
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if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
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break;
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/* Switch off BCLK_N Divider */
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snd_soc_component_update_bits(component, AIC32X4_BCLKN,
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AIC32X4_BCLKEN, 0);
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/* Switch off MADC Divider */
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snd_soc_component_update_bits(component, AIC32X4_MADC,
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AIC32X4_MADCEN, 0);
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/* Switch off NADC Divider */
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snd_soc_component_update_bits(component, AIC32X4_NADC,
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AIC32X4_NADCEN, 0);
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/* Switch off MDAC Divider */
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snd_soc_component_update_bits(component, AIC32X4_MDAC,
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AIC32X4_MDACEN, 0);
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/* Switch off NDAC Divider */
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snd_soc_component_update_bits(component, AIC32X4_NDAC,
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AIC32X4_NDACEN, 0);
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/* Switch off PLL */
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snd_soc_component_update_bits(component, AIC32X4_PLLPR,
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AIC32X4_PLLEN, 0);
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/* Switch off master clock */
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clk_disable_unprepare(aic32x4->mclk);
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clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
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break;
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case SND_SOC_BIAS_OFF:
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break;
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