forked from Minki/linux
ARM: at91: Add at91sam9n12 and refence booard
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPmtqrAAoJEOrjwV5ZMRf2FlsP/29/+UAb14HJZrvauvZzB0G8 DXX+vTB/+9xtbQravdT3nqrsoI+8sFm4Df14RSDXYnlEanGS7LsatYycp+S0LZEM QFBlRPdrP+t6GtwZbckClBpTxwrCHhq6rLpbVd3McA7/zGe6sjlZRaGB/s4RXKvK aAVIKJOpQARfnDwSBGpFvxt5LqvrKxJkJ3LcI87hqsJCe27R1xBUwaQfrhFvWk4M W8IELkrdMvBSY3hybJRGB2Bc8hjnOvgY9Gqcpu9oOkXMoGcyO2bKpMh0p/nXiZXb CNnuCedhrYpbBG0tVbgHxHCQdwece/hgzWPn5a32HYolAzHZNFUGqWqC43uXglZw ZdAMV1kYXv+lh7rpAHkm595ngvX8VuaNXTvU6/pU6RI/E44BsgUYTSeoabbjqq/g pDkX0ZDBL44z0Zfkbkpw+fbrOXdbZtVzmjBbmsCMHuqUcecLtHN3LERpMWi99+Bh FfyGl7gko6VfZvCUgGPb/Iuc42buikk8xNS2iMyPK7vbyEXi7hDOCS+ExyFWDE1K 4/FXXr9OXhCroTYBwHKLfUdTti/79cz8yd6xHfWDUsIflrYSLV2l5sCO0pP/D6Vy szmpE6/w5DnpuWOfB1g+tWBgfGuUII2KucbfOGDx/vGj2ADmauUwEPypEqgHDJZf dsVv7JtXtMWBEZGTC/b6 =+0yg -----END PGP SIGNATURE----- Merge tag 'at91-for-next-soc' of git://github.com/at91linux/linux-at91 into next/newsoc ARM: at91: Add at91sam9n12 and refence booard * tag 'at91-for-next-soc' of git://github.com/at91linux/linux-at91: ARM: at91: Add DT description files for AT91SAM9N12-EK ARM: at91: Add machine files for AT91SAM9N12 SoC ARM: at91: Add machine header file for AT91SAM9N12 SoC Based on at91/dt branch. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
d1ef5bd711
221
arch/arm/boot/dts/at91sam9n12.dtsi
Normal file
221
arch/arm/boot/dts/at91sam9n12.dtsi
Normal file
@ -0,0 +1,221 @@
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/*
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* at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
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*
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* Copyright (C) 2012 Atmel,
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* 2012 Hong Xu <hong.xu@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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/include/ "skeleton.dtsi"
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/ {
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model = "Atmel AT91SAM9N12 SoC";
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compatible = "atmel,at91sam9n12";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &dbgu;
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serial1 = &usart0;
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serial2 = &usart1;
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serial3 = &usart2;
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serial4 = &usart3;
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gpio0 = &pioA;
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gpio1 = &pioB;
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gpio2 = &pioC;
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gpio3 = &pioD;
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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};
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cpus {
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cpu@0 {
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compatible = "arm,arm926ejs";
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};
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};
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memory {
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reg = <0x20000000 0x10000000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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aic: interrupt-controller@fffff000 {
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#interrupt-cells = <2>;
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compatible = "atmel,at91rm9200-aic";
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interrupt-controller;
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reg = <0xfffff000 0x200>;
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};
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ramc0: ramc@ffffe800 {
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compatible = "atmel,at91sam9g45-ddramc";
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reg = <0xffffe800 0x200>;
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};
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pmc: pmc@fffffc00 {
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compatible = "atmel,at91rm9200-pmc";
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reg = <0xfffffc00 0x100>;
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};
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rstc@fffffe00 {
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compatible = "atmel,at91sam9g45-rstc";
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reg = <0xfffffe00 0x10>;
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};
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pit: timer@fffffe30 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffe30 0xf>;
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interrupts = <1 4>;
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};
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shdwc@fffffe10 {
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compatible = "atmel,at91sam9x5-shdwc";
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reg = <0xfffffe10 0x10>;
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};
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tcb0: timer@f8008000 {
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compatible = "atmel,at91sam9x5-tcb";
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reg = <0xf8008000 0x100>;
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interrupts = <17 4>;
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};
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tcb1: timer@f800c000 {
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compatible = "atmel,at91sam9x5-tcb";
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reg = <0xf800c000 0x100>;
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interrupts = <17 4>;
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};
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dma: dma-controller@ffffec00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffec00 0x200>;
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interrupts = <20 4>;
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};
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pioA: gpio@fffff400 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffff400 0x100>;
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interrupts = <2 4>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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};
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pioB: gpio@fffff600 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffff600 0x100>;
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interrupts = <2 4>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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};
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pioC: gpio@fffff800 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffff800 0x100>;
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interrupts = <3 4>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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};
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pioD: gpio@fffffa00 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffffa00 0x100>;
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interrupts = <3 4>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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};
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dbgu: serial@fffff200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfffff200 0x200>;
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interrupts = <1 4>;
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status = "disabled";
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};
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usart0: serial@f801c000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf801c000 0x4000>;
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interrupts = <5 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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usart1: serial@f8020000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf8020000 0x4000>;
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interrupts = <6 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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usart2: serial@f8024000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf8024000 0x4000>;
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interrupts = <7 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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usart3: serial@f8028000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf8028000 0x4000>;
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interrupts = <8 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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};
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nand0: nand@40000000 {
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compatible = "atmel,at91rm9200-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = < 0x40000000 0x10000000
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0xffffe000 0x00000600
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0xffffe600 0x00000200
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0x00100000 0x00100000
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>;
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atmel,nand-addr-offset = <21>;
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atmel,nand-cmd-offset = <22>;
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gpios = <&pioD 5 0
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&pioD 4 0
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0
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>;
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status = "disabled";
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};
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usb0: ohci@00500000 {
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compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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reg = <0x00500000 0x00100000>;
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interrupts = <22 4>;
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status = "disabled";
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};
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};
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i2c@0 {
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compatible = "i2c-gpio";
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gpios = <&pioA 30 0 /* sda */
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&pioA 31 0 /* scl */
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>;
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i2c-gpio,sda-open-drain;
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i2c-gpio,scl-open-drain;
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i2c-gpio,delay-us = <2>; /* ~100 kHz */
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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84
arch/arm/boot/dts/at91sam9n12ek.dts
Normal file
84
arch/arm/boot/dts/at91sam9n12ek.dts
Normal file
@ -0,0 +1,84 @@
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/*
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* at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board
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*
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* Copyright (C) 2012 Atmel,
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* 2012 Hong Xu <hong.xu@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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/dts-v1/;
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/include/ "at91sam9n12.dtsi"
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/ {
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model = "Atmel AT91SAM9N12-EK";
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compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9";
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chosen {
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bootargs = "mem=128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
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};
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memory {
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reg = <0x20000000 0x10000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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main_clock: clock@0 {
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compatible = "atmel,osc", "fixed-clock";
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clock-frequency = <16000000>;
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};
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};
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ahb {
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apb {
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dbgu: serial@fffff200 {
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status = "okay";
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};
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};
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nand0: nand@40000000 {
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nand-bus-width = <8>;
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nand-ecc-mode = "soft";
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nand-on-flash-bbt;
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status = "okay";
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};
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};
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leds {
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compatible = "gpio-leds";
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d8 {
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label = "d8";
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gpios = <&pioB 4 1>;
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linux,default-trigger = "mmc0";
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};
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d9 {
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label = "d6";
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gpios = <&pioB 5 1>;
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linux,default-trigger = "nand-disk";
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};
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d10 {
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label = "d7";
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gpios = <&pioB 6 0>;
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linux,default-trigger = "heartbeat";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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enter {
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label = "Enter";
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gpios = <&pioB 4 1>;
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linux,code = <28>;
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gpio-key,wakeup;
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};
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};
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};
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@ -91,6 +91,14 @@ config SOC_AT91SAM9X5
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This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35
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and AT91SAM9X35.
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config SOC_AT91SAM9N12
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bool "AT91SAM9N12 family"
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select SOC_AT91SAM9
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select HAVE_AT91_DBGU0
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select HAVE_FB_ATMEL
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help
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Select this if you are using Atmel's AT91SAM9N12 SoC.
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choice
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prompt "Atmel AT91 Processor Devices for non DT boards"
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@ -18,6 +18,7 @@ obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o
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obj-$(CONFIG_SOC_AT91SAM9261) += at91sam9261.o
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obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o
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obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o
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obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o
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obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o
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obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
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@ -30,5 +30,7 @@ dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb
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dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
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# sam9g45
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dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
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# sam9n12
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dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9n12ek.dtb
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# sam9x5
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dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
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233
arch/arm/mach-at91/at91sam9n12.c
Normal file
233
arch/arm/mach-at91/at91sam9n12.c
Normal file
@ -0,0 +1,233 @@
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/*
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* SoC specific setup code for the AT91SAM9N12
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*
|
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* Copyright (C) 2012 Atmel Corporation.
|
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*
|
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* Licensed under GPLv2 or later.
|
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*/
|
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/at91sam9n12.h>
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#include <mach/at91_pmc.h>
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#include <mach/cpu.h>
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#include <mach/board.h>
|
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|
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#include "soc.h"
|
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#include "generic.h"
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#include "clock.h"
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#include "sam9_smc.h"
|
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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||||
|
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/*
|
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* The peripheral clocks.
|
||||
*/
|
||||
static struct clk pioAB_clk = {
|
||||
.name = "pioAB_clk",
|
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.pmc_mask = 1 << AT91SAM9N12_ID_PIOAB,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pioCD_clk = {
|
||||
.name = "pioCD_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_PIOCD,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart0_clk = {
|
||||
.name = "usart0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_USART0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart1_clk = {
|
||||
.name = "usart1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_USART1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart2_clk = {
|
||||
.name = "usart2_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_USART2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart3_clk = {
|
||||
.name = "usart3_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_USART3,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi0_clk = {
|
||||
.name = "twi0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_TWI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi1_clk = {
|
||||
.name = "twi1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_TWI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk mmc_clk = {
|
||||
.name = "mci_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_MCI,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi0_clk = {
|
||||
.name = "spi0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_SPI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi1_clk = {
|
||||
.name = "spi1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_SPI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uart0_clk = {
|
||||
.name = "uart0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_UART0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uart1_clk = {
|
||||
.name = "uart1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_UART1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk tcb_clk = {
|
||||
.name = "tcb_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_TCB,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pwm_clk = {
|
||||
.name = "pwm_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_PWM,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk adc_clk = {
|
||||
.name = "adc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_ADC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk dma_clk = {
|
||||
.name = "dma_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_DMA,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uhp_clk = {
|
||||
.name = "uhp",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_UHP,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk udp_clk = {
|
||||
.name = "udp_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_UDP,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk lcdc_clk = {
|
||||
.name = "lcdc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_LCDC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ssc_clk = {
|
||||
.name = "ssc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_SSC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
|
||||
static struct clk *periph_clocks[] __initdata = {
|
||||
&pioAB_clk,
|
||||
&pioCD_clk,
|
||||
&usart0_clk,
|
||||
&usart1_clk,
|
||||
&usart2_clk,
|
||||
&usart3_clk,
|
||||
&twi0_clk,
|
||||
&twi1_clk,
|
||||
&mmc_clk,
|
||||
&spi0_clk,
|
||||
&spi1_clk,
|
||||
&lcdc_clk,
|
||||
&uart0_clk,
|
||||
&uart1_clk,
|
||||
&tcb_clk,
|
||||
&pwm_clk,
|
||||
&adc_clk,
|
||||
&dma_clk,
|
||||
&uhp_clk,
|
||||
&udp_clk,
|
||||
&ssc_clk,
|
||||
};
|
||||
|
||||
static struct clk_lookup periph_clocks_lookups[] = {
|
||||
/* lookup table for DT entries */
|
||||
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
|
||||
CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
|
||||
CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
|
||||
CLKDEV_CON_ID("pioA", &pioAB_clk),
|
||||
CLKDEV_CON_ID("pioB", &pioAB_clk),
|
||||
CLKDEV_CON_ID("pioC", &pioCD_clk),
|
||||
CLKDEV_CON_ID("pioD", &pioCD_clk),
|
||||
/* additional fake clock for macb_hclk */
|
||||
CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
|
||||
CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
|
||||
};
|
||||
|
||||
/*
|
||||
* The two programmable clocks.
|
||||
* You must configure pin multiplexing to bring these signals out.
|
||||
*/
|
||||
static struct clk pck0 = {
|
||||
.name = "pck0",
|
||||
.pmc_mask = AT91_PMC_PCK0,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 0,
|
||||
};
|
||||
static struct clk pck1 = {
|
||||
.name = "pck1",
|
||||
.pmc_mask = AT91_PMC_PCK1,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 1,
|
||||
};
|
||||
|
||||
static void __init at91sam9n12_register_clocks(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
|
||||
clk_register(periph_clocks[i]);
|
||||
clk_register(&pck0);
|
||||
clk_register(&pck1);
|
||||
|
||||
clkdev_add_table(periph_clocks_lookups,
|
||||
ARRAY_SIZE(periph_clocks_lookups));
|
||||
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* AT91SAM9N12 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init at91sam9n12_map_io(void)
|
||||
{
|
||||
at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
|
||||
}
|
||||
|
||||
void __init at91sam9n12_initialize(void)
|
||||
{
|
||||
at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
|
||||
|
||||
/* Register GPIO subsystem (using DT) */
|
||||
at91_gpio_init(NULL, 0);
|
||||
}
|
||||
|
||||
struct at91_init_soc __initdata at91sam9n12_soc = {
|
||||
.map_io = at91sam9n12_map_io,
|
||||
.register_clocks = at91sam9n12_register_clocks,
|
||||
.init = at91sam9n12_initialize,
|
||||
};
|
||||
@ -57,13 +57,15 @@ void __iomem *at91_pmc_base;
|
||||
|
||||
#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12())
|
||||
|
||||
#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
|
||||
|
||||
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5()))
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12()))
|
||||
|
||||
#define cpu_has_upll() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
@ -77,12 +79,15 @@ void __iomem *at91_pmc_base;
|
||||
|| cpu_is_at91sam9x5()))
|
||||
|
||||
#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12())
|
||||
|
||||
#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12())
|
||||
|
||||
#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
|
||||
#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12())
|
||||
|
||||
static LIST_HEAD(clocks);
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
|
||||
60
arch/arm/mach-at91/include/mach/at91sam9n12.h
Normal file
60
arch/arm/mach-at91/include/mach/at91sam9n12.h
Normal file
@ -0,0 +1,60 @@
|
||||
/*
|
||||
* SoC specific header file for the AT91SAM9N12
|
||||
*
|
||||
* Copyright (C) 2012 Atmel Corporation
|
||||
*
|
||||
* Common definitions, based on AT91SAM9N12 SoC datasheet
|
||||
*
|
||||
* Licensed under GPLv2 or later
|
||||
*/
|
||||
|
||||
#ifndef _AT91SAM9N12_H_
|
||||
#define _AT91SAM9N12_H_
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
|
||||
#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
|
||||
#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */
|
||||
#define AT91SAM9N12_ID_USART0 5 /* USART 0 */
|
||||
#define AT91SAM9N12_ID_USART1 6 /* USART 1 */
|
||||
#define AT91SAM9N12_ID_USART2 7 /* USART 2 */
|
||||
#define AT91SAM9N12_ID_USART3 8 /* USART 3 */
|
||||
#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */
|
||||
#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */
|
||||
#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */
|
||||
#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9N12_ID_UART0 15 /* UART 0 */
|
||||
#define AT91SAM9N12_ID_UART1 16 /* UART 1 */
|
||||
#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||
#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */
|
||||
#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */
|
||||
#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */
|
||||
#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */
|
||||
#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */
|
||||
#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */
|
||||
#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */
|
||||
#define AT91SAM9N12_ID_TRNG 30 /* TRNG */
|
||||
#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9N12_BASE_USART0 0xf801c000
|
||||
#define AT91SAM9N12_BASE_USART1 0xf8020000
|
||||
#define AT91SAM9N12_BASE_USART2 0xf8024000
|
||||
#define AT91SAM9N12_BASE_USART3 0xf8028000
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
|
||||
|
||||
#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */
|
||||
#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
|
||||
|
||||
#endif
|
||||
53
arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
Normal file
53
arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Matrix-centric header file for the AT91SAM9N12
|
||||
*
|
||||
* Copyright (C) 2012 Atmel Corporation.
|
||||
*
|
||||
* Only EBI related registers.
|
||||
* Write Protect register definitions may be useful.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _AT91SAM9N12_MATRIX_H_
|
||||
#define _AT91SAM9N12_MATRIX_H_
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||
#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
|
||||
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
|
||||
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
|
||||
#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
|
||||
#define AT91_MATRIX_MP_OFF (0 << 25)
|
||||
#define AT91_MATRIX_MP_ON (1 << 25)
|
||||
|
||||
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
|
||||
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||
|
||||
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
|
||||
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||
|
||||
#endif
|
||||
@ -25,6 +25,7 @@
|
||||
#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
|
||||
#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
|
||||
#define ARCH_ID_AT91SAM9X5 0x819a05a0
|
||||
#define ARCH_ID_AT91SAM9N12 0x819a07a0
|
||||
|
||||
#define ARCH_ID_AT91SAM9XE128 0x329973a0
|
||||
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
|
||||
@ -71,6 +72,9 @@ enum at91_soc_type {
|
||||
/* SAM9X5 */
|
||||
AT91_SOC_SAM9X5,
|
||||
|
||||
/* SAM9N12 */
|
||||
AT91_SOC_SAM9N12,
|
||||
|
||||
/* Unknown type */
|
||||
AT91_SOC_NONE
|
||||
};
|
||||
@ -177,6 +181,12 @@ static inline int at91_soc_is_detected(void)
|
||||
#define cpu_is_at91sam9x25() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AT91SAM9N12
|
||||
#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12)
|
||||
#else
|
||||
#define cpu_is_at91sam9n12() (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Since this is ARM, we will never run on any AVR32 CPU. But these
|
||||
* definitions may reduce clutter in common drivers.
|
||||
|
||||
@ -32,6 +32,7 @@
|
||||
#include <mach/at91sam9rl.h>
|
||||
#include <mach/at91sam9g45.h>
|
||||
#include <mach/at91sam9x5.h>
|
||||
#include <mach/at91sam9n12.h>
|
||||
|
||||
/*
|
||||
* On all at91 except rm9200 and x40 have the System Controller starts
|
||||
|
||||
@ -142,6 +142,11 @@ static void __init soc_detect(u32 dbgu_base)
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9X5;
|
||||
at91_boot_soc = at91sam9x5_soc;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9N12:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9N12;
|
||||
at91_boot_soc = at91sam9n12_soc;
|
||||
break;
|
||||
}
|
||||
|
||||
/* at91sam9g10 */
|
||||
@ -209,6 +214,7 @@ static const char *soc_name[] = {
|
||||
[AT91_SOC_SAM9G45] = "at91sam9g45",
|
||||
[AT91_SOC_SAM9RL] = "at91sam9rl",
|
||||
[AT91_SOC_SAM9X5] = "at91sam9x5",
|
||||
[AT91_SOC_SAM9N12] = "at91sam9n12",
|
||||
[AT91_SOC_NONE] = "Unknown"
|
||||
};
|
||||
|
||||
|
||||
@ -20,6 +20,7 @@ extern struct at91_init_soc at91sam9263_soc;
|
||||
extern struct at91_init_soc at91sam9g45_soc;
|
||||
extern struct at91_init_soc at91sam9rl_soc;
|
||||
extern struct at91_init_soc at91sam9x5_soc;
|
||||
extern struct at91_init_soc at91sam9n12_soc;
|
||||
|
||||
static inline int at91_soc_is_enabled(void)
|
||||
{
|
||||
@ -53,3 +54,7 @@ static inline int at91_soc_is_enabled(void)
|
||||
#if !defined(CONFIG_SOC_AT91SAM9X5)
|
||||
#define at91sam9x5_soc at91_boot_soc
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SOC_AT91SAM9N12)
|
||||
#define at91sam9n12_soc at91_boot_soc
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user