forked from Minki/linux
net: stmmac:sti: Add STi SOC glue driver.
STi series SOCs have a glue layer on top of the synopsis gmac IP, this glue layer needs to be configured before the gmac driver starts using the IP. This patch adds a support to this glue layer which is configured via stmmac setup, init, exit callbacks. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Srinivas Kandagatla
David S. Miller
parent
c7966b525f
commit
d15891ca1f
58
Documentation/devicetree/bindings/net/sti-dwmac.txt
Normal file
58
Documentation/devicetree/bindings/net/sti-dwmac.txt
Normal file
@ -0,0 +1,58 @@
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STMicroelectronics SoC DWMAC glue layer controller
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The device node has following properties.
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Required properties:
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- compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
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"st,stid127-dwmac".
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- reg : Offset of the glue configuration register map in system
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configuration regmap pointed by st,syscon property and size.
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- reg-names : Should be "sti-ethconf".
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- st,syscon : Should be phandle to system configuration node which
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encompases this glue registers.
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- st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be
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wired up in from different sources. One via TXCLK pin and other via CLK_125
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pin. This wiring is totally board dependent. However the retiming glue
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logic should be configured accordingly. Possible values for this property
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"txclk" - if 125Mhz clock is wired up via txclk line.
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"clk_125" - if 125Mhz clock is wired up via clk_125 line.
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This property is only valid for Giga bit setup( GMII, RGMII), and it is
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un-used for non-giga bit (MII and RMII) setups. Also note that internal
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clockgen can not generate stable 125Mhz clock.
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- st,ext-phyclk: This boolean property indicates who is generating the clock
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for tx and rx. This property is only valid for RMII case where the clock can
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be generated from the MAC or PHY.
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- clock-names: should be "sti-ethclk".
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- clocks: Should point to ethernet clockgen which can generate phyclk.
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Example:
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ethernet0: dwmac@fe810000 {
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device_type = "network";
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compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
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reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
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reg-names = "stmmaceth", "sti-ethconf";
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interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
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phy-mode = "mii";
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st,syscon = <&syscfg_rear>;
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snps,pbl = <32>;
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snps,mixed-burst;
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resets = <&softreset STIH416_ETH0_SOFTRESET>;
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reset-names = "stmmaceth";
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pinctrl-0 = <&pinctrl_mii0>;
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pinctrl-names = "default";
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clocks = <&CLK_S_GMAC0_PHY>;
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clock-names = "stmmaceth";
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};
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@ -37,6 +37,17 @@ config DWMAC_SUNXI
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stmmac device driver. This driver is used for A20/A31
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GMAC ethernet controller.
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config DWMAC_STI
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bool "STi GMAC support"
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depends on STMMAC_PLATFORM && ARCH_STI
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default y
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---help---
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Support for ethernet controller on STi SOCs.
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This selects STi SoC glue layer support for the stmmac
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device driver. This driver is used on for the STi series
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SOCs GMAC ethernet controller.
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config STMMAC_PCI
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bool "STMMAC PCI bus support"
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depends on STMMAC_ETH && PCI
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@ -2,6 +2,7 @@ obj-$(CONFIG_STMMAC_ETH) += stmmac.o
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stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o
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stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o
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stmmac-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o
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stmmac-$(CONFIG_DWMAC_STI) += dwmac-sti.o
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stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
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chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
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dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
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330
drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
Normal file
330
drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
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@ -0,0 +1,330 @@
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/**
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* dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
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*
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* Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
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* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/stmmac.h>
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#include <linux/phy.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_net.h>
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/**
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* STi GMAC glue logic.
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* --------------------
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*
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* _
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* | \
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* --------|0 \ ETH_SEL_INTERNAL_NOTEXT_PHYCLK
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* phyclk | |___________________________________________
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* | | | (phyclk-in)
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* --------|1 / |
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* int-clk |_ / |
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* | _
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* | | \
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* |_______|1 \ ETH_SEL_TX_RETIME_CLK
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* | |___________________________
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* | | (tx-retime-clk)
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* _______|0 /
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* | |_ /
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* _ |
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* | \ |
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* --------|0 \ |
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* clk_125 | |__|
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* | | ETH_SEL_TXCLK_NOT_CLK125
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* --------|1 /
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* txclk |_ /
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*
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*
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* ETH_SEL_INTERNAL_NOTEXT_PHYCLK is valid only for RMII where PHY can
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* generate 50MHz clock or MAC can generate it.
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* This bit is configured by "st,ext-phyclk" property.
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*
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* ETH_SEL_TXCLK_NOT_CLK125 is only valid for gigabit modes, where the 125Mhz
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* clock either comes from clk-125 pin or txclk pin. This configuration is
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* totally driven by the board wiring. This bit is configured by
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* "st,tx-retime-src" property.
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*
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* TXCLK configuration is different for different phy interface modes
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* and changes according to link speed in modes like RGMII.
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*
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* Below table summarizes the clock requirement and clock sources for
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* supported phy interface modes with link speeds.
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* ________________________________________________
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*| PHY_MODE | 1000 Mbit Link | 100 Mbit Link |
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* ------------------------------------------------
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*| MII | n/a | 25Mhz |
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*| | | txclk |
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* ------------------------------------------------
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*| GMII | 125Mhz | 25Mhz |
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*| | clk-125/txclk | txclk |
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* ------------------------------------------------
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*| RGMII | 125Mhz | 25Mhz |
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*| | clk-125/txclk | clkgen |
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* ------------------------------------------------
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*| RMII | n/a | 25Mhz |
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*| | |clkgen/phyclk-in |
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* ------------------------------------------------
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*
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* TX lines are always retimed with a clk, which can vary depending
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* on the board configuration. Below is the table of these bits
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* in eth configuration register depending on source of retime clk.
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*
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*---------------------------------------------------------------
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* src | tx_rt_clk | int_not_ext_phyclk | txclk_n_clk125|
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*---------------------------------------------------------------
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* txclk | 0 | n/a | 1 |
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*---------------------------------------------------------------
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* ck_125| 0 | n/a | 0 |
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*---------------------------------------------------------------
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* phyclk| 1 | 0 | n/a |
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*---------------------------------------------------------------
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* clkgen| 1 | 1 | n/a |
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*---------------------------------------------------------------
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*/
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/* Register definition */
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/* 3 bits [8:6]
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* [6:6] ETH_SEL_TXCLK_NOT_CLK125
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* [7:7] ETH_SEL_INTERNAL_NOTEXT_PHYCLK
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* [8:8] ETH_SEL_TX_RETIME_CLK
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*
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*/
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#define TX_RETIME_SRC_MASK GENMASK(8, 6)
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#define ETH_SEL_TX_RETIME_CLK BIT(8)
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#define ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7)
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#define ETH_SEL_TXCLK_NOT_CLK125 BIT(6)
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#define ENMII_MASK GENMASK(5, 5)
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#define ENMII BIT(5)
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/**
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* 3 bits [4:2]
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* 000-GMII/MII
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* 001-RGMII
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* 010-SGMII
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* 100-RMII
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*/
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#define MII_PHY_SEL_MASK GENMASK(4, 2)
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#define ETH_PHY_SEL_RMII BIT(4)
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#define ETH_PHY_SEL_SGMII BIT(3)
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#define ETH_PHY_SEL_RGMII BIT(2)
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#define ETH_PHY_SEL_GMII 0x0
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#define ETH_PHY_SEL_MII 0x0
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#define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \
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iface == PHY_INTERFACE_MODE_RGMII_ID || \
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iface == PHY_INTERFACE_MODE_RGMII_RXID || \
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iface == PHY_INTERFACE_MODE_RGMII_TXID)
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#define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \
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iface == PHY_INTERFACE_MODE_GMII)
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struct sti_dwmac {
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int interface;
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bool ext_phyclk;
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bool is_tx_retime_src_clk_125;
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struct clk *clk;
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int reg;
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struct device *dev;
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struct regmap *regmap;
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};
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static u32 phy_intf_sels[] = {
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[PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII,
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[PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII,
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[PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII,
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[PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII,
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[PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII,
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[PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII,
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};
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enum {
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TX_RETIME_SRC_NA = 0,
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TX_RETIME_SRC_TXCLK = 1,
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TX_RETIME_SRC_CLK_125,
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TX_RETIME_SRC_PHYCLK,
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TX_RETIME_SRC_CLKGEN,
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};
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static const char *const tx_retime_srcs[] = {
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[TX_RETIME_SRC_NA] = "",
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[TX_RETIME_SRC_TXCLK] = "txclk",
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[TX_RETIME_SRC_CLK_125] = "clk_125",
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[TX_RETIME_SRC_PHYCLK] = "phyclk",
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[TX_RETIME_SRC_CLKGEN] = "clkgen",
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};
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static u32 tx_retime_val[] = {
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[TX_RETIME_SRC_TXCLK] = ETH_SEL_TXCLK_NOT_CLK125,
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[TX_RETIME_SRC_CLK_125] = 0x0,
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[TX_RETIME_SRC_PHYCLK] = ETH_SEL_TX_RETIME_CLK,
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[TX_RETIME_SRC_CLKGEN] = ETH_SEL_TX_RETIME_CLK |
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ETH_SEL_INTERNAL_NOTEXT_PHYCLK,
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};
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static void setup_retime_src(struct sti_dwmac *dwmac, u32 spd)
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{
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u32 src = 0, freq = 0;
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if (spd == SPEED_100) {
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if (dwmac->interface == PHY_INTERFACE_MODE_MII ||
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dwmac->interface == PHY_INTERFACE_MODE_GMII) {
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src = TX_RETIME_SRC_TXCLK;
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} else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) {
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if (dwmac->ext_phyclk) {
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src = TX_RETIME_SRC_PHYCLK;
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} else {
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src = TX_RETIME_SRC_CLKGEN;
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freq = 50000000;
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}
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} else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) {
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src = TX_RETIME_SRC_CLKGEN;
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freq = 25000000;
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}
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if (src == TX_RETIME_SRC_CLKGEN && dwmac->clk)
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clk_set_rate(dwmac->clk, freq);
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} else if (spd == SPEED_1000) {
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if (dwmac->is_tx_retime_src_clk_125)
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src = TX_RETIME_SRC_CLK_125;
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else
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src = TX_RETIME_SRC_TXCLK;
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}
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regmap_update_bits(dwmac->regmap, dwmac->reg,
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TX_RETIME_SRC_MASK, tx_retime_val[src]);
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}
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static void sti_dwmac_exit(struct platform_device *pdev, void *priv)
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{
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struct sti_dwmac *dwmac = priv;
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if (dwmac->clk)
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clk_disable_unprepare(dwmac->clk);
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}
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static void sti_fix_mac_speed(void *priv, unsigned int spd)
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{
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struct sti_dwmac *dwmac = priv;
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setup_retime_src(dwmac, spd);
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return;
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}
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static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
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struct platform_device *pdev)
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{
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struct resource *res;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct regmap *regmap;
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int err;
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if (!np)
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return -EINVAL;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-ethconf");
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if (!res)
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return -ENODATA;
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regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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dwmac->dev = dev;
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dwmac->interface = of_get_phy_mode(np);
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dwmac->regmap = regmap;
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dwmac->reg = res->start;
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dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
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dwmac->is_tx_retime_src_clk_125 = false;
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if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) {
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const char *rs;
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err = of_property_read_string(np, "st,tx-retime-src", &rs);
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if (err < 0) {
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dev_err(dev, "st,tx-retime-src not specified\n");
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return err;
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}
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if (!strcasecmp(rs, "clk_125"))
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dwmac->is_tx_retime_src_clk_125 = true;
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}
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dwmac->clk = devm_clk_get(dev, "sti-ethclk");
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if (IS_ERR(dwmac->clk))
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dwmac->clk = NULL;
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return 0;
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}
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static int sti_dwmac_init(struct platform_device *pdev, void *priv)
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{
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struct sti_dwmac *dwmac = priv;
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struct regmap *regmap = dwmac->regmap;
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int iface = dwmac->interface;
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u32 reg = dwmac->reg;
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u32 val, spd;
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if (dwmac->clk)
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clk_prepare_enable(dwmac->clk);
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regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]);
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val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII;
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regmap_update_bits(regmap, reg, ENMII_MASK, val);
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if (IS_PHY_IF_MODE_GBIT(iface))
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spd = SPEED_1000;
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else
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spd = SPEED_100;
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setup_retime_src(dwmac, spd);
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return 0;
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}
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static void *sti_dwmac_setup(struct platform_device *pdev)
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{
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struct sti_dwmac *dwmac;
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int ret;
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dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
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if (!dwmac)
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return ERR_PTR(-ENOMEM);
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ret = sti_dwmac_parse_data(dwmac, pdev);
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if (ret) {
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dev_err(&pdev->dev, "Unable to parse OF data\n");
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return ERR_PTR(ret);
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}
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return dwmac;
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}
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const struct stmmac_of_data sti_gmac_data = {
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.fix_mac_speed = sti_fix_mac_speed,
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.setup = sti_dwmac_setup,
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.init = sti_dwmac_init,
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.exit = sti_dwmac_exit,
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};
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@ -133,6 +133,9 @@ bool stmmac_eee_init(struct stmmac_priv *priv);
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#ifdef CONFIG_DWMAC_SUNXI
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extern const struct stmmac_of_data sun7i_gmac_data;
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#endif
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#ifdef CONFIG_DWMAC_STI
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extern const struct stmmac_of_data sti_gmac_data;
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#endif
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extern struct platform_driver stmmac_pltfr_driver;
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static inline int stmmac_register_platform(void)
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{
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@ -32,6 +32,11 @@
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static const struct of_device_id stmmac_dt_ids[] = {
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#ifdef CONFIG_DWMAC_SUNXI
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{ .compatible = "allwinner,sun7i-a20-gmac", .data = &sun7i_gmac_data},
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#endif
|
||||
#ifdef CONFIG_DWMAC_STI
|
||||
{ .compatible = "st,stih415-dwmac", .data = &sti_gmac_data},
|
||||
{ .compatible = "st,stih416-dwmac", .data = &sti_gmac_data},
|
||||
{ .compatible = "st,stih127-dwmac", .data = &sti_gmac_data},
|
||||
#endif
|
||||
/* SoC specific glue layers should come before generic bindings */
|
||||
{ .compatible = "st,spear600-gmac"},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user