leandrof/linux
1
0
Fork 0
forked from Minki/linux
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'for-next' into for-linus

Browse Source 
Conflicts:

	kernel/irq/chip.c
This commit is contained in:
Jiri Kosina 2009-12-07 18:36:35 +01:00
commit d014d04386
490 changed files with 721 additions and 832 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/ABI/testing/procfs-diskstats
View File

@ -8,7 +8,7 @@ Description:
1 - major number
2 - minor mumber
3 - device name
4 - reads completed succesfully
4 - reads completed successfully
5 - reads merged
6 - sectors read
7 - time spent reading (ms)

2
Documentation/ABI/testing/sysfs-block
View File

@ -4,7 +4,7 @@ Contact: Jerome Marchand <jmarchan@redhat.com>
Description:
The /sys/block/<disk>/stat files displays the I/O
statistics of disk <disk>. They contain 11 fields:
1 - reads completed succesfully
1 - reads completed successfully
2 - reads merged
3 - sectors read
4 - time spent reading (ms)

4
Documentation/DocBook/genericirq.tmpl
View File

@ -417,8 +417,8 @@ desc->chip->end();
</para>
<para>
To make use of the split implementation, replace the call to
__do_IRQ by a call to desc->chip->handle_irq() and associate
the appropriate handler function to desc->chip->handle_irq().
__do_IRQ by a call to desc->handle_irq() and associate
the appropriate handler function to desc->handle_irq().
In most cases the generic handler implementations should
be sufficient.
</para>

2
Documentation/DocBook/mtdnand.tmpl
View File

@ -362,7 +362,7 @@ module_exit(board_cleanup);
<sect1 id="Multiple_chip_control">
<title>Multiple chip control</title>
<para>
The nand driver can control chip arrays. Therefor the
The nand driver can control chip arrays. Therefore the
board driver must provide an own select_chip function. This
function must (de)select the requested chip.
The function pointer in the nand_chip structure must

2
Documentation/DocBook/v4l/videodev2.h.xml
View File

@ -492,7 +492,7 @@ struct <link linkend="v4l2-jpegcompression">v4l2_jpegcompression</link> {
* you do, leave them untouched.
* Inluding less markers will make the
* resulting code smaller, but there will
* be fewer aplications which can read it.
* be fewer applications which can read it.
* The presence of the APP and COM marker
* is influenced by APP_len and COM_len
* ONLY, not by this property! */

2
Documentation/DocBook/writing-an-alsa-driver.tmpl
View File

@ -5318,7 +5318,7 @@ struct _snd_pcm_runtime {
pages of the given size and map them onto the virtually contiguous
memory. The virtual pointer is addressed in runtime-&gt;dma_area.
The physical address (runtime-&gt;dma_addr) is set to zero,
because the buffer is physically non-contigous.
because the buffer is physically non-contiguous.
The physical address table is set up in sgbuf-&gt;table.
You can get the physical address at a certain offset via
<function>snd_pcm_sgbuf_get_addr()</function>.

2
Documentation/dvb/README.dvb-usb
View File

@ -85,7 +85,7 @@ http://www.linuxtv.org/wiki/index.php/DVB_USB
- moved transfer control (pid filter, fifo control) from usb driver to frontend, it seems
better settled there (added xfer_ops-struct)
- created a common files for frontends (mc/p/mb)
2004-09-28 - added support for a new device (Unkown, vendor ID is Hyper-Paltek)
2004-09-28 - added support for a new device (Unknown, vendor ID is Hyper-Paltek)
2004-09-20 - added support for a new device (Compro DVB-U2000), thanks
to Amaury Demol for reporting
- changed usb TS transfer method (several urbs, stopping transfer

7
Documentation/edac.txt
View File

@ -80,7 +80,7 @@ is:
broken_parity_status
as is located in /sys/devices/pci<XXX>/0000:XX:YY.Z directorys for
as is located in /sys/devices/pci<XXX>/0000:XX:YY.Z directories for
PCI devices.
FUTURE HARDWARE SCANNING
@ -288,9 +288,8 @@ Total UE count that had no information attribute fileY:
'ue_noinfo_count'
This attribute file displays the number of UEs that
have occurred have occurred with no informations as to which DIMM
slot is having errors.
This attribute file displays the number of UEs that have occurred
with no information as to which DIMM slot is having errors.
Total Correctable Errors count attribute file:

2
Documentation/lguest/lguest.c
View File

@ -304,7 +304,7 @@ static void *map_zeroed_pages(unsigned int num)
addr = mmap(NULL, getpagesize() * num,
PROT_READ|PROT_WRITE|PROT_EXEC, MAP_PRIVATE, fd, 0);
if (addr == MAP_FAILED)
err(1, "Mmaping %u pages of /dev/zero", num);
err(1, "Mmapping %u pages of /dev/zero", num);
/*
* One neat mmap feature is that you can close the fd, and it

2
Documentation/oops-tracing.txt
View File

@ -257,6 +257,8 @@ characters, each representing a particular tainted value.
10: 'W' if a warning has previously been issued by the kernel.
11: 'C' if a staging driver has been loaded.
The primary reason for the 'Tainted: ' string is to tell kernel
debuggers if this is a clean kernel or if anything unusual has
occurred. Tainting is permanent: even if an offending module is

2
Documentation/power/regulator/consumer.txt
View File

@ -104,7 +104,7 @@ to set the limit to 500mA when supplying power.
Consumers can control their supply current limit by calling :-
int regulator_set_current_limit(regulator, min_uV, max_uV);
int regulator_set_current_limit(regulator, min_uA, max_uA);
Where min_uA and max_uA are the minimum and maximum acceptable current limit in
microamps.

2
Documentation/scsi/ChangeLog.megaraid_sas
View File

@ -185,7 +185,7 @@ ii. FW enables WCE bit in Mode Sense cmd for drives that are configured
Disks are exposed with WCE=1. User is advised to enable Write Back
mode only when the controller has battery backup. At this time
Synhronize cache is not supported by the FW. Driver will short-cycle
the cmd and return sucess without sending down to FW.
the cmd and return success without sending down to FW.
1 Release Date : Sun Jan. 14 11:21:32 PDT 2007 -
Sumant Patro <Sumant.Patro@lsil.com>/Bo Yang

2
Documentation/spi/spi-summary
View File

@ -538,7 +538,7 @@ SPI MESSAGE QUEUE
The bulk of the driver will be managing the I/O queue fed by transfer().
That queue could be purely conceptual. For example, a driver used only
for low-frequency sensor acess might be fine using synchronous PIO.
for low-frequency sensor access might be fine using synchronous PIO.
But the queue will probably be very real, using message->queue, PIO,
often DMA (especially if the root filesystem is in SPI flash), and

6
Documentation/sysctl/kernel.txt
View File

@ -139,9 +139,9 @@ core_pattern is used to specify a core dumpfile pattern name.
core_pipe_limit:
This sysctl is only applicable when core_pattern is configured to pipe core
files to user space helper a (when the first character of core_pattern is a '|',
files to a user space helper (when the first character of core_pattern is a '|',
see above). When collecting cores via a pipe to an application, it is
occasionally usefull for the collecting application to gather data about the
occasionally useful for the collecting application to gather data about the
crashing process from its /proc/pid directory. In order to do this safely, the
kernel must wait for the collecting process to exit, so as not to remove the
crashing processes proc files prematurely. This in turn creates the possibility
@ -152,7 +152,7 @@ applications in parallel. If this value is exceeded, then those crashing
processes above that value are noted via the kernel log and their cores are
skipped. 0 is a special value, indicating that unlimited processes may be
captured in parallel, but that no waiting will take place (i.e. the collecting
process is not guaranteed access to /proc/<crahing pid>/). This value defaults
process is not guaranteed access to /proc/<crashing pid>/). This value defaults
to 0.
==============================================================

2
Documentation/sysctl/vm.txt
View File

@ -370,7 +370,7 @@ The default is 1 percent.
mmap_min_addr
This file indicates the amount of address space which a user process will
be restricted from mmaping. Since kernel null dereference bugs could
be restricted from mmapping. Since kernel null dereference bugs could
accidentally operate based on the information in the first couple of pages
of memory userspace processes should not be allowed to write to them. By
default this value is set to 0 and no protections will be enforced by the

2
Documentation/timers/hpet.txt
View File

@ -3,7 +3,7 @@
The High Precision Event Timer (HPET) hardware follows a specification
by Intel and Microsoft which can be found at
http://www.intel.com/technology/architecture/hpetspec.htm
http://www.intel.com/hardwaredesign/hpetspec_1.pdf
Each HPET has one fixed-rate counter (at 10+ MHz, hence "High Precision")
and up to 32 comparators. Normally three or more comparators are provided,

2
Documentation/video4linux/gspca.txt
View File

@ -6,7 +6,7 @@ The modules are:
xxxx vend:prod
----
spca501 0000:0000 MystFromOri Unknow Camera
spca501 0000:0000 MystFromOri Unknown Camera
m5602 0402:5602 ALi Video Camera Controller
spca501 040a:0002 Kodak DVC-325
spca500 040a:0300 Kodak EZ200

2
Documentation/vm/page-types.c
View File

@ -301,7 +301,7 @@ static char *page_flag_name(uint64_t flags)
present = (flags >> i) & 1;
if (!page_flag_names[i]) {
if (present)
fatal("unkown flag bit %d\n", i);
fatal("unknown flag bit %d\n", i);
continue;
}
buf[j++] = present ? page_flag_names[i][0] : '_';

2
Documentation/vm/slub.txt
View File

@ -245,7 +245,7 @@ been overwritten. Here a string of 8 characters was written into a slab that
has the length of 8 characters. However, a 8 character string needs a
terminating 0. That zero has overwritten the first byte of the Redzone field.
After reporting the details of the issue encountered the FIX SLUB message
tell us that SLUB has restored the Redzone to its proper value and then
tells us that SLUB has restored the Redzone to its proper value and then
system operations continue.
Emergency operations:

2
arch/alpha/mm/numa.c
View File

@ -197,7 +197,7 @@ setup_memory_node(int nid, void *kernel_end)
}
if (bootmap_start == -1)
panic("couldn't find a contigous place for the bootmap");
panic("couldn't find a contiguous place for the bootmap");
/* Allocate the bootmap and mark the whole MM as reserved. */
bootmap_size = init_bootmem_node(NODE_DATA(nid), bootmap_start,

2
arch/arm/common/scoop.c
View File

@ -82,7 +82,7 @@ static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
/* XXX: I'm usure, but it seems so */
/* XXX: I'm unsure, but it seems so */
return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1));
}

2
arch/arm/mach-bcmring/include/csp/reg.h
View File

@ -16,7 +16,7 @@
/**
* @file reg.h
*
* @brief Generic register defintions used in CSP
* @brief Generic register definitions used in CSP
*/
/****************************************************************************/

2
arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
View File

@ -83,7 +83,7 @@ typedef struct {
* @brief Get next available transaction width
*
*
* @return On sucess : Next avail able transaction width
* @return On success : Next available transaction width
* On failure : dmacHw_TRANSACTION_WIDTH_8
*
* @note

2
arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
View File

@ -16,7 +16,7 @@
/**
* @file mm_addr.h
*
* @brief Memory Map address defintions
* @brief Memory Map address definitions
*
* @note
* None

2
arch/arm/mach-bcmring/include/mach/dma.h
View File

@ -651,7 +651,7 @@ int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about t
/**
* Creates a descriptor ring from a memory mapping.
*
* @return 0 on sucess, error code otherwise.
* @return 0 on success, error code otherwise.
*/
/****************************************************************************/

2
arch/arm/mach-lh7a40x/include/mach/hardware.h
View File

@ -31,7 +31,7 @@
/*
* This __REG() version gives the same results as the one above, except
* that we are fooling gcc somehow so it generates far better and smaller
* assembly code for access to contigous registers. It's a shame that gcc
* assembly code for access to contiguous registers. It's a shame that gcc
* doesn't guess this by itself.
*/
#include <asm/types.h>

2
arch/arm/mach-orion5x/pci.c
View File

@ -463,7 +463,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
writel(win_enable, PCI_BAR_ENABLE);
/*
* Disable automatic update of address remaping when writing to BARs.
* Disable automatic update of address remapping when writing to BARs.
*/
orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
}

2
arch/arm/mach-pxa/include/mach/palmld.h
View File

@ -91,7 +91,7 @@
/* BATTERY */
#define PALMLD_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */
#define PALMLD_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */
#define PALMLD_BAT_MAX_CURRENT 0 /* unknokn */
#define PALMLD_BAT_MAX_CURRENT 0 /* unknown */
#define PALMLD_BAT_MIN_CURRENT 0 /* unknown */
#define PALMLD_BAT_MAX_CHARGE 1 /* unknown */
#define PALMLD_BAT_MIN_CHARGE 1 /* unknown */

2
arch/arm/mach-pxa/include/mach/palmt5.h
View File

@ -66,7 +66,7 @@
/* BATTERY */
#define PALMT5_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
#define PALMT5_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
#define PALMT5_BAT_MAX_CURRENT 0 /* unknokn */
#define PALMT5_BAT_MAX_CURRENT 0 /* unknown */
#define PALMT5_BAT_MIN_CURRENT 0 /* unknown */
#define PALMT5_BAT_MAX_CHARGE 1 /* unknown */
#define PALMT5_BAT_MIN_CHARGE 1 /* unknown */

2
arch/arm/mach-pxa/include/mach/palmtc.h
View File

@ -68,7 +68,7 @@
/* BATTERY */
#define PALMTC_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */
#define PALMTC_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */
#define PALMTC_BAT_MAX_CURRENT 0 /* unknokn */
#define PALMTC_BAT_MAX_CURRENT 0 /* unknown */
#define PALMTC_BAT_MIN_CURRENT 0 /* unknown */
#define PALMTC_BAT_MAX_CHARGE 1 /* unknown */
#define PALMTC_BAT_MIN_CHARGE 1 /* unknown */

2
arch/arm/mach-pxa/include/mach/palmte2.h
View File

@ -59,7 +59,7 @@
/* BATTERY */
#define PALMTE2_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
#define PALMTE2_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
#define PALMTE2_BAT_MAX_CURRENT 0 /* unknokn */
#define PALMTE2_BAT_MAX_CURRENT 0 /* unknown */
#define PALMTE2_BAT_MIN_CURRENT 0 /* unknown */
#define PALMTE2_BAT_MAX_CHARGE 1 /* unknown */
#define PALMTE2_BAT_MIN_CHARGE 1 /* unknown */

2
arch/arm/mach-pxa/include/mach/palmtx.h
View File

@ -94,7 +94,7 @@
/* BATTERY */
#define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
#define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
#define PALMTX_BAT_MAX_CURRENT 0 /* unknokn */
#define PALMTX_BAT_MAX_CURRENT 0 /* unknown */
#define PALMTX_BAT_MIN_CURRENT 0 /* unknown */
#define PALMTX_BAT_MAX_CHARGE 1 /* unknown */
#define PALMTX_BAT_MIN_CHARGE 1 /* unknown */

2
arch/arm/mach-pxa/include/mach/palmz72.h
View File

@ -49,7 +49,7 @@
/* Battery */
#define PALMZ72_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
#define PALMZ72_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
#define PALMZ72_BAT_MAX_CURRENT 0 /* unknokn */
#define PALMZ72_BAT_MAX_CURRENT 0 /* unknown */
#define PALMZ72_BAT_MIN_CURRENT 0 /* unknown */
#define PALMZ72_BAT_MAX_CHARGE 1 /* unknown */
#define PALMZ72_BAT_MIN_CHARGE 1 /* unknown */

6
arch/arm/mach-s3c2400/Kconfig
View File

@ -1,13 +1,7 @@
# arch/arm/mach-s3c2400/Kconfig
#
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2
menu "S3C2400 Machines"
endmenu

2
arch/arm/mach-s3c2410/Kconfig
View File

@ -1,5 +1,3 @@
# arch/arm/mach-s3c2410/Kconfig
#
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2

4
arch/arm/mach-s3c2412/Kconfig
View File

@ -1,5 +1,3 @@
# arch/arm/mach-s3c2412/Kconfig
#
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2
@ -90,6 +88,4 @@ config MACH_VSTMS
help
Say Y here if you are using an VSTMS board
endmenu

3
arch/arm/mach-s3c2440/Kconfig
View File

@ -1,5 +1,3 @@
# arch/arm/mach-s3c2440/Kconfig
#
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2
@ -109,4 +107,3 @@ config MACH_MINI2440
available via various sources. It can come with a 3.5" or 7" touch LCD.
endmenu

4
arch/arm/mach-s3c2442/Kconfig
View File

@ -1,5 +1,3 @@
# arch/arm/mach-s3c2442/Kconfig
#
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2
@ -36,6 +34,4 @@ config MACH_NEO1973_GTA02
help
Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
endmenu

2
arch/arm/mach-s3c2443/Kconfig
View File

@ -1,5 +1,3 @@
# arch/arm/mach-s3c2443/Kconfig
#
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2

2
arch/arm/mach-s3c6400/Kconfig
View File

@ -1,5 +1,3 @@
# arch/arm/mach-s3c6400/Kconfig
#
# Copyright 2008 Openmoko, Inc.
# Simtec Electronics, Ben Dooks <ben@simtec.co.uk>
#

2
arch/arm/mach-s3c6400/setup-sdhci.c
View File

@ -30,7 +30,7 @@ char *s3c6400_hsmmc_clksrcs[4] = {
[0] = "hsmmc",
[1] = "hsmmc",
[2] = "mmc_bus",
/* [3] = "48m", - note not succesfully used yet */
/* [3] = "48m", - note not successfully used yet */
};
void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,

2
arch/arm/mach-s3c6410/Kconfig
View File

@ -1,5 +1,3 @@
# arch/arm/mach-s3c6410/Kconfig
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
#

2
arch/arm/mach-s3c6410/setup-sdhci.c
View File

@ -30,7 +30,7 @@ char *s3c6410_hsmmc_clksrcs[4] = {
[0] = "hsmmc",
[1] = "hsmmc",
[2] = "mmc_bus",
/* [3] = "48m", - note not succesfully used yet */
/* [3] = "48m", - note not successfully used yet */
};

2
arch/arm/mach-s5pc100/Kconfig
View File

@ -1,5 +1,3 @@
# arch/arm/mach-s5pc100/Kconfig
#
# Copyright 2009 Samsung Electronics Co.
# Byungho Min <bhmin@samsung.com>
#

2
arch/arm/mach-sa1100/dma.c
View File

@ -65,7 +65,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
/**
* sa1100_request_dma - allocate one of the SA11x0's DMA chanels
* sa1100_request_dma - allocate one of the SA11x0's DMA channels
* @device: The SA11x0 peripheral targeted by this request
* @device_id: An ascii name for the claiming device
* @callback: Function to be called when the DMA completes

2
arch/arm/mach-u300/include/mach/u300-regs.h
View File

@ -6,7 +6,7 @@
* Copyright (C) 2006-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* Basic register address definitions in physical memory and
* some block defintions for core devices like the timer.
* some block definitions for core devices like the timer.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/

2
arch/arm/plat-mxc/include/mach/iomux-mx3.h
View File

@ -112,7 +112,7 @@ enum iomux_gp_func {
* setups a single pin:
* - reserves the pin so that it is not claimed by another driver
* - setups the iomux according to the configuration
* - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
* - if the pin is configured as a GPIO, we claim it through kernel gpiolib
*/
int mxc_iomux_alloc_pin(const unsigned int pin, const char *label);
/*

2
arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
View File

@ -48,7 +48,7 @@
* setups a single pin:
* - reserves the pin so that it is not claimed by another driver
* - setups the iomux according to the configuration
* - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
* - if the pin is configured as a GPIO, we claim it through kernel gpiolib
*/
int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label);
/*

2
arch/arm/plat-mxc/pwm.c
View File

@ -94,7 +94,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
* register to follow the ratio of duty_ns vs. period_ns
* accordingly.
*
* This is good enought for programming the brightness of
* This is good enough for programming the brightness of
* the LCD backlight.
*
* The real implementation would divide PERCLK[0] first by

2
arch/arm/plat-omap/dma.c
View File

@ -1246,7 +1246,7 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
* OMAP_DMA_DYNAMIC_CHAIN
* @params - Channel parameters
*
* @return - Succes : 0
* @return - Success : 0
* Failure: -EINVAL/-ENOMEM
*/
int omap_request_dma_chain(int dev_id, const char *dev_name,

2
arch/arm/plat-omap/include/mach/omap16xx.h
View File

@ -124,7 +124,7 @@
#define TIPB_SWITCH_BASE (0xfffbc800)
#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
/* UART3 Registers Maping through MPU bus */
/* UART3 Registers Mapping through MPU bus */
#define UART3_RHR (OMAP_UART3_BASE + 0)
#define UART3_THR (OMAP_UART3_BASE + 0)
#define UART3_DLL (OMAP_UART3_BASE + 0)

2
arch/arm/plat-s3c/Kconfig
View File

@ -1,5 +1,3 @@
# arch/arm/plat-s3c/Kconfig
#
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2

2
arch/arm/plat-s3c24xx/Kconfig
View File

@ -1,5 +1,3 @@
# arch/arm/plat-s3c24xx/Kconfig
#
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2

2
arch/arm/plat-s3c24xx/include/plat/map.h
View File

@ -64,7 +64,7 @@
/* the calculation for the VA of this must ensure that
* it is the same distance apart from the UART in the
* phsyical address space, as the initial mapping for the IO
* is done as a 1:1 maping. This puts it (currently) at
* is done as a 1:1 mapping. This puts it (currently) at
* 0xFA800000, which is not in the way of any current mapping
* by the base system.
*/

2
arch/arm/plat-s3c64xx/Kconfig
View File

@ -1,5 +1,3 @@
# arch/arm/plat-s3c64xx/Kconfig
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
# Ben Dooks <ben@simtec.co.uk>

2
arch/arm/plat-s5pc1xx/Kconfig
View File

@ -1,5 +1,3 @@
# arch/arm/plat-s5pc1xx/Kconfig
#
# Copyright 2009 Samsung Electronics Co.
# Byungho Min <bhmin@samsung.com>
#

2
arch/avr32/boards/hammerhead/Kconfig
View File

@ -24,7 +24,7 @@ config BOARD_HAMMERHEAD_SND
bool "Atmel AC97 Sound support"
help
This enables Sound support for the Hammerhead board. You may
also go trough the ALSA settings to get it working.
also go through the ALSA settings to get it working.
Choose 'Y' here if you have ordered a Corona daugther board and
want to make your board funky.

2
arch/blackfin/kernel/traps.c
View File

@ -619,7 +619,7 @@ asmlinkage notrace void trap_c(struct pt_regs *fp)
/*
* Similar to get_user, do some address checking, then dereference
* Return true on sucess, false on bad address
* Return true on success, false on bad address
*/
static bool get_instruction(unsigned short *val, unsigned short *address)
{

4
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
View File

@ -542,7 +542,7 @@
#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
@ -550,7 +550,7 @@
#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */

4
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
View File

@ -544,7 +544,7 @@
#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
@ -552,7 +552,7 @@
#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */

4
arch/blackfin/mach-bf537/include/mach/defBF534.h
View File

@ -934,7 +934,7 @@
#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
@ -942,7 +942,7 @@
#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */

4
arch/blackfin/mach-bf548/include/mach/defBF544.h
View File

@ -491,7 +491,7 @@
#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
@ -501,7 +501,7 @@
#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */

4
arch/blackfin/mach-bf548/include/mach/defBF547.h
View File

@ -470,7 +470,7 @@
#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
@ -480,7 +480,7 @@
#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */

4
arch/blackfin/mach-bf548/include/mach/defBF548.h
View File

@ -853,7 +853,7 @@
#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
@ -863,7 +863,7 @@
#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */

4
arch/blackfin/mach-bf548/include/mach/defBF549.h
View File

@ -1024,7 +1024,7 @@
#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
@ -1034,7 +1034,7 @@
#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */

3
arch/cris/arch-v10/mm/fault.c
View File

@ -80,8 +80,7 @@ handle_mmu_bus_fault(struct pt_regs *regs)
* do_page_fault may have flushed the TLB so we have to restore
* the MMU registers.
*/
local_save_flags(flags);
local_irq_disable();
local_irq_save(flags);
pmd = (pmd_t *)(pgd + pgd_index(address));
if (pmd_none(*pmd))
goto exit;

22
arch/cris/arch-v10/mm/tlb.c
View File

@ -134,28 +134,6 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
local_irq_restore(flags);
}
/* dump the entire TLB for debug purposes */
#if 0
void
dump_tlb_all(void)
{
int i;
unsigned long flags;
printk("TLB dump. LO is: pfn | reserved | global | valid | kernel | we |\n");
local_save_flags(flags);
local_irq_disable();
for(i = 0; i < NUM_TLB_ENTRIES; i++) {
*R_TLB_SELECT = ( IO_FIELD(R_TLB_SELECT, index, i) );
printk("Entry %d: HI 0x%08lx, LO 0x%08lx\n",
i, *R_TLB_HI, *R_TLB_LO);
}
local_irq_restore(flags);
}
#endif
/*
* Initialize the context related info for a new mm_struct
* instance.

2
arch/cris/mm/fault.c
View File

@ -209,7 +209,7 @@ do_page_fault(unsigned long address, struct pt_regs *regs,
/* Are we prepared to handle this kernel fault?
*
* (The kernel has valid exception-points in the source
* when it acesses user-memory. When it fails in one
* when it accesses user-memory. When it fails in one
* of those points, we find it in a table and do a jump
* to some fixup code that loads an appropriate error
* code)

2
arch/ia64/hp/common/sba_iommu.c
View File

@ -1381,7 +1381,7 @@ sba_coalesce_chunks(struct ioc *ioc, struct device *dev,
#endif
/*
** Not virtually contigous.
** Not virtually contiguous.
** Terminate prev chunk.
** Start a new chunk.
**

2
arch/ia64/ia32/ia32_entry.S
View File

@ -79,7 +79,7 @@ GLOBAL_ENTRY(ia32_ret_from_clone)
(p6) br.cond.spnt .ia32_strace_check_retval
;; // prevent RAW on r8
END(ia32_ret_from_clone)
// fall thrugh
// fall through
GLOBAL_ENTRY(ia32_ret_from_syscall)
PT_REGS_UNWIND_INFO(0)

2
arch/ia64/include/asm/perfmon_default_smpl.h
View File

@ -67,7 +67,7 @@ typedef struct {
unsigned long ip; /* where did the overflow interrupt happened */
unsigned long tstamp; /* ar.itc when entering perfmon intr. handler */
unsigned short cpu; /* cpu on which the overfow occured */
unsigned short cpu; /* cpu on which the overflow occured */
unsigned short set; /* event set active when overflow ocurred */
int tgid; /* thread group id (for NPTL, this is getpid()) */
} pfm_default_smpl_entry_t;

2
arch/ia64/include/asm/sn/shubio.h
View File

@ -3289,7 +3289,7 @@ typedef ii_icrb0_e_u_t icrbe_t;
#define IIO_IIDSR_LVL_SHIFT 0
#define IIO_IIDSR_LVL_MASK 0x000000ff
/* Xtalk timeout threshhold register (IIO_IXTT) */
/* Xtalk timeout threshold register (IIO_IXTT) */
#define IXTT_RRSP_TO_SHFT 55 /* read response timeout */
#define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT)
#define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */

2
arch/ia64/kernel/esi.c
View File

@ -84,7 +84,7 @@ static int __init esi_init (void)
case ESI_DESC_ENTRY_POINT:
break;
default:
printk(KERN_WARNING "Unkown table type %d found in "
printk(KERN_WARNING "Unknown table type %d found in "
"ESI table, ignoring rest of table\n", *p);
return -ENODEV;
}

2
arch/ia64/kernel/perfmon.c
View File

@ -3523,7 +3523,7 @@ pfm_use_debug_registers(struct task_struct *task)
* IA64_THREAD_DBG_VALID set. This indicates a task which was
* able to use the debug registers for debugging purposes via
* ptrace(). Therefore we know it was not using them for
* perfmormance monitoring, so we only decrement the number
* performance monitoring, so we only decrement the number
* of "ptraced" debug register users to keep the count up to date
*/
int

28
arch/m68k/ifpsp060/src/fpsp.S
View File

@ -753,7 +753,7 @@ fovfl_ovfl_on:
bra.l _real_ovfl
# overflow occurred but is disabled. meanwhile, inexact is enabled. therefore,
# overflow occurred but is disabled. meanwhile, inexact is enabled. Therefore,
# we must jump to real_inex().
fovfl_inex_on:
@ -1015,7 +1015,7 @@ funfl_unfl_on2:
bra.l _real_unfl
# undeflow occurred but is disabled. meanwhile, inexact is enabled. therefore,
# underflow occurred but is disabled. meanwhile, inexact is enabled. Therefore,
# we must jump to real_inex().
funfl_inex_on:
@ -2963,7 +2963,7 @@ iea_disabled:
tst.w %d0 # is instr fmovm?
bmi.b iea_dis_fmovm # yes
# instruction is using an extended precision immediate operand. therefore,
# instruction is using an extended precision immediate operand. Therefore,
# the total instruction length is 16 bytes.
iea_dis_immed:
mov.l &0x10,%d0 # 16 bytes of instruction
@ -9624,7 +9624,7 @@ sok_dnrm:
bge.b sok_norm2 # thank goodness no
# the multiply factor that we're trying to create should be a denorm
# for the multiply to work. therefore, we're going to actually do a
# for the multiply to work. Therefore, we're going to actually do a
# multiply with a denorm which will cause an unimplemented data type
# exception to be put into the machine which will be caught and corrected
# later. we don't do this with the DENORMs above because this method
@ -12216,7 +12216,7 @@ fin_sd_unfl_dis:
#
# operand will underflow AND underflow or inexact is enabled.
# therefore, we must return the result rounded to extended precision.
# Therefore, we must return the result rounded to extended precision.
#
fin_sd_unfl_ena:
mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
@ -12746,7 +12746,7 @@ fdiv_zero_load_p:
#
# The destination was In Range and the source was a ZERO. The result,
# therefore, is an INF w/ the proper sign.
# Therefore, is an INF w/ the proper sign.
# So, determine the sign and return a new INF (w/ the j-bit cleared).
#
global fdiv_inf_load # global for fsgldiv
@ -12996,7 +12996,7 @@ fneg_sd_unfl_dis:
#
# operand will underflow AND underflow is enabled.
# therefore, we must return the result rounded to extended precision.
# Therefore, we must return the result rounded to extended precision.
#
fneg_sd_unfl_ena:
mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
@ -13611,7 +13611,7 @@ fabs_sd_unfl_dis:
#
# operand will underflow AND underflow is enabled.
# therefore, we must return the result rounded to extended precision.
# Therefore, we must return the result rounded to extended precision.
#
fabs_sd_unfl_ena:
mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
@ -14973,7 +14973,7 @@ fadd_zero_2:
#
# the ZEROes have opposite signs:
# - therefore, we return +ZERO if the rounding modes are RN,RZ, or RP.
# - Therefore, we return +ZERO if the rounding modes are RN,RZ, or RP.
# - -ZERO is returned in the case of RM.
#
fadd_zero_2_chk_rm:
@ -15425,7 +15425,7 @@ fsub_zero_2:
#
# the ZEROes have the same signs:
# - therefore, we return +ZERO if the rounding mode is RN,RZ, or RP
# - Therefore, we return +ZERO if the rounding mode is RN,RZ, or RP
# - -ZERO is returned in the case of RM.
#
fsub_zero_2_chk_rm:
@ -15693,7 +15693,7 @@ fsqrt_sd_unfl_dis:
#
# operand will underflow AND underflow is enabled.
# therefore, we must return the result rounded to extended precision.
# Therefore, we must return the result rounded to extended precision.
#
fsqrt_sd_unfl_ena:
mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
@ -21000,7 +21000,7 @@ fout_pack_type:
tst.l %d0
bne.b fout_pack_set
# "mantissa" is all zero which means that the answer is zero. but, the '040
# algorithm allows the exponent to be non-zero. the 881/2 do not. therefore,
# algorithm allows the exponent to be non-zero. the 881/2 do not. Therefore,
# if the mantissa is zero, I will zero the exponent, too.
# the question now is whether the exponents sign bit is allowed to be non-zero
# for a zero, also...
@ -21743,7 +21743,7 @@ denorm_set_stky:
rts
# #
# dnrm_lp(): normalize exponent/mantissa to specified threshhold #
# dnrm_lp(): normalize exponent/mantissa to specified threshold #
# #
# INPUT: #
# %a0 : points to the operand to be denormalized #
@ -22402,7 +22402,7 @@ unnorm_shift:
bgt.b unnorm_nrm_zero # yes; denorm only until exp = 0
#
# exponent would not go < 0. therefore, number stays normalized
# exponent would not go < 0. Therefore, number stays normalized
#
sub.w %d0, %d1 # shift exponent value
mov.w FTEMP_EX(%a0), %d0 # load old exponent

26
arch/m68k/ifpsp060/src/pfpsp.S
View File

@ -752,7 +752,7 @@ fovfl_ovfl_on:
bra.l _real_ovfl
# overflow occurred but is disabled. meanwhile, inexact is enabled. therefore,
# overflow occurred but is disabled. meanwhile, inexact is enabled. Therefore,
# we must jump to real_inex().
fovfl_inex_on:
@ -1014,7 +1014,7 @@ funfl_unfl_on2:
bra.l _real_unfl
# undeflow occurred but is disabled. meanwhile, inexact is enabled. therefore,
# underflow occurred but is disabled. meanwhile, inexact is enabled. Therefore,
# we must jump to real_inex().
funfl_inex_on:
@ -2962,7 +2962,7 @@ iea_disabled:
tst.w %d0 # is instr fmovm?
bmi.b iea_dis_fmovm # yes
# instruction is using an extended precision immediate operand. therefore,
# instruction is using an extended precision immediate operand. Therefore,
# the total instruction length is 16 bytes.
iea_dis_immed:
mov.l &0x10,%d0 # 16 bytes of instruction
@ -5865,7 +5865,7 @@ denorm_set_stky:
rts
# #
# dnrm_lp(): normalize exponent/mantissa to specified threshhold #
# dnrm_lp(): normalize exponent/mantissa to specified threshold #
# #
# INPUT: #
# %a0 : points to the operand to be denormalized #
@ -6524,7 +6524,7 @@ unnorm_shift:
bgt.b unnorm_nrm_zero # yes; denorm only until exp = 0
#
# exponent would not go < 0. therefore, number stays normalized
# exponent would not go < 0. Therefore, number stays normalized
#
sub.w %d0, %d1 # shift exponent value
mov.w FTEMP_EX(%a0), %d0 # load old exponent
@ -7901,7 +7901,7 @@ fout_pack_type:
tst.l %d0
bne.b fout_pack_set
# "mantissa" is all zero which means that the answer is zero. but, the '040
# algorithm allows the exponent to be non-zero. the 881/2 do not. therefore,
# algorithm allows the exponent to be non-zero. the 881/2 do not. Therefore,
# if the mantissa is zero, I will zero the exponent, too.
# the question now is whether the exponents sign bit is allowed to be non-zero
# for a zero, also...
@ -8647,7 +8647,7 @@ fin_sd_unfl_dis:
#
# operand will underflow AND underflow or inexact is enabled.
# therefore, we must return the result rounded to extended precision.
# Therefore, we must return the result rounded to extended precision.
#
fin_sd_unfl_ena:
mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
@ -9177,7 +9177,7 @@ fdiv_zero_load_p:
#
# The destination was In Range and the source was a ZERO. The result,
# therefore, is an INF w/ the proper sign.
# Therefore, is an INF w/ the proper sign.
# So, determine the sign and return a new INF (w/ the j-bit cleared).
#
global fdiv_inf_load # global for fsgldiv
@ -9427,7 +9427,7 @@ fneg_sd_unfl_dis:
#
# operand will underflow AND underflow is enabled.
# therefore, we must return the result rounded to extended precision.
# Therefore, we must return the result rounded to extended precision.
#
fneg_sd_unfl_ena:
mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
@ -10042,7 +10042,7 @@ fabs_sd_unfl_dis:
#
# operand will underflow AND underflow is enabled.
# therefore, we must return the result rounded to extended precision.
# Therefore, we must return the result rounded to extended precision.
#
fabs_sd_unfl_ena:
mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
@ -11404,7 +11404,7 @@ fadd_zero_2:
#
# the ZEROes have opposite signs:
# - therefore, we return +ZERO if the rounding modes are RN,RZ, or RP.
# - Therefore, we return +ZERO if the rounding modes are RN,RZ, or RP.
# - -ZERO is returned in the case of RM.
#
fadd_zero_2_chk_rm:
@ -11856,7 +11856,7 @@ fsub_zero_2:
#
# the ZEROes have the same signs:
# - therefore, we return +ZERO if the rounding mode is RN,RZ, or RP
# - Therefore, we return +ZERO if the rounding mode is RN,RZ, or RP
# - -ZERO is returned in the case of RM.
#
fsub_zero_2_chk_rm:
@ -12124,7 +12124,7 @@ fsqrt_sd_unfl_dis:
#
# operand will underflow AND underflow is enabled.
# therefore, we must return the result rounded to extended precision.
# Therefore, we must return the result rounded to extended precision.
#
fsqrt_sd_unfl_ena:
mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)

2
arch/m68k/include/asm/bootinfo.h
View File

@ -145,7 +145,7 @@ struct bi_record {
/*
* Macintosh hardware profile data - unused, see macintosh.h for
* resonable type values
* reasonable type values
*/
#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */

2
arch/microblaze/lib/memcpy.c
View File

@ -9,7 +9,7 @@
* It is based on demo code originally Copyright 2001 by Intel Corp, taken from
* http://www.embedded.com/showArticle.jhtml?articleID=19205567
*
* Attempts were made, unsuccesfully, to contact the original
* Attempts were made, unsuccessfully, to contact the original
* author of this code (Michael Morrow, Intel). Below is the original
* copyright notice.
*

2
arch/microblaze/lib/memmove.c
View File

@ -9,7 +9,7 @@
* It is based on demo code originally Copyright 2001 by Intel Corp, taken from
* http://www.embedded.com/showArticle.jhtml?articleID=19205567
*
* Attempts were made, unsuccesfully, to contact the original
* Attempts were made, unsuccessfully, to contact the original
* author of this code (Michael Morrow, Intel). Below is the original
* copyright notice.
*

2
arch/microblaze/lib/memset.c
View File

@ -9,7 +9,7 @@
* It is based on demo code originally Copyright 2001 by Intel Corp, taken from
* http://www.embedded.com/showArticle.jhtml?articleID=19205567
*
* Attempts were made, unsuccesfully, to contact the original
* Attempts were made, unsuccessfully, to contact the original
* author of this code (Michael Morrow, Intel). Below is the original
* copyright notice.
*

2
arch/mips/include/asm/mach-pnx833x/gpio.h
View File

@ -24,7 +24,7 @@
/* BIG FAT WARNING: races danger!
No protections exist here. Current users are only early init code,
when locking is not needed because no cuncurency yet exists there,
when locking is not needed because no concurrency yet exists there,
and GPIO IRQ dispatcher, which does locking.
However, if many uses will ever happen, proper locking will be needed
- including locking between different uses

2
arch/mips/include/asm/sgi/ioc.h
View File

@ -164,7 +164,7 @@ struct sgioc_regs {
u32 _unused5;
u8 _write[3];
volatile u8 write;
#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshhold */
#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshold */
#define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */
#define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */
#define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */

2
arch/mips/include/asm/sibyte/sb1250_mac.h
View File

@ -212,7 +212,7 @@
#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1)
/*
* MAC Fifo Threshhold registers (Table 9-14)
* MAC Fifo Threshold registers (Table 9-14)
* Register: MAC_THRSH_CFG_0
* Register: MAC_THRSH_CFG_1
* Register: MAC_THRSH_CFG_2

2
arch/mips/include/asm/sn/sn0/hubio.h
View File

@ -825,7 +825,7 @@ typedef union iprb_u {
struct {
u64 rsvd1: 15,
error: 1, /* Widget rcvd wr resp pkt w/ error */
ovflow: 5, /* Over flow count. perf measurement */
ovflow: 5, /* Overflow count. perf measurement */
fire_and_forget: 1, /* Launch Write without response */
mode: 2, /* Widget operation Mode */
rsvd2: 2,

2
arch/mips/kernel/smtc.c
View File

@ -1331,7 +1331,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
if (!((asid += ASID_INC) & ASID_MASK) ) {
if (cpu_has_vtag_icache)
flush_icache_all();
/* Traverse all online CPUs (hack requires contigous range) */
/* Traverse all online CPUs (hack requires contiguous range) */
for_each_online_cpu(i) {
/*
* We don't need to worry about our own CPU, nor those of

2
arch/mips/math-emu/dp_sub.c
View File

@ -110,7 +110,7 @@ ieee754dp ieee754dp_sub(ieee754dp x, ieee754dp y)
case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
DPDNORMX;
/* FAAL THOROUGH */
/* FALL THROUGH */
case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
/* normalize ym,ye */

2
arch/mips/txx9/generic/smsc_fdc37m81x.c
View File

@ -117,7 +117,7 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port)
if (chip_id == SMSC_FDC37M81X_CHIP_ID)
smsc_fdc37m81x_config_end();
else {
printk(KERN_WARNING "%s: unknow chip id 0x%02x\n", __func__,
printk(KERN_WARNING "%s: unknown chip id 0x%02x\n", __func__,
chip_id);
g_smsc_fdc37m81x_base = 0;
}

2
arch/parisc/kernel/perf.c
View File

@ -24,7 +24,7 @@
*
* This driver programs the PCX-U/PCX-W performance counters
* on the PA-RISC 2.0 chips. The driver keeps all images now
* internally to the kernel to hopefully eliminate the possiblity
* internally to the kernel to hopefully eliminate the possibility
* of a bad image halting the CPU. Also, there are different
* images for the PCX-W and later chips vs the PCX-U chips.
*

2
arch/powerpc/include/asm/reg_fsl_emb.h
View File

@ -39,7 +39,7 @@
#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshold Multiple Field */
#define PMLCB_THRESHMUL_SHIFT 8
#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */

2
arch/powerpc/kernel/kgdb.c
View File

@ -52,7 +52,7 @@ static struct hard_trap_info
{ 0x2030, 0x08 /* SIGFPE */ }, /* spe fp data */
{ 0x2040, 0x08 /* SIGFPE */ }, /* spe fp data */
{ 0x2050, 0x08 /* SIGFPE */ }, /* spe fp round */
{ 0x2060, 0x0e /* SIGILL */ }, /* performace monitor */
{ 0x2060, 0x0e /* SIGILL */ }, /* performance monitor */
{ 0x2900, 0x08 /* SIGFPE */ }, /* apu unavailable */
{ 0x3100, 0x0e /* SIGALRM */ }, /* fixed interval timer */
{ 0x3200, 0x02 /* SIGINT */ }, /* watchdog */

2
arch/powerpc/kernel/tau_6xx.c
View File

@ -59,7 +59,7 @@ void set_thresholds(unsigned long cpu)
mtspr(SPRN_THRM1, THRM1_THRES(tau[cpu].low) | THRM1_V | THRM1_TIE | THRM1_TID);
/* setup THRM2,
* threshold, valid bit, enable interrupts, interrupt when above threshhold
* threshold, valid bit, enable interrupts, interrupt when above threshold
*/
mtspr (SPRN_THRM2, THRM1_THRES(tau[cpu].high) | THRM1_V | THRM1_TIE);
#else

2
arch/powerpc/kernel/vdso.c
View File

@ -721,7 +721,7 @@ static int __init vdso_init(void)
#ifdef CONFIG_PPC64
/*
* Fill up the "systemcfg" stuff for backward compatiblity
* Fill up the "systemcfg" stuff for backward compatibility
*/
strcpy((char *)vdso_data->eye_catcher, "SYSTEMCFG:PPC64");
vdso_data->version.major = SYSTEMCFG_MAJOR;

6
arch/powerpc/oprofile/op_model_cell.c
View File

@ -248,7 +248,7 @@ static int pm_rtas_activate_signals(u32 node, u32 count)
* There is no debug setup required for the cycles event.
* Note that only events in the same group can be used.
* Otherwise, there will be conflicts in correctly routing
* the signals on the debug bus. It is the responsiblity
* the signals on the debug bus. It is the responsibility
* of the OProfile user tool to check the events are in
* the same group.
*/
@ -1594,7 +1594,7 @@ static void cell_handle_interrupt_spu(struct pt_regs *regs,
* to a latch. The new values (interrupt setting bits, reset
* counter value etc.) are not copied to the actual registers
* until the performance monitor is enabled. In order to get
* this to work as desired, the permormance monitor needs to
* this to work as desired, the performance monitor needs to
* be disabled while writing to the latches. This is a
* HW design issue.
*/
@ -1668,7 +1668,7 @@ static void cell_handle_interrupt_ppu(struct pt_regs *regs,
* to a latch. The new values (interrupt setting bits, reset
* counter value etc.) are not copied to the actual registers
* until the performance monitor is enabled. In order to get
* this to work as desired, the permormance monitor needs to
* this to work as desired, the performance monitor needs to
* be disabled while writing to the latches. This is a
* HW design issue.
*/

2
arch/powerpc/platforms/52xx/mpc52xx_pci.c
View File

@ -100,7 +100,7 @@ const struct of_device_id mpc52xx_pci_ids[] __initdata = {
};
/* ======================================================================== */
/* PCI configuration acess */
/* PCI configuration access */
/* ======================================================================== */
static int

2
arch/powerpc/platforms/powermac/pci.c
View File

@ -302,7 +302,7 @@ static void __init setup_chaos(struct pci_controller *hose,
* 1 -> Skip the device but act as if the access was successfull
* (return 0xff's on reads, eventually, cache config space
* accesses in a later version)
* -1 -> Hide the device (unsuccessful acess)
* -1 -> Hide the device (unsuccessful access)
*/
static int u3_ht_skip_device(struct pci_controller *hose,
struct pci_bus *bus, unsigned int devfn)

2
arch/powerpc/sysdev/dart_iommu.c
View File

@ -160,7 +160,7 @@ static int dart_build(struct iommu_table *tbl, long index,
dp = ((unsigned int*)tbl->it_base) + index;
/* On U3, all memory is contigous, so we can move this
/* On U3, all memory is contiguous, so we can move this
* out of the loop.
*/
l = npages;

4
arch/s390/math-emu/math.c
View File

@ -2088,7 +2088,7 @@ int math_emu_ldr(__u8 *opcode) {
__u16 opc = *((__u16 *) opcode);
if ((opc & 0x90) == 0) { /* test if rx in {0,2,4,6} */
/* we got an exception therfore ry can't be in {0,2,4,6} */
/* we got an exception therefore ry can't be in {0,2,4,6} */
asm volatile( /* load rx from fp_regs.fprs[ry] */
" bras 1,0f\n"
" ld 0,0(%1)\n"
@ -2118,7 +2118,7 @@ int math_emu_ler(__u8 *opcode) {
__u16 opc = *((__u16 *) opcode);
if ((opc & 0x90) == 0) { /* test if rx in {0,2,4,6} */
/* we got an exception therfore ry can't be in {0,2,4,6} */
/* we got an exception therefore ry can't be in {0,2,4,6} */
asm volatile( /* load rx from fp_regs.fprs[ry] */
" bras 1,0f\n"
" le 0,0(%1)\n"

2
arch/sh/include/mach-common/mach/titan.h
View File

@ -1,5 +1,5 @@
/*
* Platform defintions for Titan
* Platform definitions for Titan
*/
#ifndef _ASM_SH_TITAN_H
#define _ASM_SH_TITAN_H

4
arch/x86/include/asm/desc_defs.h
View File

@ -12,9 +12,9 @@
#include <linux/types.h>
/*
* FIXME: Acessing the desc_struct through its fields is more elegant,
* FIXME: Accessing the desc_struct through its fields is more elegant,
* and should be the one valid thing to do. However, a lot of open code
* still touches the a and b acessors, and doing this allow us to do it
* still touches the a and b accessors, and doing this allow us to do it
* incrementally. We keep the signature as a struct, rather than an union,
* so we can get rid of it transparently in the future -- glommer
*/

2
arch/x86/include/asm/mmzone_32.h
View File

@ -47,7 +47,7 @@ static inline void resume_map_numa_kva(pgd_t *pgd) {}
/*
* generic node memory support, the following assumptions apply:
*
* 1) memory comes in 64Mb contigious chunks which are either present or not
* 1) memory comes in 64Mb contiguous chunks which are either present or not
* 2) we will not have more than 64Gb in total
*
* for now assume that 64Gb is max amount of RAM for whole system

Some files were not shown because too many files have changed in this diff Show More