drm/amdgpu: enable DPG mode for VCN3.0
Enable DPG mode for VCN3.0 by updating related flag. V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher
parent
7055f4a353
commit
d00b0fa90f
@@ -726,6 +726,7 @@ static int nv_common_early_init(void *handle)
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AMD_CG_SUPPORT_IH_CG |
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AMD_CG_SUPPORT_IH_CG |
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AMD_CG_SUPPORT_MC_LS;
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AMD_CG_SUPPORT_MC_LS;
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adev->pg_flags = AMD_PG_SUPPORT_VCN |
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adev->pg_flags = AMD_PG_SUPPORT_VCN |
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AMD_PG_SUPPORT_VCN_DPG |
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AMD_PG_SUPPORT_JPEG |
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AMD_PG_SUPPORT_JPEG |
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AMD_PG_SUPPORT_ATHUB;
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AMD_PG_SUPPORT_ATHUB;
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adev->external_rev_id = adev->rev_id + 0x28;
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adev->external_rev_id = adev->rev_id + 0x28;
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@@ -254,7 +254,8 @@ static int vcn_v3_0_hw_init(void *handle)
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done:
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done:
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if (!r)
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if (!r)
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DRM_INFO("VCN decode and encode initialized successfully.\n");
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DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
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(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
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return r;
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return r;
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}
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}
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@@ -278,7 +279,9 @@ static int vcn_v3_0_hw_fini(void *handle)
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ring = &adev->vcn.inst[i].ring_dec;
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ring = &adev->vcn.inst[i].ring_dec;
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if (RREG32_SOC15(VCN, i, mmUVD_STATUS))
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if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
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(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
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RREG32_SOC15(VCN, i, mmUVD_STATUS)))
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vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
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vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
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ring->sched.ready = false;
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ring->sched.ready = false;
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