Merge branch 'pci/virtualization' into next
* pci/virtualization: PCI: Disable VF decoding before pcibios_sriov_disable() updates resources PCI: Add ACS quirk for APM X-Gene devices PCI: Mark AMD Stoney GPU ATS as broken Conflicts: drivers/pci/quirks.c
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commit
cf2d804110
@ -331,7 +331,6 @@ failed:
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while (i--)
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while (i--)
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pci_iov_remove_virtfn(dev, i, 0);
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pci_iov_remove_virtfn(dev, i, 0);
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pcibios_sriov_disable(dev);
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err_pcibios:
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err_pcibios:
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iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
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iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
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pci_cfg_access_lock(dev);
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pci_cfg_access_lock(dev);
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@ -339,6 +338,8 @@ err_pcibios:
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ssleep(1);
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ssleep(1);
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pci_cfg_access_unlock(dev);
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pci_cfg_access_unlock(dev);
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pcibios_sriov_disable(dev);
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if (iov->link != dev->devfn)
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if (iov->link != dev->devfn)
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sysfs_remove_link(&dev->dev.kobj, "dep_link");
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sysfs_remove_link(&dev->dev.kobj, "dep_link");
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@ -357,14 +358,14 @@ static void sriov_disable(struct pci_dev *dev)
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for (i = 0; i < iov->num_VFs; i++)
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for (i = 0; i < iov->num_VFs; i++)
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pci_iov_remove_virtfn(dev, i, 0);
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pci_iov_remove_virtfn(dev, i, 0);
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pcibios_sriov_disable(dev);
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iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
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iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
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pci_cfg_access_lock(dev);
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pci_cfg_access_lock(dev);
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pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
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pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
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ssleep(1);
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ssleep(1);
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pci_cfg_access_unlock(dev);
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pci_cfg_access_unlock(dev);
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pcibios_sriov_disable(dev);
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if (iov->link != dev->devfn)
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if (iov->link != dev->devfn)
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sysfs_remove_link(&dev->dev.kobj, "dep_link");
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sysfs_remove_link(&dev->dev.kobj, "dep_link");
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@ -4137,6 +4137,18 @@ static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
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return acs_flags ? 0 : 1;
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return acs_flags ? 0 : 1;
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}
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}
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static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
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{
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/*
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* X-Gene root matching this quirk do not allow peer-to-peer
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* transactions with others, allowing masking out these bits as if they
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* were unimplemented in the ACS capability.
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*/
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acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
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return acs_flags ? 0 : 1;
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}
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/*
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/*
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* Many Intel PCH root ports do provide ACS-like features to disable peer
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* Many Intel PCH root ports do provide ACS-like features to disable peer
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* transactions and validate bus numbers in requests, but do not provide an
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* transactions and validate bus numbers in requests, but do not provide an
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@ -4385,6 +4397,8 @@ static const struct pci_dev_acs_enabled {
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{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
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{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
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/* Cavium ThunderX */
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/* Cavium ThunderX */
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{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
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{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
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/* APM X-Gene */
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{ PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
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{ 0 }
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{ 0 }
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};
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};
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@ -4680,3 +4694,18 @@ static void quirk_no_ext_tags(struct pci_dev *pdev)
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
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#ifdef CONFIG_PCI_ATS
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/*
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* Some devices have a broken ATS implementation causing IOMMU stalls.
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* Don't use ATS for those devices.
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*/
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static void quirk_no_ats(struct pci_dev *pdev)
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{
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dev_info(&pdev->dev, "disabling ATS (broken on this device)\n");
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pdev->ats_cap = 0;
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}
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/* AMD Stoney platform GPU */
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
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#endif /* CONFIG_PCI_ATS */
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