forked from Minki/linux
Merge branch 'remotes/lorenzo/pci/uniphier'
- Add UniPhier PCIe controller driver and DT bindings (Kunihiko Hayashi) * remotes/lorenzo/pci/uniphier: PCI: uniphier: Add UniPhier PCIe host controller support dt-bindings: PCI: Add UniPhier PCIe host controller description # Conflicts: # drivers/pci/controller/dwc/Kconfig # drivers/pci/controller/dwc/Makefile
This commit is contained in:
Bjorn Helgaas
commit
cdf4f4dc11
81
Documentation/devicetree/bindings/pci/uniphier-pcie.txt
Normal file
81
Documentation/devicetree/bindings/pci/uniphier-pcie.txt
Normal file
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@ -0,0 +1,81 @@
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Socionext UniPhier PCIe host controller bindings
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This describes the devicetree bindings for PCIe host controller implemented
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on Socionext UniPhier SoCs.
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UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
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It shares common functions with the PCIe DesignWare core driver and inherits
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common properties defined in
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Documentation/devicetree/bindings/pci/designware-pcie.txt.
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Required properties:
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- compatible: Should be "socionext,uniphier-pcie".
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- reg: Specifies offset and length of the register set for the device.
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According to the reg-names, appropriate register sets are required.
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- reg-names: Must include the following entries:
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"dbi" - controller configuration registers
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"link" - SoC-specific glue layer registers
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"config" - PCIe configuration space
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- clocks: A phandle to the clock gate for PCIe glue layer including
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the host controller.
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- resets: A phandle to the reset line for PCIe glue layer including
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the host controller.
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- interrupts: A list of interrupt specifiers. According to the
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interrupt-names, appropriate interrupts are required.
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- interrupt-names: Must include the following entries:
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"dma" - DMA interrupt
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"msi" - MSI interrupt
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Optional properties:
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- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate
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phys are required.
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- phy-names: Must be "pcie-phy".
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Required sub-node:
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- legacy-interrupt-controller: Specifies interrupt controller for legacy PCI
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interrupts.
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Required properties for legacy-interrupt-controller:
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- interrupt-controller: identifies the node as an interrupt controller.
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- interrupt-parent: Phandle to the parent interrupt controller.
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- interrupts: An interrupt specifier for legacy interrupt.
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Example:
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pcie: pcie@66000000 {
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compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
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status = "disabled";
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reg-names = "dbi", "link", "config";
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reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
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<0x2fff0000 0x10000>;
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&sys_clk 24>;
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resets = <&sys_rst 24>;
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num-lanes = <1>;
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num-viewport = <1>;
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bus-range = <0x0 0xff>;
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device_type = "pci";
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ranges =
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/* downstream I/O */
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<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000
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/* non-prefetchable memory */
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0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
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#interrupt-cells = <1>;
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interrupt-names = "dma", "msi";
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interrupts = <0 224 4>, <0 225 4>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
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<0 0 0 2 &pcie_intc 1>, /* INTB */
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<0 0 0 3 &pcie_intc 2>, /* INTC */
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<0 0 0 4 &pcie_intc 3>; /* INTD */
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pcie_intc: legacy-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <0 226 4>;
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};
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};
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@ -11585,6 +11585,13 @@ S: Maintained
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F: Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
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F: drivers/pci/controller/pci-v3-semi.c
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PCIE DRIVER FOR SOCIONEXT UNIPHIER
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M: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/uniphier-pcie.txt
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F: drivers/pci/controller/dwc/pcie-uniphier.c
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PCIE DRIVER FOR ST SPEAR13XX
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M: Pratyush Anand <pratyush.anand@gmail.com>
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L: linux-pci@vger.kernel.org
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@ -203,4 +203,14 @@ config PCI_MESON
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and therefore the driver re-uses the DesignWare core functions to
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implement the driver.
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config PCIE_UNIPHIER
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bool "Socionext UniPhier PCIe controllers"
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && HAS_IOMEM
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support on UniPhier SoCs.
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This driver supports LD20 and PXs3 SoCs.
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endmenu
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@ -15,6 +15,7 @@ obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
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obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
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obj-$(CONFIG_PCI_MESON) += pci-meson.o
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obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
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# The following drivers are for devices that use the generic ACPI
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# pci_root.c driver but don't support standard ECAM config access.
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471
drivers/pci/controller/dwc/pcie-uniphier.c
Normal file
471
drivers/pci/controller/dwc/pcie-uniphier.c
Normal file
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@ -0,0 +1,471 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for UniPhier SoCs
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* Copyright 2018 Socionext Inc.
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* Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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*/
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "pcie-designware.h"
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#define PCL_PINCTRL0 0x002c
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#define PCL_PERST_PLDN_REGEN BIT(12)
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#define PCL_PERST_NOE_REGEN BIT(11)
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#define PCL_PERST_OUT_REGEN BIT(8)
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#define PCL_PERST_PLDN_REGVAL BIT(4)
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#define PCL_PERST_NOE_REGVAL BIT(3)
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#define PCL_PERST_OUT_REGVAL BIT(0)
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#define PCL_PIPEMON 0x0044
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#define PCL_PCLK_ALIVE BIT(15)
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#define PCL_APP_READY_CTRL 0x8008
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#define PCL_APP_LTSSM_ENABLE BIT(0)
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#define PCL_APP_PM0 0x8078
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#define PCL_SYS_AUX_PWR_DET BIT(8)
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#define PCL_RCV_INT 0x8108
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#define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17)
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#define PCL_CFG_BW_MGT_STATUS BIT(4)
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#define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3)
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#define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2)
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#define PCL_CFG_PME_MSI_STATUS BIT(1)
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#define PCL_RCV_INTX 0x810c
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#define PCL_RCV_INTX_ALL_ENABLE GENMASK(19, 16)
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#define PCL_RCV_INTX_ALL_MASK GENMASK(11, 8)
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#define PCL_RCV_INTX_MASK_SHIFT 8
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#define PCL_RCV_INTX_ALL_STATUS GENMASK(3, 0)
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#define PCL_RCV_INTX_STATUS_SHIFT 0
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#define PCL_STATUS_LINK 0x8140
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#define PCL_RDLH_LINK_UP BIT(1)
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#define PCL_XMLH_LINK_UP BIT(0)
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struct uniphier_pcie_priv {
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void __iomem *base;
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struct dw_pcie pci;
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struct clk *clk;
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struct reset_control *rst;
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struct phy *phy;
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struct irq_domain *legacy_irq_domain;
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};
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#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
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static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv,
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bool enable)
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{
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u32 val;
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val = readl(priv->base + PCL_APP_READY_CTRL);
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if (enable)
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val |= PCL_APP_LTSSM_ENABLE;
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else
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val &= ~PCL_APP_LTSSM_ENABLE;
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writel(val, priv->base + PCL_APP_READY_CTRL);
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}
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static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
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{
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u32 val;
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/* use auxiliary power detection */
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val = readl(priv->base + PCL_APP_PM0);
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val |= PCL_SYS_AUX_PWR_DET;
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writel(val, priv->base + PCL_APP_PM0);
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/* assert PERST# */
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val = readl(priv->base + PCL_PINCTRL0);
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val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
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| PCL_PERST_PLDN_REGVAL);
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val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
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| PCL_PERST_PLDN_REGEN;
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writel(val, priv->base + PCL_PINCTRL0);
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uniphier_pcie_ltssm_enable(priv, false);
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usleep_range(100000, 200000);
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/* deassert PERST# */
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val = readl(priv->base + PCL_PINCTRL0);
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val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
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writel(val, priv->base + PCL_PINCTRL0);
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}
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static int uniphier_pcie_wait_rc(struct uniphier_pcie_priv *priv)
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{
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u32 status;
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int ret;
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/* wait PIPE clock */
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ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
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status & PCL_PCLK_ALIVE, 100000, 1000000);
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if (ret) {
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dev_err(priv->pci.dev,
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"Failed to initialize controller in RC mode\n");
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return ret;
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}
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return 0;
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}
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static int uniphier_pcie_link_up(struct dw_pcie *pci)
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{
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struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
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u32 val, mask;
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val = readl(priv->base + PCL_STATUS_LINK);
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mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;
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return (val & mask) == mask;
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}
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static int uniphier_pcie_establish_link(struct dw_pcie *pci)
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{
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struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
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if (dw_pcie_link_up(pci))
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return 0;
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uniphier_pcie_ltssm_enable(priv, true);
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return dw_pcie_wait_for_link(pci);
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}
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static void uniphier_pcie_stop_link(struct dw_pcie *pci)
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{
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struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
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uniphier_pcie_ltssm_enable(priv, false);
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}
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static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv)
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{
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writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT);
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writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX);
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}
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static void uniphier_pcie_irq_disable(struct uniphier_pcie_priv *priv)
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{
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writel(0, priv->base + PCL_RCV_INT);
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writel(0, priv->base + PCL_RCV_INTX);
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}
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static void uniphier_pcie_irq_ack(struct irq_data *d)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
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u32 val;
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val = readl(priv->base + PCL_RCV_INTX);
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val &= ~PCL_RCV_INTX_ALL_STATUS;
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val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT);
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writel(val, priv->base + PCL_RCV_INTX);
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}
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static void uniphier_pcie_irq_mask(struct irq_data *d)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
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u32 val;
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val = readl(priv->base + PCL_RCV_INTX);
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val &= ~PCL_RCV_INTX_ALL_MASK;
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val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
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writel(val, priv->base + PCL_RCV_INTX);
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}
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static void uniphier_pcie_irq_unmask(struct irq_data *d)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
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u32 val;
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val = readl(priv->base + PCL_RCV_INTX);
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val &= ~PCL_RCV_INTX_ALL_MASK;
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val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
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writel(val, priv->base + PCL_RCV_INTX);
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}
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static struct irq_chip uniphier_pcie_irq_chip = {
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.name = "PCI",
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.irq_ack = uniphier_pcie_irq_ack,
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.irq_mask = uniphier_pcie_irq_mask,
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.irq_unmask = uniphier_pcie_irq_unmask,
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};
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static int uniphier_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &uniphier_pcie_irq_chip,
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handle_level_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops uniphier_intx_domain_ops = {
|
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.map = uniphier_pcie_intx_map,
|
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};
|
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static void uniphier_pcie_irq_handler(struct irq_desc *desc)
|
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{
|
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struct pcie_port *pp = irq_desc_get_handler_data(desc);
|
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
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struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
|
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struct irq_chip *chip = irq_desc_get_chip(desc);
|
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unsigned long reg;
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u32 val, bit, virq;
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|
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/* INT for debug */
|
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val = readl(priv->base + PCL_RCV_INT);
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|
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if (val & PCL_CFG_BW_MGT_STATUS)
|
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dev_dbg(pci->dev, "Link Bandwidth Management Event\n");
|
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if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
|
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dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n");
|
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if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
|
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dev_dbg(pci->dev, "Root Error\n");
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if (val & PCL_CFG_PME_MSI_STATUS)
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dev_dbg(pci->dev, "PME Interrupt\n");
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|
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writel(val, priv->base + PCL_RCV_INT);
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|
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/* INTx */
|
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chained_irq_enter(chip, desc);
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|
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val = readl(priv->base + PCL_RCV_INTX);
|
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reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
|
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|
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for_each_set_bit(bit, ®, PCI_NUM_INTX) {
|
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virq = irq_linear_revmap(priv->legacy_irq_domain, bit);
|
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generic_handle_irq(virq);
|
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}
|
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chained_irq_exit(chip, desc);
|
||||
}
|
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|
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static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
|
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{
|
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
|
||||
struct device_node *np = pci->dev->of_node;
|
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struct device_node *np_intc;
|
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|
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np_intc = of_get_child_by_name(np, "legacy-interrupt-controller");
|
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if (!np_intc) {
|
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dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n");
|
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return -EINVAL;
|
||||
}
|
||||
|
||||
pp->irq = irq_of_parse_and_map(np_intc, 0);
|
||||
if (!pp->irq) {
|
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dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
priv->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
|
||||
&uniphier_intx_domain_ops, pp);
|
||||
if (!priv->legacy_irq_domain) {
|
||||
dev_err(pci->dev, "Failed to get INTx domain\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler,
|
||||
pp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uniphier_pcie_host_init(struct pcie_port *pp)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
|
||||
int ret;
|
||||
|
||||
ret = uniphier_pcie_config_legacy_irq(pp);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
uniphier_pcie_irq_enable(priv);
|
||||
|
||||
dw_pcie_setup_rc(pp);
|
||||
ret = uniphier_pcie_establish_link(pci);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI))
|
||||
dw_pcie_msi_init(pp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
|
||||
.host_init = uniphier_pcie_host_init,
|
||||
};
|
||||
|
||||
static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct dw_pcie *pci = &priv->pci;
|
||||
struct pcie_port *pp = &pci->pp;
|
||||
struct device *dev = &pdev->dev;
|
||||
int ret;
|
||||
|
||||
pp->ops = &uniphier_pcie_host_ops;
|
||||
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
pp->msi_irq = platform_get_irq_byname(pdev, "msi");
|
||||
if (pp->msi_irq < 0)
|
||||
return pp->msi_irq;
|
||||
}
|
||||
|
||||
ret = dw_pcie_host_init(pp);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to initialize host (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(priv->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = reset_control_deassert(priv->rst);
|
||||
if (ret)
|
||||
goto out_clk_disable;
|
||||
|
||||
uniphier_pcie_init_rc(priv);
|
||||
|
||||
ret = phy_init(priv->phy);
|
||||
if (ret)
|
||||
goto out_rst_assert;
|
||||
|
||||
ret = uniphier_pcie_wait_rc(priv);
|
||||
if (ret)
|
||||
goto out_phy_exit;
|
||||
|
||||
return 0;
|
||||
|
||||
out_phy_exit:
|
||||
phy_exit(priv->phy);
|
||||
out_rst_assert:
|
||||
reset_control_assert(priv->rst);
|
||||
out_clk_disable:
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void uniphier_pcie_host_disable(struct uniphier_pcie_priv *priv)
|
||||
{
|
||||
uniphier_pcie_irq_disable(priv);
|
||||
phy_exit(priv->phy);
|
||||
reset_control_assert(priv->rst);
|
||||
clk_disable_unprepare(priv->clk);
|
||||
}
|
||||
|
||||
static const struct dw_pcie_ops dw_pcie_ops = {
|
||||
.start_link = uniphier_pcie_establish_link,
|
||||
.stop_link = uniphier_pcie_stop_link,
|
||||
.link_up = uniphier_pcie_link_up,
|
||||
};
|
||||
|
||||
static int uniphier_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct uniphier_pcie_priv *priv;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->pci.dev = dev;
|
||||
priv->pci.ops = &dw_pcie_ops;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
|
||||
priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res);
|
||||
if (IS_ERR(priv->pci.dbi_base))
|
||||
return PTR_ERR(priv->pci.dbi_base);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "link");
|
||||
priv->base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
|
||||
priv->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(priv->clk))
|
||||
return PTR_ERR(priv->clk);
|
||||
|
||||
priv->rst = devm_reset_control_get_shared(dev, NULL);
|
||||
if (IS_ERR(priv->rst))
|
||||
return PTR_ERR(priv->rst);
|
||||
|
||||
priv->phy = devm_phy_optional_get(dev, "pcie-phy");
|
||||
if (IS_ERR(priv->phy))
|
||||
return PTR_ERR(priv->phy);
|
||||
|
||||
platform_set_drvdata(pdev, priv);
|
||||
|
||||
ret = uniphier_pcie_host_enable(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return uniphier_add_pcie_port(priv, pdev);
|
||||
}
|
||||
|
||||
static int uniphier_pcie_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct uniphier_pcie_priv *priv = platform_get_drvdata(pdev);
|
||||
|
||||
uniphier_pcie_host_disable(priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id uniphier_pcie_match[] = {
|
||||
{ .compatible = "socionext,uniphier-pcie", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, uniphier_pcie_match);
|
||||
|
||||
static struct platform_driver uniphier_pcie_driver = {
|
||||
.probe = uniphier_pcie_probe,
|
||||
.remove = uniphier_pcie_remove,
|
||||
.driver = {
|
||||
.name = "uniphier-pcie",
|
||||
.of_match_table = uniphier_pcie_match,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(uniphier_pcie_driver);
|
||||
|
||||
MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
|
||||
MODULE_DESCRIPTION("UniPhier PCIe host controller driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user