mt76: mt7615: add dma and tx queue initialization for MT7622
MT7622 queue mapping is different from MT7615 and requires an extra dma scheduler init and a few register tweaks Co-developed-by: Shayne Chen <shayne.chen@mediatek.com> Co-developed-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Felix Fietkau
parent
853fb35c50
commit
cdad487405
@ -12,31 +12,7 @@
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#include "mac.h"
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static int
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mt7615_init_tx_queues(struct mt7615_dev *dev, int n_desc)
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{
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struct mt76_sw_queue *q;
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struct mt76_queue *hwq;
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int err, i;
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hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL);
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if (!hwq)
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return -ENOMEM;
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err = mt76_queue_alloc(dev, hwq, 0, n_desc, 0, MT_TX_RING_BASE);
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if (err < 0)
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return err;
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for (i = 0; i < MT_TXQ_MCU; i++) {
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q = &dev->mt76.q_tx[i];
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INIT_LIST_HEAD(&q->swq);
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q->q = hwq;
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}
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return 0;
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}
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static int
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mt7615_init_mcu_queue(struct mt7615_dev *dev, struct mt76_sw_queue *q,
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mt7615_init_tx_queue(struct mt7615_dev *dev, struct mt76_sw_queue *q,
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int idx, int n_desc)
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{
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struct mt76_queue *hwq;
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@ -56,6 +32,68 @@ mt7615_init_mcu_queue(struct mt7615_dev *dev, struct mt76_sw_queue *q,
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return 0;
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}
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static int
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mt7622_init_tx_queues_multi(struct mt7615_dev *dev)
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{
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static const u8 wmm_queue_map[] = {
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MT7622_TXQ_AC0,
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MT7622_TXQ_AC1,
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MT7622_TXQ_AC2,
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MT7622_TXQ_AC3,
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};
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int ret;
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int i;
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for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
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ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[i],
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wmm_queue_map[i],
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MT7615_TX_RING_SIZE / 2);
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if (ret)
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return ret;
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}
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ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_PSD],
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MT7622_TXQ_MGMT, MT7615_TX_MGMT_RING_SIZE);
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if (ret)
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return ret;
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ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU],
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MT7622_TXQ_MCU, MT7615_TX_MCU_RING_SIZE);
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return ret;
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}
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static int
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mt7615_init_tx_queues(struct mt7615_dev *dev)
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{
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struct mt76_sw_queue *q;
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int ret, i;
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ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_FWDL],
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MT7615_TXQ_FWDL,
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MT7615_TX_FWDL_RING_SIZE);
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if (ret)
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return ret;
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if (!is_mt7615(&dev->mt76))
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return mt7622_init_tx_queues_multi(dev);
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ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[0], 0,
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MT7615_TX_RING_SIZE);
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if (ret)
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return ret;
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for (i = 1; i < MT_TXQ_MCU; i++) {
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q = &dev->mt76.q_tx[i];
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INIT_LIST_HEAD(&q->swq);
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q->q = dev->mt76.q_tx[0].q;
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}
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ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU],
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MT7615_TXQ_MCU,
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MT7615_TX_MCU_RING_SIZE);
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return 0;
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}
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void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
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struct sk_buff *skb)
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{
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@ -90,25 +128,32 @@ void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
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}
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}
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static void
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mt7615_tx_cleanup(struct mt7615_dev *dev)
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{
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int i;
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mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false);
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if (is_mt7615(&dev->mt76)) {
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mt76_queue_tx_cleanup(dev, MT_TXQ_BE, false);
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} else {
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for (i = 0; i < IEEE80211_NUM_ACS; i++)
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mt76_queue_tx_cleanup(dev, i, false);
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}
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}
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static int mt7615_poll_tx(struct napi_struct *napi, int budget)
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{
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static const u8 queue_map[] = {
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MT_TXQ_MCU,
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MT_TXQ_BE
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};
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struct mt7615_dev *dev;
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int i;
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dev = container_of(napi, struct mt7615_dev, mt76.tx_napi);
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for (i = 0; i < ARRAY_SIZE(queue_map); i++)
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mt76_queue_tx_cleanup(dev, queue_map[i], false);
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mt7615_tx_cleanup(dev);
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if (napi_complete_done(napi, 0))
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mt7615_irq_enable(dev, MT_INT_TX_DONE_ALL);
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for (i = 0; i < ARRAY_SIZE(queue_map); i++)
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mt76_queue_tx_cleanup(dev, queue_map[i], false);
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mt7615_tx_cleanup(dev);
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mt7615_mac_sta_poll(dev);
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@ -117,6 +162,30 @@ static int mt7615_poll_tx(struct napi_struct *napi, int budget)
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return 0;
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}
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static void mt7622_dma_sched_init(struct mt7615_dev *dev)
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{
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u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE);
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int i;
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mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE,
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MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
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FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
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FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
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for (i = 0; i <= 5; i++)
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mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i),
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) |
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
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mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210);
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mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210);
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mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5);
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mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0);
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mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f);
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mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987);
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}
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int mt7615_dma_init(struct mt7615_dev *dev)
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{
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int ret;
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@ -126,9 +195,12 @@ int mt7615_dma_init(struct mt7615_dev *dev)
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mt76_wr(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE |
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MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN |
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MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY |
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MT_WPDMA_GLO_CFG_OMIT_TX_INFO);
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if (!is_mt7622(&dev->mt76))
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mt76_set(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY);
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mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1);
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@ -141,28 +213,19 @@ int mt7615_dma_init(struct mt7615_dev *dev)
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mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3);
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mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1);
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mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000);
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mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000);
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mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026);
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mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881);
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mt76_set(dev, 0x7158, BIT(16));
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mt76_clear(dev, 0x7000, BIT(23));
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if (is_mt7615(&dev->mt76)) {
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mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1);
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mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000);
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mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000);
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mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026);
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mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881);
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mt76_set(dev, 0x7158, BIT(16));
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mt76_clear(dev, 0x7000, BIT(23));
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}
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mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
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ret = mt7615_init_tx_queues(dev, MT7615_TX_RING_SIZE);
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if (ret)
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return ret;
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ret = mt7615_init_mcu_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU],
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MT7615_TXQ_MCU,
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MT7615_TX_MCU_RING_SIZE);
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if (ret)
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return ret;
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ret = mt7615_init_mcu_queue(dev, &dev->mt76.q_tx[MT_TXQ_FWDL],
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MT7615_TXQ_FWDL,
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MT7615_TX_FWDL_RING_SIZE);
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ret = mt7615_init_tx_queues(dev);
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if (ret)
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return ret;
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@ -201,6 +264,9 @@ int mt7615_dma_init(struct mt7615_dev *dev)
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/* enable interrupts for TX/RX rings */
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mt7615_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL);
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if (is_mt7622(&dev->mt76))
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mt7622_dma_sched_init(dev);
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return 0;
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}
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@ -20,6 +20,7 @@
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#define MT7615_RATE_RETRY 2
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#define MT7615_TX_RING_SIZE 1024
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#define MT7615_TX_MGMT_RING_SIZE 128
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#define MT7615_TX_MCU_RING_SIZE 128
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#define MT7615_TX_FWDL_RING_SIZE 128
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@ -56,6 +57,16 @@ enum mt7615_hw_txq_id {
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MT7615_TXQ_FWDL,
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};
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enum mt7622_hw_txq_id {
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MT7622_TXQ_AC0,
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MT7622_TXQ_AC1,
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MT7622_TXQ_AC2,
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MT7622_TXQ_FWDL = MT7615_TXQ_FWDL,
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MT7622_TXQ_AC3,
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MT7622_TXQ_MGMT,
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MT7622_TXQ_MCU = 15,
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};
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struct mt7615_rate_set {
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struct ieee80211_tx_rate probe_rate;
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struct ieee80211_tx_rate rates[4];
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@ -287,6 +298,11 @@ static inline bool is_mt7622(struct mt76_dev *dev)
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return mt76_chip(dev) == 0x7622;
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}
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static inline bool is_mt7615(struct mt76_dev *dev)
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{
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return mt76_chip(dev) == 0x7615;
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}
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static inline void mt7615_irq_enable(struct mt7615_dev *dev, u32 mask)
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{
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mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask);
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@ -339,6 +339,27 @@
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#define MT_TX_AGG_CNT(n) MT_WF_MIB(0xa8 + ((n) << 2))
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#define MT_DMASHDL_BASE 0x5000a000
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#define MT_DMASHDL_OPTIONAL 0x008
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#define MT_DMASHDL_PAGE 0x00c
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#define MT_DMASHDL_REFILL 0x010
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#define MT_DMASHDL_PKT_MAX_SIZE 0x01c
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#define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0)
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#define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16)
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#define MT_DMASHDL_GROUP_QUOTA(_n) (0x020 + ((_n) << 2))
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#define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0)
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#define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16)
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#define MT_DMASHDL_SCHED_SET0 0x0b0
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#define MT_DMASHDL_SCHED_SET1 0x0b4
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#define MT_DMASHDL_Q_MAP(_n) (0x0d0 + ((_n) << 2))
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#define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0)
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#define MT_DMASHDL_Q_MAP_SHIFT(_n) (4 * ((_n) % 8))
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#define MT_LED_BASE_PHYS 0x80024000
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#define MT_LED_PHYS(_n) (MT_LED_BASE_PHYS + (_n))
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