forked from Minki/linux
USB: ehci-fsl: Fix 'have_sysif_regs' detection
Previously a check was done on an ID register at the base of a CPU's internal USB registers to determine if system interface regsiters were present. The check looked for an ID register that had the format ID[0:5] == ~ID[8:13] as described in the MPC5121 User's Manual to determine if a MPC5121 or MPC83xx/85xx was being used. There are two issues with this method: - The ID register is not defined on the MPC83xx/85xx CPUs, so its unclear what is being checked on them. - Newer CPUs such as the P4080 also don't document the ID register, but do share the same format as the MPC5121. Thus the previous code did not set 'have_sysif_regs' properly which results in the P4080 not properly initializing its USB ports. Using the device tree 'compatible' node is a cleaner way to determine if 'have_sysif_regs' should be set and resolves the USB initialization issue seen on the P4080. Tested on a P4080-based system and compile tested on mpc512x_defconfig with Freescale EHCI driver enabled. Cc: Anatolij Gustschin <agust@denx.de> Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -52,7 +52,6 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
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struct resource *res;
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int irq;
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int retval;
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unsigned int temp;
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pr_debug("initializing FSL-SOC USB Controller\n");
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@ -126,18 +125,6 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
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goto err3;
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}
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/*
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* Check if it is MPC5121 SoC, otherwise set pdata->have_sysif_regs
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* flag for 83xx or 8536 system interface registers.
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*/
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if (pdata->big_endian_mmio)
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temp = in_be32(hcd->regs + FSL_SOC_USB_ID);
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else
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temp = in_le32(hcd->regs + FSL_SOC_USB_ID);
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if ((temp & ID_MSK) != (~((temp & NID_MSK) >> 8) & ID_MSK))
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pdata->have_sysif_regs = 1;
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/* Enable USB controller, 83xx or 8536 */
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if (pdata->have_sysif_regs)
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setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
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@ -19,9 +19,6 @@
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#define _EHCI_FSL_H
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/* offsets for the non-ehci registers in the FSL SOC USB controller */
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#define FSL_SOC_USB_ID 0x0
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#define ID_MSK 0x3f
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#define NID_MSK 0x3f00
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#define FSL_SOC_USB_ULPIVP 0x170
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#define FSL_SOC_USB_PORTSC1 0x184
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#define PORT_PTS_MSK (3<<30)
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@ -262,19 +262,24 @@ static void fsl_usb2_mpc5121_exit(struct platform_device *pdev)
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}
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}
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struct fsl_usb2_platform_data fsl_usb2_mpc5121_pd = {
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static struct fsl_usb2_platform_data fsl_usb2_mpc5121_pd = {
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.big_endian_desc = 1,
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.big_endian_mmio = 1,
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.es = 1,
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.have_sysif_regs = 0,
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.le_setup_buf = 1,
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.init = fsl_usb2_mpc5121_init,
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.exit = fsl_usb2_mpc5121_exit,
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};
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#endif /* CONFIG_PPC_MPC512x */
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static struct fsl_usb2_platform_data fsl_usb2_mpc8xxx_pd = {
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.have_sysif_regs = 1,
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};
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static const struct of_device_id fsl_usb2_mph_dr_of_match[] = {
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{ .compatible = "fsl-usb2-mph", },
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{ .compatible = "fsl-usb2-dr", },
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{ .compatible = "fsl-usb2-mph", .data = &fsl_usb2_mpc8xxx_pd, },
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{ .compatible = "fsl-usb2-dr", .data = &fsl_usb2_mpc8xxx_pd, },
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#ifdef CONFIG_PPC_MPC512x
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{ .compatible = "fsl,mpc5121-usb2-dr", .data = &fsl_usb2_mpc5121_pd, },
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#endif
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