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drm/amd/pp: Export new smu message for PCC feature on Vega10

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used to set PccThrottleLevel and PccResidencyThreshold

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu
2018-03-02 10:52:25 +08:00
committed by Alex Deucher
parent ada6770e95
commit cc1bb66fbc
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/amd/powerplay/inc/smu9.h
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@@ -58,7 +58,7 @@
#define FEATURE_FAST_PPT_BIT 26 #define FEATURE_FAST_PPT_BIT 26
#define FEATURE_GFX_EDC_BIT 27 #define FEATURE_GFX_EDC_BIT 27
#define FEATURE_ACG_BIT 28 #define FEATURE_ACG_BIT 28
#define FEATURE_SPARE_29_BIT 29 #define FEATURE_PCC_LIMIT_CONTROL_BIT 29
#define FEATURE_SPARE_30_BIT 30 #define FEATURE_SPARE_30_BIT 30
#define FEATURE_SPARE_31_BIT 31 #define FEATURE_SPARE_31_BIT 31
@@ -94,7 +94,7 @@
#define FEATURE_FAST_PPT_MASK (1 << FAST_PPT_BIT ) #define FEATURE_FAST_PPT_MASK (1 << FAST_PPT_BIT )
#define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT ) #define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT )
#define FEATURE_ACG_MASK (1 << FEATURE_ACG_BIT ) #define FEATURE_ACG_MASK (1 << FEATURE_ACG_BIT )
#define FFEATURE_SPARE_29_MASK (1 << FEATURE_SPARE_29_BIT ) #define FEATURE_PCC_LIMIT_CONTROL_MASK (1 << FEATURE_PCC_LIMIT_CONTROL_BIT )
#define FFEATURE_SPARE_30_MASK (1 << FEATURE_SPARE_30_BIT ) #define FFEATURE_SPARE_30_MASK (1 << FEATURE_SPARE_30_BIT )
#define FFEATURE_SPARE_31_MASK (1 << FEATURE_SPARE_31_BIT ) #define FFEATURE_SPARE_31_MASK (1 << FEATURE_SPARE_31_BIT )
/* Workload types */ /* Workload types */