forked from Minki/linux
MIPS: Extend hardware table walking support to MIPS64
Extend the existing support for Hardware Table Walking (HTW) to MIPS64 systems by supporting PMDs & setting the pointer size bit in PWSize, then ceasing to blacklist HTW on MIPS64 systems. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/11224/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -536,8 +536,7 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
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c->options |= MIPS_CPU_SEGMENTS;
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if (config3 & MIPS_CONF3_MSA)
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c->ases |= MIPS_ASE_MSA;
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/* Only tested on 32-bit cores */
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if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
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if (config3 & MIPS_CONF3_PW) {
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c->htw_seq = 0;
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c->options |= MIPS_CPU_HTW;
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}
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@ -2284,6 +2284,10 @@ static void config_htw_params(void)
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/* re-initialize the PTI field including the even/odd bit */
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pwfield &= ~MIPS_PWFIELD_PTI_MASK;
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pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
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if (CONFIG_PGTABLE_LEVELS >= 3) {
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pwfield &= ~MIPS_PWFIELD_MDI_MASK;
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pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;
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}
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/* Set the PTEI right shift */
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ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
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pwfield |= ptei;
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@ -2305,9 +2309,11 @@ static void config_htw_params(void)
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pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
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pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
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if (CONFIG_PGTABLE_LEVELS >= 3)
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pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
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/* If XPA has been enabled, PTEs are 64-bit in size. */
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if (read_c0_pagegrain() & PG_ELPA)
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if (config_enabled(CONFIG_64BITS) || (read_c0_pagegrain() & PG_ELPA))
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pwsize |= 1;
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write_c0_pwsize(pwsize);
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