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ARM: Remove support for LinkUp Systems L7200 SDP.

Browse Source 
This hasn't been actively maintained for a long time, only receiving
the occasional build update when things break.  I doubt anyone has
one of these on their desks anymore.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2010-06-24 15:41:31 +01:00
parent 7e27d6e778
commit c9c6fe5033
29 changed files with 0 additions and 1687 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm/Kconfig
View File

@ -439,21 +439,6 @@ config ARCH_IXP4XX
help
Support for Intel's IXP4XX (XScale) family of processors.
config ARCH_L7200
bool "LinkUp-L7200"
select CPU_ARM720T
select FIQ
select ARCH_USES_GETTIMEOFFSET
help
Say Y here if you intend to run this kernel on a LinkUp Systems
L7200 Software Development Board which uses an ARM720T processor.
Information on this board can be obtained at:
<http://www.linkupsys.com/>
If you have any questions or comments about the Linux kernel port
to this board, send e-mail to <sjhill@cotw.com>.
config ARCH_DOVE
bool "Marvell Dove"
select PCI
@ -1184,7 +1169,6 @@ source kernel/Kconfig.preempt
config HZ
int
default 128 if ARCH_L7200
default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
default AT91_TIMER_HZ if ARCH_AT91

1
arch/arm/Makefile
View File

@ -139,7 +139,6 @@ machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
machine-$(CONFIG_ARCH_KS8695) := ks8695
machine-$(CONFIG_ARCH_L7200) := l7200
machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
machine-$(CONFIG_ARCH_LOKI) := loki
machine-$(CONFIG_ARCH_MMP) := mmp

4
arch/arm/boot/compressed/Makefile
View File

@ -19,10 +19,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
OBJS += head-shark.o ofw-shark.o
endif
ifeq ($(CONFIG_ARCH_L7200),y)
OBJS += head-l7200.o
endif
ifeq ($(CONFIG_ARCH_P720T),y)
# Borrow this code from SA1100
OBJS += head-sa1100.o

29
arch/arm/boot/compressed/head-l7200.S
View File

@ -1,29 +0,0 @@
/*
* linux/arch/arm/boot/compressed/head-l7200.S
*
* Copyright (C) 2000 Steve Hill <sjhill@cotw.com>
*
* Some code borrowed from Nicolas Pitre's 'head-sa1100.S' file. This
* is merged with head.S by the linker.
*/
#include <asm/mach-types.h>
#ifndef CONFIG_ARCH_L7200
#error What am I doing here...
#endif
.section ".start", "ax"
__L7200_start:
mov r0, #0x00100000 @ FLASH address of initrd
mov r2, #0xf1000000 @ RAM address of initrd
add r3, r2, #0x00700000 @ Size of initrd
1:
ldmia r0!, {r4, r5, r6, r7}
stmia r2!, {r4, r5, r6, r7}
cmp r2, r3
ble 1b
mov r8, #0 @ Zero it out
mov r7, #MACH_TYPE_L7200 @ Set architecture ID

453
arch/arm/configs/lusl7200_defconfig
View File

@ -1,453 +0,0 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.12-rc1-bk2
# Mon Mar 28 00:24:38 2005
#
CONFIG_ARM=y
CONFIG_MMU=y
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_IOMAP=y
CONFIG_FIQ=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_BROKEN_ON_SMP=y
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
# CONFIG_HOTPLUG is not set
# CONFIG_IKCONFIG is not set
CONFIG_EMBEDDED=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SHMEM=y
CONFIG_CC_ALIGN_FUNCTIONS=0
CONFIG_CC_ALIGN_LABELS=0
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
#
# Loadable module support
#
CONFIG_MODULES=y
# CONFIG_MODULE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
#
# System Type
#
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_IOP3XX is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_IXP2000 is not set
CONFIG_ARCH_L7200=y
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_H720X is not set
#
# Processor Type
#
CONFIG_CPU_ARM720T=y
CONFIG_CPU_32v4=y
CONFIG_CPU_ABRT_LV4T=y
CONFIG_CPU_CACHE_V4=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_COPY_V4WT=y
CONFIG_CPU_TLB_V4WT=y
#
# Processor Features
#
# CONFIG_ARM_THUMB is not set
#
# Bus support
#
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# Kernel Features
#
# CONFIG_PREEMPT is not set
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x00010000
CONFIG_ZBOOT_ROM_BSS=0xf03e0000
CONFIG_ZBOOT_ROM=y
CONFIG_CMDLINE="console=tty0 console=ttyLU1,115200 root=/dev/ram initrd=0xf1000000,0x005dac7b mem=32M"
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
# CONFIG_FPE_NWFPE is not set
# CONFIG_FPE_FASTFPE is not set
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_AOUT=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_ARTHUR is not set
#
# Power management options
#
# CONFIG_PM is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CDROM_PKTCDVD is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_SCSI is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
#
# IEEE 1394 (FireWire) support
#
#
# I2O device support
#
#
# Networking support
#
# CONFIG_NET is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
#
# Input device support
#
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_SERPORT is not set
# CONFIG_SERIO_LIBPS2 is not set
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
#
# Character devices
#
# CONFIG_VT is not set
CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_COMPUTONE is not set
# CONFIG_ROCKETPORT is not set
# CONFIG_CYCLADES is not set
# CONFIG_DIGIEPCA is not set
# CONFIG_MOXA_INTELLIO is not set
# CONFIG_MOXA_SMARTIO is not set
# CONFIG_ISI is not set
# CONFIG_SYNCLINKMP is not set
# CONFIG_N_HDLC is not set
# CONFIG_RISCOM8 is not set
# CONFIG_SPECIALIX is not set
# CONFIG_SX is not set
# CONFIG_RIO is not set
# CONFIG_STALDRV is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# Misc devices
#
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
#
# Graphics support
#
# CONFIG_FB is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB is not set
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
#
# XFS support
#
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_SYSFS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVPTS_FS_XATTR is not set
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_FRAME_POINTER=y
CONFIG_DEBUG_USER=y
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
# Hardware crypto devices
#
#
# Library routines
#
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC32 is not set
# CONFIG_LIBCRC32C is not set

1
arch/arm/lib/Makefile
View File

@ -41,7 +41,6 @@ else
endif
lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o
lib-$(CONFIG_ARCH_L7200) += io-acorn.o
lib-$(CONFIG_ARCH_SHARK) += io-shark.o
$(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S

11
arch/arm/mach-l7200/Makefile
View File

@ -1,11 +0,0 @@
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := core.o
obj-m :=
obj-n :=
obj- :=

2
arch/arm/mach-l7200/Makefile.boot
View File

@ -1,2 +0,0 @@
zreladdr-y := 0xf0008000

100
arch/arm/mach-l7200/core.c
View File

@ -1,100 +0,0 @@
/*
* linux/arch/arm/mm/mm-lusl7200.c
*
* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
*
* Extra MM routines for L7200 architecture
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/device.h>
#include <asm/types.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/page.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
/*
* IRQ base register
*/
#define IRQ_BASE (IO_BASE_2 + 0x1000)
/*
* Normal IRQ registers
*/
#define IRQ_STATUS (*(volatile unsigned long *) (IRQ_BASE + 0x000))
#define IRQ_RAWSTATUS (*(volatile unsigned long *) (IRQ_BASE + 0x004))
#define IRQ_ENABLE (*(volatile unsigned long *) (IRQ_BASE + 0x008))
#define IRQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x00c))
#define IRQ_SOFT (*(volatile unsigned long *) (IRQ_BASE + 0x010))
#define IRQ_SOURCESEL (*(volatile unsigned long *) (IRQ_BASE + 0x018))
/*
* Fast IRQ registers
*/
#define FIQ_STATUS (*(volatile unsigned long *) (IRQ_BASE + 0x100))
#define FIQ_RAWSTATUS (*(volatile unsigned long *) (IRQ_BASE + 0x104))
#define FIQ_ENABLE (*(volatile unsigned long *) (IRQ_BASE + 0x108))
#define FIQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x10c))
#define FIQ_SOFT (*(volatile unsigned long *) (IRQ_BASE + 0x110))
#define FIQ_SOURCESEL (*(volatile unsigned long *) (IRQ_BASE + 0x118))
static void l7200_mask_irq(unsigned int irq)
{
IRQ_ENABLECLEAR = 1 << irq;
}
static void l7200_unmask_irq(unsigned int irq)
{
IRQ_ENABLE = 1 << irq;
}
static struct irq_chip l7200_irq_chip = {
.ack = l7200_mask_irq,
.mask = l7200_mask_irq,
.unmask = l7200_unmask_irq
};
static void __init l7200_init_irq(void)
{
int irq;
IRQ_ENABLECLEAR = 0xffffffff; /* clear all interrupt enables */
FIQ_ENABLECLEAR = 0xffffffff; /* clear all fast interrupt enables */
for (irq = 0; irq < NR_IRQS; irq++) {
set_irq_chip(irq, &l7200_irq_chip);
set_irq_flags(irq, IRQF_VALID);
set_irq_handler(irq, handle_level_irq);
}
init_FIQ();
}
static struct map_desc l7200_io_desc[] __initdata = {
{ IO_BASE, IO_START, IO_SIZE, MT_DEVICE },
{ IO_BASE_2, IO_START_2, IO_SIZE_2, MT_DEVICE },
{ AUX_BASE, AUX_START, AUX_SIZE, MT_DEVICE },
{ FLASH1_BASE, FLASH1_START, FLASH1_SIZE, MT_DEVICE },
{ FLASH2_BASE, FLASH2_START, FLASH2_SIZE, MT_DEVICE }
};
static void __init l7200_map_io(void)
{
iotable_init(l7200_io_desc, ARRAY_SIZE(l7200_io_desc));
}
MACHINE_START(L7200, "LinkUp Systems L7200")
/* Maintainer: Steve Hill / Scott McConnell */
.phys_io = 0x80040000,
.io_pg_offst = ((0xd0000000) >> 18) & 0xfffc,
.map_io = l7200_map_io,
.init_irq = l7200_init_irq,
MACHINE_END

28
arch/arm/mach-l7200/include/mach/aux_reg.h
View File

@ -1,28 +0,0 @@
/*
* arch/arm/mach-l7200/include/mach/aux_reg.h
*
* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
*
* Changelog:
* 08-02-2000 SJH Created file
*/
#ifndef _ASM_ARCH_AUXREG_H
#define _ASM_ARCH_AUXREG_H
#include <mach/hardware.h>
#define l7200aux_reg *((volatile unsigned int *) (AUX_BASE))
/*
* Auxillary register values
*/
#define AUX_CLEAR 0x00000000
#define AUX_DIAG_LED_ON 0x00000002
#define AUX_RTS_UART1 0x00000004
#define AUX_DTR_UART1 0x00000008
#define AUX_KBD_COLUMN_12_HIGH 0x00000010
#define AUX_KBD_COLUMN_12_OFF 0x00000020
#define AUX_KBD_COLUMN_13_HIGH 0x00000040
#define AUX_KBD_COLUMN_13_OFF 0x00000080
#endif

40
arch/arm/mach-l7200/include/mach/debug-macro.S
View File

@ -1,40 +0,0 @@
/* arch/arm/mach-l7200/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
.equ io_virt, IO_BASE
.equ io_phys, IO_START
.macro addruart, rx, tmp
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #io_phys @ physical base address
movne \rx, #io_virt @ virtual address
add \rx, \rx, #0x00044000 @ UART1
@ add \rx, \rx, #0x00045000 @ UART2
.endm
.macro senduart,rd,rx
str \rd, [\rx, #0x0] @ UARTDR
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
bne 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
bne 1001b
.endm

35
arch/arm/mach-l7200/include/mach/entry-macro.S
View File

@ -1,35 +0,0 @@
/*
* arch/arm/mach-l7200/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for L7200-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/hardware.h>
.equ irq_base_addr, IO_BASE_2
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqstat, #irq_base_addr @ Virt addr IRQ regs
add \irqstat, \irqstat, #0x00001000 @ Status reg
ldr \irqstat, [\irqstat, #0] @ get interrupts
mov \irqnr, #0
1001: tst \irqstat, #1
addeq \irqnr, \irqnr, #1
moveq \irqstat, \irqstat, lsr #1
tsteq \irqnr, #32
beq 1001b
teq \irqnr, #32
.endm

42
arch/arm/mach-l7200/include/mach/gp_timers.h
View File

@ -1,42 +0,0 @@
/*
* arch/arm/mach-l7200/include/mach/gp_timers.h
*
* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
*
* Changelog:
* 07-28-2000 SJH Created file
* 08-02-2000 SJH Used structure for registers
*/
#ifndef _ASM_ARCH_GPTIMERS_H
#define _ASM_ARCH_GPTIMERS_H
#include <mach/hardware.h>
/*
* Layout of L7200 general purpose timer registers
*/
struct GPT_Regs {
unsigned int TIMERLOAD;
unsigned int TIMERVALUE;
unsigned int TIMERCONTROL;
unsigned int TIMERCLEAR;
};
#define GPT_BASE (IO_BASE_2 + 0x3000)
#define l7200_timer1_regs ((volatile struct GPT_Regs *) (GPT_BASE))
#define l7200_timer2_regs ((volatile struct GPT_Regs *) (GPT_BASE + 0x20))
/*
* General register values
*/
#define GPT_PRESCALE_1 0x00000000
#define GPT_PRESCALE_16 0x00000004
#define GPT_PRESCALE_256 0x00000008
#define GPT_MODE_FREERUN 0x00000000
#define GPT_MODE_PERIODIC 0x00000040
#define GPT_ENABLE 0x00000080
#define GPT_BZTOG 0x00000100
#define GPT_BZMOD 0x00000200
#define GPT_LOAD_MASK 0x0000ffff
#endif

105
arch/arm/mach-l7200/include/mach/gpio.h
View File

@ -1,105 +0,0 @@
/****************************************************************************/
/*
* arch/arm/mach-l7200/include/mach/gpio.h
*
* Registers and helper functions for the L7200 Link-Up Systems
* GPIO.
*
* (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
/****************************************************************************/
#define GPIO_OFF 0x00005000 /* Offset from IO_START to the GPIO reg's. */
/* IO_START and IO_BASE are defined in hardware.h */
#define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */
#define GPIO_BASE (IO_BASE_2 + GPIO_OFF) /* Virtual addr of the GPIO reg. */
/* Offsets from the start of the GPIO for all the registers. */
#define PADR_OFF 0x000
#define PADDR_OFF 0x004
#define PASBSR_OFF 0x008
#define PAEENR_OFF 0x00c
#define PAESNR_OFF 0x010
#define PAESTR_OFF 0x014
#define PAIMR_OFF 0x018
#define PAINT_OFF 0x01c
#define PBDR_OFF 0x020
#define PBDDR_OFF 0x024
#define PBSBSR_OFF 0x028
#define PBIMR_OFF 0x038
#define PBINT_OFF 0x03c
#define PCDR_OFF 0x040
#define PCDDR_OFF 0x044
#define PCSBSR_OFF 0x048
#define PCIMR_OFF 0x058
#define PCINT_OFF 0x05c
#define PDDR_OFF 0x060
#define PDDDR_OFF 0x064
#define PDSBSR_OFF 0x068
#define PDEENR_OFF 0x06c
#define PDESNR_OFF 0x070
#define PDESTR_OFF 0x074
#define PDIMR_OFF 0x078
#define PDINT_OFF 0x07c
#define PEDR_OFF 0x080
#define PEDDR_OFF 0x084
#define PESBSR_OFF 0x088
#define PEEENR_OFF 0x08c
#define PEESNR_OFF 0x090
#define PEESTR_OFF 0x094
#define PEIMR_OFF 0x098
#define PEINT_OFF 0x09c
/* Define the GPIO registers for use by device drivers and the kernel. */
#define PADR (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF))
#define PADDR (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF))
#define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF))
#define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF))
#define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF))
#define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF))
#define PAIMR (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF))
#define PAINT (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF))
#define PBDR (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF))
#define PBDDR (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF))
#define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF))
#define PBIMR (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF))
#define PBINT (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF))
#define PCDR (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF))
#define PCDDR (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF))
#define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF))
#define PCIMR (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF))
#define PCINT (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF))
#define PDDR (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF))
#define PDDDR (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF))
#define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF))
#define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF))
#define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF))
#define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF))
#define PDIMR (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF))
#define PDINT (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF))
#define PEDR (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF))
#define PEDDR (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF))
#define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF))
#define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF))
#define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF))
#define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF))
#define PEIMR (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF))
#define PEINT (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF))
#define VEE_EN 0x02
#define BACKLIGHT_EN 0x04

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arch/arm/mach-l7200/include/mach/hardware.h
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/*
* arch/arm/mach-l7200/include/mach/hardware.h
*
* Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
* Steve Hill (sjhill@cotw.com)
*
* This file contains the hardware definitions for the
* LinkUp Systems L7200 SOC development board.
*
* Changelog:
* 02-01-2000 RS Created L7200 version, derived from rpc code
* 03-21-2000 SJH Cleaned up file
* 04-21-2000 RS Changed mapping of I/O in virtual space
* 04-25-2000 SJH Removed unused symbols and such
* 05-05-2000 SJH Complete rewrite
* 07-31-2000 SJH Added undocumented debug auxillary port to
* get at last two columns for keyboard driver
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/* Hardware addresses of major areas.
* *_START is the physical address
* *_SIZE is the size of the region
* *_BASE is the virtual address
*/
#define RAM_START 0xf0000000
#define RAM_SIZE 0x02000000
#define RAM_BASE 0xc0000000
#define IO_START 0x80000000 /* I/O */
#define IO_SIZE 0x01000000
#define IO_BASE 0xd0000000
#define IO_START_2 0x90000000 /* I/O */
#define IO_SIZE_2 0x01000000
#define IO_BASE_2 0xd1000000
#define AUX_START 0x1a000000 /* AUX PORT */
#define AUX_SIZE 0x01000000
#define AUX_BASE 0xd2000000
#define FLASH1_START 0x00000000 /* FLASH BANK 1 */
#define FLASH1_SIZE 0x01000000
#define FLASH1_BASE 0xd3000000
#define FLASH2_START 0x10000000 /* FLASH BANK 2 */
#define FLASH2_SIZE 0x01000000
#define FLASH2_BASE 0xd4000000
#define ISA_START 0x20000000 /* ISA */
#define ISA_SIZE 0x20000000
#define ISA_BASE 0xe0000000
#define PCIO_BASE IO_BASE
#endif

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arch/arm/mach-l7200/include/mach/io.h
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/*
* arch/arm/mach-l7200/include/mach/io.h
*
* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
*
* Changelog:
* 03-21-2000 SJH Created from arch/arm/mach-nexuspci/include/mach/io.h
* 08-31-2000 SJH Added in IO functions necessary for new drivers
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
/*
* There are not real ISA nor PCI buses, so we fake it.
*/
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

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arch/arm/mach-l7200/include/mach/irqs.h
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/*
* arch/arm/mach-l7200/include/mach/irqs.h
*
* Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
* Steve Hill (sjhill@cotw.com)
*
* Changelog:
* 01-02-2000 RS Create l7200 version
* 03-28-2000 SJH Removed unused interrupt
* 07-28-2000 SJH Added pseudo-keyboard interrupt
*/
/*
* NOTE: The second timer (Timer 2) is used as the keyboard
* interrupt when the keyboard driver is enabled.
*/
#define NR_IRQS 32
#define IRQ_STWDOG 0 /* Watchdog timer */
#define IRQ_PROG 1 /* Programmable interrupt */
#define IRQ_DEBUG_RX 2 /* Comm Rx debug */
#define IRQ_DEBUG_TX 3 /* Comm Tx debug */
#define IRQ_GCTC1 4 /* Timer 1 */
#define IRQ_GCTC2 5 /* Timer 2 / Keyboard */
#define IRQ_DMA 6 /* DMA controller */
#define IRQ_CLCD 7 /* Color LCD controller */
#define IRQ_SM_RX 8 /* Smart card */
#define IRQ_SM_TX 9 /* Smart cart */
#define IRQ_SM_RST 10 /* Smart card */
#define IRQ_SIB 11 /* Serial Interface Bus */
#define IRQ_MMC 12 /* MultiMediaCard */
#define IRQ_SSP1 13 /* Synchronous Serial Port 1 */
#define IRQ_SSP2 14 /* Synchronous Serial Port 1 */
#define IRQ_SPI 15 /* SPI slave */
#define IRQ_UART_1 16 /* UART 1 */
#define IRQ_UART_2 17 /* UART 2 */
#define IRQ_IRDA 18 /* IRDA */
#define IRQ_RTC_TICK 19 /* Real Time Clock tick */
#define IRQ_RTC_ALARM 20 /* Real Time Clock alarm */
#define IRQ_GPIO 21 /* General Purpose IO */
#define IRQ_GPIO_DMA 22 /* General Purpose IO, DMA */
#define IRQ_M2M 23 /* Memory to memory DMA */
#define IRQ_RESERVED 24 /* RESERVED, don't use */
#define IRQ_INTF 25 /* External active low interrupt */
#define IRQ_INT0 26 /* External active low interrupt */
#define IRQ_INT1 27 /* External active low interrupt */
#define IRQ_INT2 28 /* External active low interrupt */
#define IRQ_UCB1200 29 /* Interrupt generated by UCB1200*/
#define IRQ_BAT_LO 30 /* Low batery or external power */
#define IRQ_MEDIA_CHG 31 /* Media change interrupt */
/*
* This is the offset of the FIQ "IRQ" numbers
*/
#define FIQ_START 64

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arch/arm/mach-l7200/include/mach/memory.h
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/*
* arch/arm/mach-l7200/include/mach/memory.h
*
* Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
* Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
*
* Changelog:
* 03-13-2000 SJH Created
* 04-13-2000 RS Changed bus macros for new addr
* 05-03-2000 SJH Removed bus macros and fixed virt_to_phys macro
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset on the L7200 SDB.
*/
#define PHYS_OFFSET UL(0xf0000000)
/*
* Cache flushing area - ROM
*/
#define FLUSH_BASE_PHYS 0x40000000
#define FLUSH_BASE 0xdf000000
#endif

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arch/arm/mach-l7200/include/mach/pmpcon.h
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/****************************************************************************/
/*
* arch/arm/mach-l7200/include/mach/pmpcon.h
*
* Registers and helper functions for the L7200 Link-Up Systems
* DC/DC converter register.
*
* (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
/****************************************************************************/
#define PMPCON_OFF 0x00006000 /* Offset from IO_START_2. */
/* IO_START_2 and IO_BASE_2 are defined in hardware.h */
#define PMPCON_START (IO_START_2 + PMPCON_OFF) /* Physical address of reg. */
#define PMPCON_BASE (IO_BASE_2 + PMPCON_OFF) /* Virtual address of reg. */
#define PMPCON (*(volatile unsigned int *)(PMPCON_BASE))
#define PWM2_50CYCLE 0x800
#define CONTRAST 0x9
#define PWM1H (CONTRAST)
#define PWM1L (CONTRAST << 4)
#define PMPCON_VALUE (PWM2_50CYCLE | PWM1L | PWM1H)
/* PMPCON = 0x811; // too light and fuzzy
* PMPCON = 0x844;
* PMPCON = 0x866; // better color poor depth
* PMPCON = 0x888; // Darker but better depth
* PMPCON = 0x899; // Darker even better depth
* PMPCON = 0x8aa; // too dark even better depth
* PMPCON = 0X8cc; // Way too dark
*/
/* As CONTRAST value increases the greater the depth perception and
* the darker the colors.
*/

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arch/arm/mach-l7200/include/mach/pmu.h
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/****************************************************************************/
/*
* arch/arm/mach-l7200/include/mach/pmu.h
*
* Registers and helper functions for the L7200 Link-Up Systems
* Power Management Unit (PMU).
*
* (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
/****************************************************************************/
#define PMU_OFF 0x00050000 /* Offset from IO_START to the PMU registers. */
/* IO_START and IO_BASE are defined in hardware.h */
#define PMU_START (IO_START + PMU_OFF) /* Physical addr. of the PMU reg. */
#define PMU_BASE (IO_BASE + PMU_OFF) /* Virtual addr. of the PMU reg. */
/* Define the PMU registers for use by device drivers and the kernel. */
typedef struct {
unsigned int CURRENT; /* Current configuration register */
unsigned int NEXT; /* Next configuration register */
unsigned int reserved;
unsigned int RUN; /* Run configuration register */
unsigned int COMM; /* Configuration command register */
unsigned int SDRAM; /* SDRAM configuration bypass register */
} pmu_interface;
#define PMU ((volatile pmu_interface *)(PMU_BASE))
/* Macro's for reading the common register fields. */
#define GET_TRANSOP(reg) ((reg >> 25) & 0x03) /* Bits 26-25 */
#define GET_OSCEN(reg) ((reg >> 16) & 0x01)
#define GET_OSCMUX(reg) ((reg >> 15) & 0x01)
#define GET_PLLMUL(reg) ((reg >> 9) & 0x3f) /* Bits 14-9 */
#define GET_PLLEN(reg) ((reg >> 8) & 0x01)
#define GET_PLLMUX(reg) ((reg >> 7) & 0x01)
#define GET_BCLK_DIV(reg) ((reg >> 3) & 0x03) /* Bits 4-3 */
#define GET_SDRB_SEL(reg) ((reg >> 2) & 0x01)
#define GET_SDRF_SEL(reg) ((reg >> 1) & 0x01)
#define GET_FASTBUS(reg) (reg & 0x1)
/* CFG_NEXT register */
#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f) /* Bits 24-18 */
#define CFG_NEXT_INTRET ((PMU->NEXT >> 17) & 0x01)
#define CFG_NEXT_SDR_STOP ((PMU->NEXT >> 6) & 0x01)
#define CFG_NEXT_SYSCLKEN ((PMU->NEXT >> 5) & 0x01)
/* Useful field values that can be used to construct the
* CFG_NEXT and CFG_RUN registers.
*/
#define TRANSOP_NOP 0<<25 /* NOCHANGE_NOSTALL */
#define NOCHANGE_STALL 1<<25
#define CHANGE_NOSTALL 2<<25
#define CHANGE_STALL 3<<25
#define INTRET 1<<17
#define OSCEN 1<<16
#define OSCMUX 1<<15
/* PLL frequencies */
#define PLLMUL_0 0<<9 /* 3.6864 MHz */
#define PLLMUL_1 1<<9 /* ?????? MHz */
#define PLLMUL_5 5<<9 /* 18.432 MHz */
#define PLLMUL_10 10<<9 /* 36.864 MHz */
#define PLLMUL_18 18<<9 /* ?????? MHz */
#define PLLMUL_20 20<<9 /* 73.728 MHz */
#define PLLMUL_32 32<<9 /* ?????? MHz */
#define PLLMUL_35 35<<9 /* 129.024 MHz */
#define PLLMUL_36 36<<9 /* ?????? MHz */
#define PLLMUL_39 39<<9 /* ?????? MHz */
#define PLLMUL_40 40<<9 /* 147.456 MHz */
/* Clock recovery times */
#define CRCLOCK_1 1<<18
#define CRCLOCK_2 2<<18
#define CRCLOCK_4 4<<18
#define CRCLOCK_8 8<<18
#define CRCLOCK_16 16<<18
#define CRCLOCK_32 32<<18
#define CRCLOCK_63 63<<18
#define CRCLOCK_127 127<<18
#define PLLEN 1<<8
#define PLLMUX 1<<7
#define SDR_STOP 1<<6
#define SYSCLKEN 1<<5
#define BCLK_DIV_4 2<<3
#define BCLK_DIV_2 1<<3
#define BCLK_DIV_1 0<<3
#define SDRB_SEL 1<<2
#define SDRF_SEL 1<<1
#define FASTBUS 1<<0
/* CFG_SDRAM */
#define SDRREFFQ 1<<0 /* Only if SDRSTOPRQ is not set. */
#define SDRREFACK 1<<1 /* Read-only */
#define SDRSTOPRQ 1<<2 /* Only if SDRREFFQ is not set. */
#define SDRSTOPACK 1<<3 /* Read-only */
#define PICEN 1<<4 /* Enable Co-procesor */
#define PICTEST 1<<5
#define GET_SDRREFFQ ((PMU->SDRAM >> 0) & 0x01)
#define GET_SDRREFACK ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
#define GET_SDRSTOPRQ ((PMU->SDRAM >> 2) & 0x01)
#define GET_SDRSTOPACK ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
#define GET_PICEN ((PMU->SDRAM >> 4) & 0x01)
#define GET_PICTEST ((PMU->SDRAM >> 5) & 0x01)

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arch/arm/mach-l7200/include/mach/serial.h
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/*
* arch/arm/mach-l7200/include/mach/serial.h
*
* Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
* Steve Hill (sjhill@cotw.com)
*
* Changelog:
* 03-20-2000 SJH Created
* 03-26-2000 SJH Added flags for serial ports
* 03-27-2000 SJH Corrected BASE_BAUD value
* 04-14-2000 RS Made register addr dependent on IO_BASE
* 05-03-2000 SJH Complete rewrite
* 05-09-2000 SJH Stripped out architecture specific serial stuff
* and placed it in a separate file
* 07-28-2000 SJH Moved base baud rate variable
*/
#ifndef __ASM_ARCH_SERIAL_H
#define __ASM_ARCH_SERIAL_H
/*
* This assumes you have a 3.6864 MHz clock for your UART.
*/
#define BASE_BAUD 3686400
/*
* Standard COM flags
*/
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
#define STD_SERIAL_PORT_DEFNS \
/* MAGIC UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS }, /* ttyLU0 */ \
{ 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS }, /* ttyLU1 */ \
#define EXTRA_SERIAL_PORT_DEFNS
#endif

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arch/arm/mach-l7200/include/mach/serial_l7200.h
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/*
* arch/arm/mach-l7200/include/mach/serial_l7200.h
*
* Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
*
* Changelog:
* 05-09-2000 SJH Created
*/
#ifndef __ASM_ARCH_SERIAL_L7200_H
#define __ASM_ARCH_SERIAL_L7200_H
#include <mach/memory.h>
/*
* This assumes you have a 3.6864 MHz clock for your UART.
*/
#define BASE_BAUD 3686400
/*
* UART base register addresses
*/
#define UART1_BASE (IO_BASE + 0x00044000)
#define UART2_BASE (IO_BASE + 0x00045000)
/*
* UART register offsets
*/
#define UARTDR 0x00 /* Tx/Rx data */
#define RXSTAT 0x04 /* Rx status */
#define H_UBRLCR 0x08 /* mode register high */
#define M_UBRLCR 0x0C /* mode reg mid (MSB of baud)*/
#define L_UBRLCR 0x10 /* mode reg low (LSB of baud)*/
#define UARTCON 0x14 /* control register */
#define UARTFLG 0x18 /* flag register */
#define UARTINTSTAT 0x1C /* FIFO IRQ status register */
#define UARTINTMASK 0x20 /* FIFO IRQ mask register */
/*
* UART baud rate register values
*/
#define BR_110 0x827
#define BR_1200 0x06e
#define BR_2400 0x05f
#define BR_4800 0x02f
#define BR_9600 0x017
#define BR_14400 0x00f
#define BR_19200 0x00b
#define BR_38400 0x005
#define BR_57600 0x003
#define BR_76800 0x002
#define BR_115200 0x001
/*
* Receiver status register (RXSTAT) mask values
*/
#define RXSTAT_NO_ERR 0x00 /* No error */
#define RXSTAT_FRM_ERR 0x01 /* Framing error */
#define RXSTAT_PAR_ERR 0x02 /* Parity error */
#define RXSTAT_OVR_ERR 0x04 /* Overrun error */
/*
* High byte of UART bit rate and line control register (H_UBRLCR) values
*/
#define UBRLCR_BRK 0x01 /* generate break on tx */
#define UBRLCR_PEN 0x02 /* enable parity */
#define UBRLCR_PDIS 0x00 /* disable parity */
#define UBRLCR_EVEN 0x04 /* 1= even parity,0 = odd parity */
#define UBRLCR_STP2 0x08 /* transmit 2 stop bits */
#define UBRLCR_FIFO 0x10 /* enable FIFO */
#define UBRLCR_LEN5 0x60 /* word length5 */
#define UBRLCR_LEN6 0x40 /* word length6 */
#define UBRLCR_LEN7 0x20 /* word length7 */
#define UBRLCR_LEN8 0x00 /* word length8 */
/*
* UART control register (UARTCON) values
*/
#define UARTCON_UARTEN 0x01 /* Enable UART */
#define UARTCON_DMAONERR 0x08 /* Mask RxDmaRq when errors occur */
/*
* UART flag register (UARTFLG) mask values
*/
#define UARTFLG_UTXFF 0x20 /* Transmit FIFO full */
#define UARTFLG_URXFE 0x10 /* Receiver FIFO empty */
#define UARTFLG_UBUSY 0x08 /* Transmitter busy */
#define UARTFLG_DCD 0x04 /* Data carrier detect */
#define UARTFLG_DSR 0x02 /* Data set ready */
#define UARTFLG_CTS 0x01 /* Clear to send */
/*
* UART interrupt status/clear registers (UARTINTSTAT/CLR) values
*/
#define UART_TXINT 0x01 /* TX interrupt */
#define UART_RXINT 0x02 /* RX interrupt */
#define UART_RXERRINT 0x04 /* RX error interrupt */
#define UART_MSINT 0x08 /* Modem Status interrupt */
#define UART_UDINT 0x10 /* UART Disabled interrupt */
#define UART_ALLIRQS 0x1f /* All interrupts */
#endif

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arch/arm/mach-l7200/include/mach/sib.h
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/****************************************************************************/
/*
* arch/arm/mach-l7200/include/mach/sib.h
*
* Registers and helper functions for the Serial Interface Bus.
*
* (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
/****************************************************************************/
#define SIB_OFF 0x00040000 /* Offset from IO_START to the SIB reg's. */
/* IO_START and IO_BASE are defined in hardware.h */
#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */
#define SIB_BASE (IO_BASE + SIB_OFF) /* Virtual addr of the SIB reg. */
/* Offsets from the start of the SIB for all the registers. */
/* Define the SIB registers for use by device drivers and the kernel. */
typedef struct
{
unsigned int MCCR; /* SIB Control Register Offset: 0x00 */
unsigned int RES1; /* Reserved Offset: 0x04 */
unsigned int MCDR0; /* SIB Data Register 0 Offset: 0x08 */
unsigned int MCDR1; /* SIB Data Register 1 Offset: 0x0c */
unsigned int MCDR2; /* SIB Data Register 2 (UCB1x00) Offset: 0x10 */
unsigned int RES2; /* Reserved Offset: 0x14 */
unsigned int MCSR; /* SIB Status Register Offset: 0x18 */
} SIB_Interface;
#define SIB ((volatile SIB_Interface *) (SIB_BASE))
/* MCCR */
#define INTERNAL_FREQ 9216000 /* Hertz */
#define AUDIO_FREQ 5000 /* Hertz */
#define TELECOM_FREQ 5000 /* Hertz */
#define AUDIO_DIVIDE (INTERNAL_FREQ / (32 * AUDIO_FREQ))
#define TELECOM_DIVIDE (INTERNAL_FREQ / (32 * TELECOM_FREQ))
#define MCCR_ASD57 AUDIO_DIVIDE
#define MCCR_TSD57 (TELECOM_DIVIDE << 8)
#define MCCR_MCE (1 << 16) /* SIB enable */
#define MCCR_ECS (1 << 17) /* External Clock Select */
#define MCCR_ADM (1 << 18) /* A/D Data Sampling */
#define MCCR_PMC (1 << 26) /* PIN Multiplexer Control */
#define GET_ASD ((SIB->MCCR >> 0) & 0x3f) /* Audio Sample Rate Div. */
#define GET_TSD ((SIB->MCCR >> 8) & 0x3f) /* Telcom Sample Rate Div. */
#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */
#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */
#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */
#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */
#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */
#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */
#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */
#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */
#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */
#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */
#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */
#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */
/* MCDR0 */
#define AUDIO_RECV ((SIB->MCDR0 >> 4) & 0xfff)
#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4))
/* MCDR1 */
#define TELECOM_RECV ((SIB->MCDR1 >> 2) & 032fff)
#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2))
/* MCSR */
#define MCSR_ATU (1 << 4) /* Audio Transmit FIFO Underrun */
#define MCSR_ARO (1 << 5) /* Audio Receive FIFO Underrun */
#define MCSR_TTU (1 << 6) /* TELECOM Transmit FIFO Underrun */
#define MCSR_TRO (1 << 7) /* TELECOM Receive FIFO Underrun */
#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO)
#define GET_ATS ((SIB->MCSR >> 0) & 0x01) /* Audio Transmit FIFO Service Req*/
#define GET_ARS ((SIB->MCSR >> 1) & 0x01) /* Audio Recv FIFO Service Request*/
#define GET_TTS ((SIB->MCSR >> 2) & 0x01) /* TELECOM Transmit FIFO Flag */
#define GET_TRS ((SIB->MCSR >> 3) & 0x01) /* TELECOM Recv FIFO Service Req. */
#define GET_ATU ((SIB->MCSR >> 4) & 0x01) /* Audio Transmit FIFO Underrun */
#define GET_ARO ((SIB->MCSR >> 5) & 0x01) /* Audio Receive FIFO Underrun */
#define GET_TTU ((SIB->MCSR >> 6) & 0x01) /* TELECOM Transmit FIFO Underrun */
#define GET_TRO ((SIB->MCSR >> 7) & 0x01) /* TELECOM Receive FIFO Underrun */
#define GET_ANF ((SIB->MCSR >> 8) & 0x01) /* Audio Transmit FIFO not full */
#define GET_ANE ((SIB->MCSR >> 9) & 0x01) /* Audio Receive FIFO not empty */
#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */
#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */
#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */
#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */
#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */
#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */
/* MCDR2 */
#define MCDR2_rW (1 << 16)
#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff)))
#define MCDR2_WRITE_COMPLETE GET_CWC
#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17))
#define MCDR2_READ_COMPLETE GET_CRC
#define MCDR2_READ (SIB->MCDR2 & 0xffff)

67
arch/arm/mach-l7200/include/mach/sys-clock.h
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@ -1,67 +0,0 @@
/****************************************************************************/
/*
* arch/arm/mach-l7200/include/mach/sys-clock.h
*
* Registers and helper functions for the L7200 Link-Up Systems
* System clocks.
*
* (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
/****************************************************************************/
#define SYS_CLOCK_OFF 0x00050030 /* Offset from IO_START. */
/* IO_START and IO_BASE are defined in hardware.h */
#define SYS_CLOCK_START (IO_START + SYS_CLOCK_OFF) /* Physical address */
#define SYS_CLOCK_BASE (IO_BASE + SYS_CLOCK_OFF) /* Virtual address */
/* Define the interface to the SYS_CLOCK */
typedef struct
{
unsigned int ENABLE;
unsigned int ESYNC;
unsigned int SELECT;
} sys_clock_interface;
#define SYS_CLOCK ((volatile sys_clock_interface *)(SYS_CLOCK_BASE))
//#define CLOCK_EN (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF))
//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF))
//#define CLOCK_SEL (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF))
/* SYS_CLOCK -> ENABLE */
#define SYN_EN 1<<0
#define B18M_EN 1<<1
#define CLK3M6_EN 1<<2
#define BUART_EN 1<<3
#define CLK18MU_EN 1<<4
#define FIR_EN 1<<5
#define MIRN_EN 1<<6
#define UARTM_EN 1<<7
#define SIBADC_EN 1<<8
#define ALTD_EN 1<<9
#define CLCLK_EN 1<<10
/* SYS_CLOCK -> SELECT */
#define CLK18M_DIV 1<<0
#define MIR_SEL 1<<1
#define SSP_SEL 1<<4
#define MM_DIV 1<<5
#define MM_SEL 1<<6
#define ADC_SEL_2 0<<7
#define ADC_SEL_4 1<<7
#define ADC_SEL_8 3<<7
#define ADC_SEL_16 7<<7
#define ADC_SEL_32 0x0f<<7
#define ADC_SEL_64 0x1f<<7
#define ADC_SEL_128 0x3f<<7
#define ALTD_SEL 1<<13

29
arch/arm/mach-l7200/include/mach/system.h
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/*
* arch/arm/mach-l7200/include/mach/system.h
*
* Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
*
* Changelog
* 03-21-2000 SJH Created
* 04-26-2000 SJH Fixed functions
* 05-03-2000 SJH Removed usage of obsolete 'iomd.h'
* 05-31-2000 SJH Properly implemented 'arch_idle'
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <mach/hardware.h>
static inline void arch_idle(void)
{
*(unsigned long *)(IO_BASE + 0x50004) = 1; /* idle mode */
}
static inline void arch_reset(char mode, const char *cmd)
{
if (mode == 's') {
cpu_reset(0);
}
}
#endif

73
arch/arm/mach-l7200/include/mach/time.h
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/*
* arch/arm/mach-l7200/include/mach/time.h
*
* Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
* Steve Hill (sjhill@cotw.com)
*
* Changelog:
* 01-02-2000 RS Created l7200 version, derived from rpc code
* 05-03-2000 SJH Complete rewrite
*/
#ifndef _ASM_ARCH_TIME_H
#define _ASM_ARCH_TIME_H
#include <mach/irqs.h>
/*
* RTC base register address
*/
#define RTC_BASE (IO_BASE_2 + 0x2000)
/*
* RTC registers
*/
#define RTC_RTCDR (*(volatile unsigned char *) (RTC_BASE + 0x000))
#define RTC_RTCMR (*(volatile unsigned char *) (RTC_BASE + 0x004))
#define RTC_RTCS (*(volatile unsigned char *) (RTC_BASE + 0x008))
#define RTC_RTCC (*(volatile unsigned char *) (RTC_BASE + 0x008))
#define RTC_RTCDV (*(volatile unsigned char *) (RTC_BASE + 0x00c))
#define RTC_RTCCR (*(volatile unsigned char *) (RTC_BASE + 0x010))
/*
* RTCCR register values
*/
#define RTC_RATE_32 0x00 /* 32 Hz tick */
#define RTC_RATE_64 0x10 /* 64 Hz tick */
#define RTC_RATE_128 0x20 /* 128 Hz tick */
#define RTC_RATE_256 0x30 /* 256 Hz tick */
#define RTC_EN_ALARM 0x01 /* Enable alarm */
#define RTC_EN_TIC 0x04 /* Enable counter */
#define RTC_EN_STWDOG 0x08 /* Enable watchdog */
/*
* Handler for RTC timer interrupt
*/
static irqreturn_t
timer_interrupt(int irq, void *dev_id)
{
struct pt_regs *regs = get_irq_regs();
do_timer(1);
#ifndef CONFIG_SMP
update_process_times(user_mode(regs));
#endif
do_profile(regs);
RTC_RTCC = 0; /* Clear interrupt */
return IRQ_HANDLED;
}
/*
* Set up RTC timer interrupt, and return the current time in seconds.
*/
void __init time_init(void)
{
RTC_RTCC = 0; /* Clear interrupt */
timer_irq.handler = timer_interrupt;
setup_irq(IRQ_RTC_TICK, &timer_irq);
RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC; /* Set rate and enable timer */
}
#endif

20
arch/arm/mach-l7200/include/mach/timex.h
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/*
* arch/arm/mach-l7200/include/mach/timex.h
*
* Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
* Steve Hill (sjhill@cotw.com)
*
* 04-21-2000 RS Created file
* 05-03-2000 SJH Tick rate was wrong
*
*/
/*
* On the ARM720T, clock ticks are set to 128 Hz.
*
* NOTE: The actual RTC value is set in 'time.h' which
* must be changed when choosing a different tick
* rate. The value of HZ in 'param.h' must also
* be changed to match below.
*/
#define CLOCK_TICK_RATE 128

39
arch/arm/mach-l7200/include/mach/uncompress.h
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/*
* arch/arm/mach-l7200/include/mach/uncompress.h
*
* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
*
* Changelog:
* 05-01-2000 SJH Created
* 05-13-2000 SJH Filled in function bodies
* 07-26-2000 SJH Removed hard coded baud rate
*/
#include <mach/hardware.h>
#define IO_UART IO_START + 0x00044000
#define __raw_writeb(v,p) (*(volatile unsigned char *)(p) = (v))
#define __raw_readb(p) (*(volatile unsigned char *)(p))
static inline void putc(int c)
{
while(__raw_readb(IO_UART + 0x18) & 0x20 ||
__raw_readb(IO_UART + 0x18) & 0x08)
barrier();
__raw_writeb(c, IO_UART + 0x00);
}
static inline void flush(void)
{
}
static __inline__ void arch_decomp_setup(void)
{
__raw_writeb(0x00, IO_UART + 0x08); /* Set HSB */
__raw_writeb(0x00, IO_UART + 0x20); /* Disable IRQs */
__raw_writeb(0x01, IO_UART + 0x14); /* Enable UART */
}
#define arch_decomp_wdog()

4
arch/arm/mach-l7200/include/mach/vmalloc.h
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/*
* arch/arm/mach-l7200/include/mach/vmalloc.h
*/
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)