forked from Minki/linux
qed: Add support for debug data collection
This patch adds the support for dumping and formatting the HW/FW debug data. Signed-off-by: Tomer Tayar <Tomer.Tayar@qlogic.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Tomer Tayar
David S. Miller
parent
936f0600de
commit
c965db4446
@ -2,5 +2,5 @@ obj-$(CONFIG_QED) := qed.o
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qed-y := qed_cxt.o qed_dev.o qed_hw.o qed_init_fw_funcs.o qed_init_ops.o \
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qed_int.o qed_main.o qed_mcp.o qed_sp_commands.o qed_spq.o qed_l2.o \
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qed_selftest.o qed_dcbx.o
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qed_selftest.o qed_dcbx.o qed_debug.o
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qed-$(CONFIG_QED_SRIOV) += qed_sriov.o qed_vf.o
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@ -23,6 +23,7 @@
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#include <linux/zlib.h>
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#include <linux/hashtable.h>
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#include <linux/qed/qed_if.h>
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#include "qed_debug.h"
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#include "qed_hsi.h"
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extern const struct qed_common_ops qed_common_ops_pass;
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@ -395,6 +396,8 @@ struct qed_hwfn {
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/* Buffer for unzipping firmware data */
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void *unzip_buf;
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struct dbg_tools_data dbg_info;
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struct qed_simd_fp_handler simd_proto_handler[64];
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#ifdef CONFIG_QED_SRIOV
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@ -430,6 +433,19 @@ struct qed_int_params {
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u8 fp_msix_cnt;
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};
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struct qed_dbg_feature {
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struct dentry *dentry;
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u8 *dump_buf;
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u32 buf_size;
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u32 dumped_dwords;
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};
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struct qed_dbg_params {
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struct qed_dbg_feature features[DBG_FEATURE_NUM];
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u8 engine_for_debug;
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bool print_data;
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};
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struct qed_dev {
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u32 dp_module;
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u8 dp_level;
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@ -444,6 +460,8 @@ struct qed_dev {
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CHIP_REV_IS_A0(dev))
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#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
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CHIP_REV_IS_B0(dev))
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#define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
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#define QED_IS_K2(dev) QED_IS_AH(dev)
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#define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
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QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
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@ -544,6 +562,8 @@ struct qed_dev {
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} protocol_ops;
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void *ops_cookie;
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struct qed_dbg_params dbg_params;
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const struct firmware *firmware;
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};
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6898
drivers/net/ethernet/qlogic/qed/qed_debug.c
Normal file
6898
drivers/net/ethernet/qlogic/qed/qed_debug.c
Normal file
File diff suppressed because it is too large
Load Diff
54
drivers/net/ethernet/qlogic/qed/qed_debug.h
Normal file
54
drivers/net/ethernet/qlogic/qed/qed_debug.h
Normal file
@ -0,0 +1,54 @@
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/* QLogic qed NIC Driver
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#ifndef _QED_DEBUGFS_H
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#define _QED_DEBUGFS_H
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enum qed_dbg_features {
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DBG_FEATURE_GRC,
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DBG_FEATURE_IDLE_CHK,
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DBG_FEATURE_MCP_TRACE,
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DBG_FEATURE_REG_FIFO,
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DBG_FEATURE_IGU_FIFO,
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DBG_FEATURE_PROTECTION_OVERRIDE,
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DBG_FEATURE_FW_ASSERTS,
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DBG_FEATURE_NUM
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};
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int qed_dbg_grc(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes);
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int qed_dbg_grc_size(struct qed_dev *cdev);
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int qed_dbg_idle_chk(struct qed_dev *cdev, void *buffer,
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u32 *num_dumped_bytes);
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int qed_dbg_idle_chk_size(struct qed_dev *cdev);
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int qed_dbg_reg_fifo(struct qed_dev *cdev, void *buffer,
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u32 *num_dumped_bytes);
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int qed_dbg_reg_fifo_size(struct qed_dev *cdev);
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int qed_dbg_igu_fifo(struct qed_dev *cdev, void *buffer,
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u32 *num_dumped_bytes);
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int qed_dbg_igu_fifo_size(struct qed_dev *cdev);
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int qed_dbg_protection_override(struct qed_dev *cdev, void *buffer,
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u32 *num_dumped_bytes);
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int qed_dbg_protection_override_size(struct qed_dev *cdev);
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int qed_dbg_fw_asserts(struct qed_dev *cdev, void *buffer,
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u32 *num_dumped_bytes);
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int qed_dbg_fw_asserts_size(struct qed_dev *cdev);
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int qed_dbg_mcp_trace(struct qed_dev *cdev, void *buffer,
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u32 *num_dumped_bytes);
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int qed_dbg_mcp_trace_size(struct qed_dev *cdev);
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int qed_dbg_all_data(struct qed_dev *cdev, void *buffer);
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int qed_dbg_all_data_size(struct qed_dev *cdev);
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u8 qed_get_debug_engine(struct qed_dev *cdev);
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void qed_set_debug_engine(struct qed_dev *cdev, int engine_number);
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int qed_dbg_feature(struct qed_dev *cdev, void *buffer,
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enum qed_dbg_features feature, u32 *num_dumped_bytes);
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int qed_dbg_feature_size(struct qed_dev *cdev, enum qed_dbg_features feature);
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void qed_dbg_pf_init(struct qed_dev *cdev);
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void qed_dbg_pf_exit(struct qed_dev *cdev);
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#endif
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File diff suppressed because it is too large
Load Diff
@ -588,6 +588,8 @@ static int qed_nic_stop(struct qed_dev *cdev)
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}
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}
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qed_dbg_pf_exit(cdev);
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return rc;
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}
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@ -846,6 +848,8 @@ static int qed_slowpath_start(struct qed_dev *cdev,
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/* First Dword used to diffrentiate between various sources */
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data = cdev->firmware->data + sizeof(u32);
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qed_dbg_pf_init(cdev);
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}
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memset(&tunn_info, 0, sizeof(tunn_info));
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@ -528,9 +528,903 @@
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#define QM_REG_WFQPFWEIGHT 0x2f4e80UL
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#define QM_REG_WFQVPWEIGHT 0x2fa000UL
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#define PGLCS_REG_DBG_SELECT \
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0x001d14UL
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#define PGLCS_REG_DBG_DWORD_ENABLE \
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0x001d18UL
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#define PGLCS_REG_DBG_SHIFT \
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0x001d1cUL
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#define PGLCS_REG_DBG_FORCE_VALID \
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0x001d20UL
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#define PGLCS_REG_DBG_FORCE_FRAME \
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0x001d24UL
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#define MISC_REG_RESET_PL_PDA_VMAIN_1 \
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0x008070UL
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#define MISC_REG_RESET_PL_PDA_VMAIN_2 \
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0x008080UL
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#define MISC_REG_RESET_PL_PDA_VAUX \
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0x008090UL
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#define MISCS_REG_RESET_PL_UA \
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0x009050UL
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#define MISCS_REG_RESET_PL_HV \
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0x009060UL
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#define MISCS_REG_RESET_PL_HV_2 \
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0x009150UL
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#define DMAE_REG_DBG_SELECT \
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0x00c510UL
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#define DMAE_REG_DBG_DWORD_ENABLE \
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0x00c514UL
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#define DMAE_REG_DBG_SHIFT \
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0x00c518UL
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#define DMAE_REG_DBG_FORCE_VALID \
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0x00c51cUL
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#define DMAE_REG_DBG_FORCE_FRAME \
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0x00c520UL
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#define NCSI_REG_DBG_SELECT \
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0x040474UL
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#define NCSI_REG_DBG_DWORD_ENABLE \
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0x040478UL
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#define NCSI_REG_DBG_SHIFT \
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0x04047cUL
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#define NCSI_REG_DBG_FORCE_VALID \
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0x040480UL
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#define NCSI_REG_DBG_FORCE_FRAME \
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0x040484UL
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#define GRC_REG_DBG_SELECT \
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0x0500a4UL
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#define GRC_REG_DBG_DWORD_ENABLE \
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0x0500a8UL
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#define GRC_REG_DBG_SHIFT \
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0x0500acUL
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#define GRC_REG_DBG_FORCE_VALID \
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0x0500b0UL
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#define GRC_REG_DBG_FORCE_FRAME \
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0x0500b4UL
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#define UMAC_REG_DBG_SELECT \
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0x051094UL
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#define UMAC_REG_DBG_DWORD_ENABLE \
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0x051098UL
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#define UMAC_REG_DBG_SHIFT \
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0x05109cUL
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#define UMAC_REG_DBG_FORCE_VALID \
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0x0510a0UL
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#define UMAC_REG_DBG_FORCE_FRAME \
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0x0510a4UL
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#define MCP2_REG_DBG_SELECT \
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0x052400UL
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#define MCP2_REG_DBG_DWORD_ENABLE \
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0x052404UL
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#define MCP2_REG_DBG_SHIFT \
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0x052408UL
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#define MCP2_REG_DBG_FORCE_VALID \
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0x052440UL
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#define MCP2_REG_DBG_FORCE_FRAME \
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0x052444UL
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#define PCIE_REG_DBG_SELECT \
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0x0547e8UL
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#define PCIE_REG_DBG_DWORD_ENABLE \
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0x0547ecUL
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#define PCIE_REG_DBG_SHIFT \
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0x0547f0UL
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#define PCIE_REG_DBG_FORCE_VALID \
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0x0547f4UL
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#define PCIE_REG_DBG_FORCE_FRAME \
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0x0547f8UL
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#define DORQ_REG_DBG_SELECT \
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0x100ad0UL
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#define DORQ_REG_DBG_DWORD_ENABLE \
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0x100ad4UL
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#define DORQ_REG_DBG_SHIFT \
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0x100ad8UL
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#define DORQ_REG_DBG_FORCE_VALID \
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0x100adcUL
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#define DORQ_REG_DBG_FORCE_FRAME \
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0x100ae0UL
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#define IGU_REG_DBG_SELECT \
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0x181578UL
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#define IGU_REG_DBG_DWORD_ENABLE \
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0x18157cUL
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#define IGU_REG_DBG_SHIFT \
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0x181580UL
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#define IGU_REG_DBG_FORCE_VALID \
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0x181584UL
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#define IGU_REG_DBG_FORCE_FRAME \
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0x181588UL
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#define CAU_REG_DBG_SELECT \
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0x1c0ea8UL
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#define CAU_REG_DBG_DWORD_ENABLE \
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0x1c0eacUL
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#define CAU_REG_DBG_SHIFT \
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0x1c0eb0UL
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#define CAU_REG_DBG_FORCE_VALID \
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0x1c0eb4UL
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#define CAU_REG_DBG_FORCE_FRAME \
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0x1c0eb8UL
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#define PRS_REG_DBG_SELECT \
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0x1f0b6cUL
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#define PRS_REG_DBG_DWORD_ENABLE \
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0x1f0b70UL
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#define PRS_REG_DBG_SHIFT \
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0x1f0b74UL
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#define PRS_REG_DBG_FORCE_VALID \
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0x1f0ba0UL
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#define PRS_REG_DBG_FORCE_FRAME \
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0x1f0ba4UL
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#define CNIG_REG_DBG_SELECT_K2 \
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0x218254UL
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#define CNIG_REG_DBG_DWORD_ENABLE_K2 \
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0x218258UL
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#define CNIG_REG_DBG_SHIFT_K2 \
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0x21825cUL
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#define CNIG_REG_DBG_FORCE_VALID_K2 \
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0x218260UL
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#define CNIG_REG_DBG_FORCE_FRAME_K2 \
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0x218264UL
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#define PRM_REG_DBG_SELECT \
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0x2306a8UL
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#define PRM_REG_DBG_DWORD_ENABLE \
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0x2306acUL
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#define PRM_REG_DBG_SHIFT \
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0x2306b0UL
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#define PRM_REG_DBG_FORCE_VALID \
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0x2306b4UL
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#define PRM_REG_DBG_FORCE_FRAME \
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0x2306b8UL
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#define SRC_REG_DBG_SELECT \
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0x238700UL
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#define SRC_REG_DBG_DWORD_ENABLE \
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0x238704UL
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#define SRC_REG_DBG_SHIFT \
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0x238708UL
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#define SRC_REG_DBG_FORCE_VALID \
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0x23870cUL
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#define SRC_REG_DBG_FORCE_FRAME \
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0x238710UL
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#define RSS_REG_DBG_SELECT \
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0x238c4cUL
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#define RSS_REG_DBG_DWORD_ENABLE \
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0x238c50UL
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#define RSS_REG_DBG_SHIFT \
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0x238c54UL
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#define RSS_REG_DBG_FORCE_VALID \
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0x238c58UL
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#define RSS_REG_DBG_FORCE_FRAME \
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0x238c5cUL
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#define RPB_REG_DBG_SELECT \
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0x23c728UL
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#define RPB_REG_DBG_DWORD_ENABLE \
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0x23c72cUL
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#define RPB_REG_DBG_SHIFT \
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0x23c730UL
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#define RPB_REG_DBG_FORCE_VALID \
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0x23c734UL
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#define RPB_REG_DBG_FORCE_FRAME \
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0x23c738UL
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#define PSWRQ2_REG_DBG_SELECT \
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0x240100UL
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#define PSWRQ2_REG_DBG_DWORD_ENABLE \
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0x240104UL
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#define PSWRQ2_REG_DBG_SHIFT \
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0x240108UL
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#define PSWRQ2_REG_DBG_FORCE_VALID \
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0x24010cUL
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#define PSWRQ2_REG_DBG_FORCE_FRAME \
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0x240110UL
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#define PSWRQ_REG_DBG_SELECT \
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0x280020UL
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#define PSWRQ_REG_DBG_DWORD_ENABLE \
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0x280024UL
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#define PSWRQ_REG_DBG_SHIFT \
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0x280028UL
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#define PSWRQ_REG_DBG_FORCE_VALID \
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0x28002cUL
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#define PSWRQ_REG_DBG_FORCE_FRAME \
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0x280030UL
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#define PSWWR_REG_DBG_SELECT \
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0x29a084UL
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#define PSWWR_REG_DBG_DWORD_ENABLE \
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0x29a088UL
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#define PSWWR_REG_DBG_SHIFT \
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0x29a08cUL
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#define PSWWR_REG_DBG_FORCE_VALID \
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0x29a090UL
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#define PSWWR_REG_DBG_FORCE_FRAME \
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0x29a094UL
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#define PSWRD_REG_DBG_SELECT \
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0x29c040UL
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#define PSWRD_REG_DBG_DWORD_ENABLE \
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0x29c044UL
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#define PSWRD_REG_DBG_SHIFT \
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0x29c048UL
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#define PSWRD_REG_DBG_FORCE_VALID \
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0x29c04cUL
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#define PSWRD_REG_DBG_FORCE_FRAME \
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0x29c050UL
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#define PSWRD2_REG_DBG_SELECT \
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0x29d400UL
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#define PSWRD2_REG_DBG_DWORD_ENABLE \
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0x29d404UL
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#define PSWRD2_REG_DBG_SHIFT \
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0x29d408UL
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#define PSWRD2_REG_DBG_FORCE_VALID \
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0x29d40cUL
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#define PSWRD2_REG_DBG_FORCE_FRAME \
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0x29d410UL
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#define PSWHST2_REG_DBG_SELECT \
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0x29e058UL
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#define PSWHST2_REG_DBG_DWORD_ENABLE \
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0x29e05cUL
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#define PSWHST2_REG_DBG_SHIFT \
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0x29e060UL
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#define PSWHST2_REG_DBG_FORCE_VALID \
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0x29e064UL
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#define PSWHST2_REG_DBG_FORCE_FRAME \
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0x29e068UL
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#define PSWHST_REG_DBG_SELECT \
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0x2a0100UL
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#define PSWHST_REG_DBG_DWORD_ENABLE \
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0x2a0104UL
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#define PSWHST_REG_DBG_SHIFT \
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0x2a0108UL
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#define PSWHST_REG_DBG_FORCE_VALID \
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0x2a010cUL
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#define PSWHST_REG_DBG_FORCE_FRAME \
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0x2a0110UL
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#define PGLUE_B_REG_DBG_SELECT \
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0x2a8400UL
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#define PGLUE_B_REG_DBG_DWORD_ENABLE \
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0x2a8404UL
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#define PGLUE_B_REG_DBG_SHIFT \
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0x2a8408UL
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#define PGLUE_B_REG_DBG_FORCE_VALID \
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0x2a840cUL
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#define PGLUE_B_REG_DBG_FORCE_FRAME \
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0x2a8410UL
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#define TM_REG_DBG_SELECT \
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0x2c07a8UL
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#define TM_REG_DBG_DWORD_ENABLE \
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0x2c07acUL
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#define TM_REG_DBG_SHIFT \
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0x2c07b0UL
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#define TM_REG_DBG_FORCE_VALID \
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0x2c07b4UL
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#define TM_REG_DBG_FORCE_FRAME \
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0x2c07b8UL
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#define TCFC_REG_DBG_SELECT \
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0x2d0500UL
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#define TCFC_REG_DBG_DWORD_ENABLE \
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0x2d0504UL
|
||||
#define TCFC_REG_DBG_SHIFT \
|
||||
0x2d0508UL
|
||||
#define TCFC_REG_DBG_FORCE_VALID \
|
||||
0x2d050cUL
|
||||
#define TCFC_REG_DBG_FORCE_FRAME \
|
||||
0x2d0510UL
|
||||
#define CCFC_REG_DBG_SELECT \
|
||||
0x2e0500UL
|
||||
#define CCFC_REG_DBG_DWORD_ENABLE \
|
||||
0x2e0504UL
|
||||
#define CCFC_REG_DBG_SHIFT \
|
||||
0x2e0508UL
|
||||
#define CCFC_REG_DBG_FORCE_VALID \
|
||||
0x2e050cUL
|
||||
#define CCFC_REG_DBG_FORCE_FRAME \
|
||||
0x2e0510UL
|
||||
#define QM_REG_DBG_SELECT \
|
||||
0x2f2e74UL
|
||||
#define QM_REG_DBG_DWORD_ENABLE \
|
||||
0x2f2e78UL
|
||||
#define QM_REG_DBG_SHIFT \
|
||||
0x2f2e7cUL
|
||||
#define QM_REG_DBG_FORCE_VALID \
|
||||
0x2f2e80UL
|
||||
#define QM_REG_DBG_FORCE_FRAME \
|
||||
0x2f2e84UL
|
||||
#define RDIF_REG_DBG_SELECT \
|
||||
0x300500UL
|
||||
#define RDIF_REG_DBG_DWORD_ENABLE \
|
||||
0x300504UL
|
||||
#define RDIF_REG_DBG_SHIFT \
|
||||
0x300508UL
|
||||
#define RDIF_REG_DBG_FORCE_VALID \
|
||||
0x30050cUL
|
||||
#define RDIF_REG_DBG_FORCE_FRAME \
|
||||
0x300510UL
|
||||
#define TDIF_REG_DBG_SELECT \
|
||||
0x310500UL
|
||||
#define TDIF_REG_DBG_DWORD_ENABLE \
|
||||
0x310504UL
|
||||
#define TDIF_REG_DBG_SHIFT \
|
||||
0x310508UL
|
||||
#define TDIF_REG_DBG_FORCE_VALID \
|
||||
0x31050cUL
|
||||
#define TDIF_REG_DBG_FORCE_FRAME \
|
||||
0x310510UL
|
||||
#define BRB_REG_DBG_SELECT \
|
||||
0x340ed0UL
|
||||
#define BRB_REG_DBG_DWORD_ENABLE \
|
||||
0x340ed4UL
|
||||
#define BRB_REG_DBG_SHIFT \
|
||||
0x340ed8UL
|
||||
#define BRB_REG_DBG_FORCE_VALID \
|
||||
0x340edcUL
|
||||
#define BRB_REG_DBG_FORCE_FRAME \
|
||||
0x340ee0UL
|
||||
#define XYLD_REG_DBG_SELECT \
|
||||
0x4c1600UL
|
||||
#define XYLD_REG_DBG_DWORD_ENABLE \
|
||||
0x4c1604UL
|
||||
#define XYLD_REG_DBG_SHIFT \
|
||||
0x4c1608UL
|
||||
#define XYLD_REG_DBG_FORCE_VALID \
|
||||
0x4c160cUL
|
||||
#define XYLD_REG_DBG_FORCE_FRAME \
|
||||
0x4c1610UL
|
||||
#define YULD_REG_DBG_SELECT \
|
||||
0x4c9600UL
|
||||
#define YULD_REG_DBG_DWORD_ENABLE \
|
||||
0x4c9604UL
|
||||
#define YULD_REG_DBG_SHIFT \
|
||||
0x4c9608UL
|
||||
#define YULD_REG_DBG_FORCE_VALID \
|
||||
0x4c960cUL
|
||||
#define YULD_REG_DBG_FORCE_FRAME \
|
||||
0x4c9610UL
|
||||
#define TMLD_REG_DBG_SELECT \
|
||||
0x4d1600UL
|
||||
#define TMLD_REG_DBG_DWORD_ENABLE \
|
||||
0x4d1604UL
|
||||
#define TMLD_REG_DBG_SHIFT \
|
||||
0x4d1608UL
|
||||
#define TMLD_REG_DBG_FORCE_VALID \
|
||||
0x4d160cUL
|
||||
#define TMLD_REG_DBG_FORCE_FRAME \
|
||||
0x4d1610UL
|
||||
#define MULD_REG_DBG_SELECT \
|
||||
0x4e1600UL
|
||||
#define MULD_REG_DBG_DWORD_ENABLE \
|
||||
0x4e1604UL
|
||||
#define MULD_REG_DBG_SHIFT \
|
||||
0x4e1608UL
|
||||
#define MULD_REG_DBG_FORCE_VALID \
|
||||
0x4e160cUL
|
||||
#define MULD_REG_DBG_FORCE_FRAME \
|
||||
0x4e1610UL
|
||||
#define NIG_REG_DBG_SELECT \
|
||||
0x502140UL
|
||||
#define NIG_REG_DBG_DWORD_ENABLE \
|
||||
0x502144UL
|
||||
#define NIG_REG_DBG_SHIFT \
|
||||
0x502148UL
|
||||
#define NIG_REG_DBG_FORCE_VALID \
|
||||
0x50214cUL
|
||||
#define NIG_REG_DBG_FORCE_FRAME \
|
||||
0x502150UL
|
||||
#define BMB_REG_DBG_SELECT \
|
||||
0x540a7cUL
|
||||
#define BMB_REG_DBG_DWORD_ENABLE \
|
||||
0x540a80UL
|
||||
#define BMB_REG_DBG_SHIFT \
|
||||
0x540a84UL
|
||||
#define BMB_REG_DBG_FORCE_VALID \
|
||||
0x540a88UL
|
||||
#define BMB_REG_DBG_FORCE_FRAME \
|
||||
0x540a8cUL
|
||||
#define PTU_REG_DBG_SELECT \
|
||||
0x560100UL
|
||||
#define PTU_REG_DBG_DWORD_ENABLE \
|
||||
0x560104UL
|
||||
#define PTU_REG_DBG_SHIFT \
|
||||
0x560108UL
|
||||
#define PTU_REG_DBG_FORCE_VALID \
|
||||
0x56010cUL
|
||||
#define PTU_REG_DBG_FORCE_FRAME \
|
||||
0x560110UL
|
||||
#define CDU_REG_DBG_SELECT \
|
||||
0x580704UL
|
||||
#define CDU_REG_DBG_DWORD_ENABLE \
|
||||
0x580708UL
|
||||
#define CDU_REG_DBG_SHIFT \
|
||||
0x58070cUL
|
||||
#define CDU_REG_DBG_FORCE_VALID \
|
||||
0x580710UL
|
||||
#define CDU_REG_DBG_FORCE_FRAME \
|
||||
0x580714UL
|
||||
#define WOL_REG_DBG_SELECT \
|
||||
0x600140UL
|
||||
#define WOL_REG_DBG_DWORD_ENABLE \
|
||||
0x600144UL
|
||||
#define WOL_REG_DBG_SHIFT \
|
||||
0x600148UL
|
||||
#define WOL_REG_DBG_FORCE_VALID \
|
||||
0x60014cUL
|
||||
#define WOL_REG_DBG_FORCE_FRAME \
|
||||
0x600150UL
|
||||
#define BMBN_REG_DBG_SELECT \
|
||||
0x610140UL
|
||||
#define BMBN_REG_DBG_DWORD_ENABLE \
|
||||
0x610144UL
|
||||
#define BMBN_REG_DBG_SHIFT \
|
||||
0x610148UL
|
||||
#define BMBN_REG_DBG_FORCE_VALID \
|
||||
0x61014cUL
|
||||
#define BMBN_REG_DBG_FORCE_FRAME \
|
||||
0x610150UL
|
||||
#define NWM_REG_DBG_SELECT \
|
||||
0x8000ecUL
|
||||
#define NWM_REG_DBG_DWORD_ENABLE \
|
||||
0x8000f0UL
|
||||
#define NWM_REG_DBG_SHIFT \
|
||||
0x8000f4UL
|
||||
#define NWM_REG_DBG_FORCE_VALID \
|
||||
0x8000f8UL
|
||||
#define NWM_REG_DBG_FORCE_FRAME \
|
||||
0x8000fcUL
|
||||
#define PBF_REG_DBG_SELECT \
|
||||
0xd80060UL
|
||||
#define PBF_REG_DBG_DWORD_ENABLE \
|
||||
0xd80064UL
|
||||
#define PBF_REG_DBG_SHIFT \
|
||||
0xd80068UL
|
||||
#define PBF_REG_DBG_FORCE_VALID \
|
||||
0xd8006cUL
|
||||
#define PBF_REG_DBG_FORCE_FRAME \
|
||||
0xd80070UL
|
||||
#define PBF_PB1_REG_DBG_SELECT \
|
||||
0xda0728UL
|
||||
#define PBF_PB1_REG_DBG_DWORD_ENABLE \
|
||||
0xda072cUL
|
||||
#define PBF_PB1_REG_DBG_SHIFT \
|
||||
0xda0730UL
|
||||
#define PBF_PB1_REG_DBG_FORCE_VALID \
|
||||
0xda0734UL
|
||||
#define PBF_PB1_REG_DBG_FORCE_FRAME \
|
||||
0xda0738UL
|
||||
#define PBF_PB2_REG_DBG_SELECT \
|
||||
0xda4728UL
|
||||
#define PBF_PB2_REG_DBG_DWORD_ENABLE \
|
||||
0xda472cUL
|
||||
#define PBF_PB2_REG_DBG_SHIFT \
|
||||
0xda4730UL
|
||||
#define PBF_PB2_REG_DBG_FORCE_VALID \
|
||||
0xda4734UL
|
||||
#define PBF_PB2_REG_DBG_FORCE_FRAME \
|
||||
0xda4738UL
|
||||
#define BTB_REG_DBG_SELECT \
|
||||
0xdb08c8UL
|
||||
#define BTB_REG_DBG_DWORD_ENABLE \
|
||||
0xdb08ccUL
|
||||
#define BTB_REG_DBG_SHIFT \
|
||||
0xdb08d0UL
|
||||
#define BTB_REG_DBG_FORCE_VALID \
|
||||
0xdb08d4UL
|
||||
#define BTB_REG_DBG_FORCE_FRAME \
|
||||
0xdb08d8UL
|
||||
#define XSDM_REG_DBG_SELECT \
|
||||
0xf80e28UL
|
||||
#define XSDM_REG_DBG_DWORD_ENABLE \
|
||||
0xf80e2cUL
|
||||
#define XSDM_REG_DBG_SHIFT \
|
||||
0xf80e30UL
|
||||
#define XSDM_REG_DBG_FORCE_VALID \
|
||||
0xf80e34UL
|
||||
#define XSDM_REG_DBG_FORCE_FRAME \
|
||||
0xf80e38UL
|
||||
#define YSDM_REG_DBG_SELECT \
|
||||
0xf90e28UL
|
||||
#define YSDM_REG_DBG_DWORD_ENABLE \
|
||||
0xf90e2cUL
|
||||
#define YSDM_REG_DBG_SHIFT \
|
||||
0xf90e30UL
|
||||
#define YSDM_REG_DBG_FORCE_VALID \
|
||||
0xf90e34UL
|
||||
#define YSDM_REG_DBG_FORCE_FRAME \
|
||||
0xf90e38UL
|
||||
#define PSDM_REG_DBG_SELECT \
|
||||
0xfa0e28UL
|
||||
#define PSDM_REG_DBG_DWORD_ENABLE \
|
||||
0xfa0e2cUL
|
||||
#define PSDM_REG_DBG_SHIFT \
|
||||
0xfa0e30UL
|
||||
#define PSDM_REG_DBG_FORCE_VALID \
|
||||
0xfa0e34UL
|
||||
#define PSDM_REG_DBG_FORCE_FRAME \
|
||||
0xfa0e38UL
|
||||
#define TSDM_REG_DBG_SELECT \
|
||||
0xfb0e28UL
|
||||
#define TSDM_REG_DBG_DWORD_ENABLE \
|
||||
0xfb0e2cUL
|
||||
#define TSDM_REG_DBG_SHIFT \
|
||||
0xfb0e30UL
|
||||
#define TSDM_REG_DBG_FORCE_VALID \
|
||||
0xfb0e34UL
|
||||
#define TSDM_REG_DBG_FORCE_FRAME \
|
||||
0xfb0e38UL
|
||||
#define MSDM_REG_DBG_SELECT \
|
||||
0xfc0e28UL
|
||||
#define MSDM_REG_DBG_DWORD_ENABLE \
|
||||
0xfc0e2cUL
|
||||
#define MSDM_REG_DBG_SHIFT \
|
||||
0xfc0e30UL
|
||||
#define MSDM_REG_DBG_FORCE_VALID \
|
||||
0xfc0e34UL
|
||||
#define MSDM_REG_DBG_FORCE_FRAME \
|
||||
0xfc0e38UL
|
||||
#define USDM_REG_DBG_SELECT \
|
||||
0xfd0e28UL
|
||||
#define USDM_REG_DBG_DWORD_ENABLE \
|
||||
0xfd0e2cUL
|
||||
#define USDM_REG_DBG_SHIFT \
|
||||
0xfd0e30UL
|
||||
#define USDM_REG_DBG_FORCE_VALID \
|
||||
0xfd0e34UL
|
||||
#define USDM_REG_DBG_FORCE_FRAME \
|
||||
0xfd0e38UL
|
||||
#define XCM_REG_DBG_SELECT \
|
||||
0x1000040UL
|
||||
#define XCM_REG_DBG_DWORD_ENABLE \
|
||||
0x1000044UL
|
||||
#define XCM_REG_DBG_SHIFT \
|
||||
0x1000048UL
|
||||
#define XCM_REG_DBG_FORCE_VALID \
|
||||
0x100004cUL
|
||||
#define XCM_REG_DBG_FORCE_FRAME \
|
||||
0x1000050UL
|
||||
#define YCM_REG_DBG_SELECT \
|
||||
0x1080040UL
|
||||
#define YCM_REG_DBG_DWORD_ENABLE \
|
||||
0x1080044UL
|
||||
#define YCM_REG_DBG_SHIFT \
|
||||
0x1080048UL
|
||||
#define YCM_REG_DBG_FORCE_VALID \
|
||||
0x108004cUL
|
||||
#define YCM_REG_DBG_FORCE_FRAME \
|
||||
0x1080050UL
|
||||
#define PCM_REG_DBG_SELECT \
|
||||
0x1100040UL
|
||||
#define PCM_REG_DBG_DWORD_ENABLE \
|
||||
0x1100044UL
|
||||
#define PCM_REG_DBG_SHIFT \
|
||||
0x1100048UL
|
||||
#define PCM_REG_DBG_FORCE_VALID \
|
||||
0x110004cUL
|
||||
#define PCM_REG_DBG_FORCE_FRAME \
|
||||
0x1100050UL
|
||||
#define TCM_REG_DBG_SELECT \
|
||||
0x1180040UL
|
||||
#define TCM_REG_DBG_DWORD_ENABLE \
|
||||
0x1180044UL
|
||||
#define TCM_REG_DBG_SHIFT \
|
||||
0x1180048UL
|
||||
#define TCM_REG_DBG_FORCE_VALID \
|
||||
0x118004cUL
|
||||
#define TCM_REG_DBG_FORCE_FRAME \
|
||||
0x1180050UL
|
||||
#define MCM_REG_DBG_SELECT \
|
||||
0x1200040UL
|
||||
#define MCM_REG_DBG_DWORD_ENABLE \
|
||||
0x1200044UL
|
||||
#define MCM_REG_DBG_SHIFT \
|
||||
0x1200048UL
|
||||
#define MCM_REG_DBG_FORCE_VALID \
|
||||
0x120004cUL
|
||||
#define MCM_REG_DBG_FORCE_FRAME \
|
||||
0x1200050UL
|
||||
#define UCM_REG_DBG_SELECT \
|
||||
0x1280050UL
|
||||
#define UCM_REG_DBG_DWORD_ENABLE \
|
||||
0x1280054UL
|
||||
#define UCM_REG_DBG_SHIFT \
|
||||
0x1280058UL
|
||||
#define UCM_REG_DBG_FORCE_VALID \
|
||||
0x128005cUL
|
||||
#define UCM_REG_DBG_FORCE_FRAME \
|
||||
0x1280060UL
|
||||
#define XSEM_REG_DBG_SELECT \
|
||||
0x1401528UL
|
||||
#define XSEM_REG_DBG_DWORD_ENABLE \
|
||||
0x140152cUL
|
||||
#define XSEM_REG_DBG_SHIFT \
|
||||
0x1401530UL
|
||||
#define XSEM_REG_DBG_FORCE_VALID \
|
||||
0x1401534UL
|
||||
#define XSEM_REG_DBG_FORCE_FRAME \
|
||||
0x1401538UL
|
||||
#define YSEM_REG_DBG_SELECT \
|
||||
0x1501528UL
|
||||
#define YSEM_REG_DBG_DWORD_ENABLE \
|
||||
0x150152cUL
|
||||
#define YSEM_REG_DBG_SHIFT \
|
||||
0x1501530UL
|
||||
#define YSEM_REG_DBG_FORCE_VALID \
|
||||
0x1501534UL
|
||||
#define YSEM_REG_DBG_FORCE_FRAME \
|
||||
0x1501538UL
|
||||
#define PSEM_REG_DBG_SELECT \
|
||||
0x1601528UL
|
||||
#define PSEM_REG_DBG_DWORD_ENABLE \
|
||||
0x160152cUL
|
||||
#define PSEM_REG_DBG_SHIFT \
|
||||
0x1601530UL
|
||||
#define PSEM_REG_DBG_FORCE_VALID \
|
||||
0x1601534UL
|
||||
#define PSEM_REG_DBG_FORCE_FRAME \
|
||||
0x1601538UL
|
||||
#define TSEM_REG_DBG_SELECT \
|
||||
0x1701528UL
|
||||
#define TSEM_REG_DBG_DWORD_ENABLE \
|
||||
0x170152cUL
|
||||
#define TSEM_REG_DBG_SHIFT \
|
||||
0x1701530UL
|
||||
#define TSEM_REG_DBG_FORCE_VALID \
|
||||
0x1701534UL
|
||||
#define TSEM_REG_DBG_FORCE_FRAME \
|
||||
0x1701538UL
|
||||
#define MSEM_REG_DBG_SELECT \
|
||||
0x1801528UL
|
||||
#define MSEM_REG_DBG_DWORD_ENABLE \
|
||||
0x180152cUL
|
||||
#define MSEM_REG_DBG_SHIFT \
|
||||
0x1801530UL
|
||||
#define MSEM_REG_DBG_FORCE_VALID \
|
||||
0x1801534UL
|
||||
#define MSEM_REG_DBG_FORCE_FRAME \
|
||||
0x1801538UL
|
||||
#define USEM_REG_DBG_SELECT \
|
||||
0x1901528UL
|
||||
#define USEM_REG_DBG_DWORD_ENABLE \
|
||||
0x190152cUL
|
||||
#define USEM_REG_DBG_SHIFT \
|
||||
0x1901530UL
|
||||
#define USEM_REG_DBG_FORCE_VALID \
|
||||
0x1901534UL
|
||||
#define USEM_REG_DBG_FORCE_FRAME \
|
||||
0x1901538UL
|
||||
#define PCIE_REG_DBG_COMMON_SELECT \
|
||||
0x054398UL
|
||||
#define PCIE_REG_DBG_COMMON_DWORD_ENABLE \
|
||||
0x05439cUL
|
||||
#define PCIE_REG_DBG_COMMON_SHIFT \
|
||||
0x0543a0UL
|
||||
#define PCIE_REG_DBG_COMMON_FORCE_VALID \
|
||||
0x0543a4UL
|
||||
#define PCIE_REG_DBG_COMMON_FORCE_FRAME \
|
||||
0x0543a8UL
|
||||
#define MISC_REG_RESET_PL_UA \
|
||||
0x008050UL
|
||||
#define MISC_REG_RESET_PL_HV \
|
||||
0x008060UL
|
||||
#define XCM_REG_CTX_RBC_ACCS \
|
||||
0x1001800UL
|
||||
#define XCM_REG_AGG_CON_CTX \
|
||||
0x1001804UL
|
||||
#define XCM_REG_SM_CON_CTX \
|
||||
0x1001808UL
|
||||
#define YCM_REG_CTX_RBC_ACCS \
|
||||
0x1081800UL
|
||||
#define YCM_REG_AGG_CON_CTX \
|
||||
0x1081804UL
|
||||
#define YCM_REG_AGG_TASK_CTX \
|
||||
0x1081808UL
|
||||
#define YCM_REG_SM_CON_CTX \
|
||||
0x108180cUL
|
||||
#define YCM_REG_SM_TASK_CTX \
|
||||
0x1081810UL
|
||||
#define PCM_REG_CTX_RBC_ACCS \
|
||||
0x1101440UL
|
||||
#define PCM_REG_SM_CON_CTX \
|
||||
0x1101444UL
|
||||
#define TCM_REG_CTX_RBC_ACCS \
|
||||
0x11814c0UL
|
||||
#define TCM_REG_AGG_CON_CTX \
|
||||
0x11814c4UL
|
||||
#define TCM_REG_AGG_TASK_CTX \
|
||||
0x11814c8UL
|
||||
#define TCM_REG_SM_CON_CTX \
|
||||
0x11814ccUL
|
||||
#define TCM_REG_SM_TASK_CTX \
|
||||
0x11814d0UL
|
||||
#define MCM_REG_CTX_RBC_ACCS \
|
||||
0x1201800UL
|
||||
#define MCM_REG_AGG_CON_CTX \
|
||||
0x1201804UL
|
||||
#define MCM_REG_AGG_TASK_CTX \
|
||||
0x1201808UL
|
||||
#define MCM_REG_SM_CON_CTX \
|
||||
0x120180cUL
|
||||
#define MCM_REG_SM_TASK_CTX \
|
||||
0x1201810UL
|
||||
#define UCM_REG_CTX_RBC_ACCS \
|
||||
0x1281700UL
|
||||
#define UCM_REG_AGG_CON_CTX \
|
||||
0x1281704UL
|
||||
#define UCM_REG_AGG_TASK_CTX \
|
||||
0x1281708UL
|
||||
#define UCM_REG_SM_CON_CTX \
|
||||
0x128170cUL
|
||||
#define UCM_REG_SM_TASK_CTX \
|
||||
0x1281710UL
|
||||
#define XSEM_REG_SLOW_DBG_EMPTY \
|
||||
0x1401140UL
|
||||
#define XSEM_REG_SYNC_DBG_EMPTY \
|
||||
0x1401160UL
|
||||
#define XSEM_REG_SLOW_DBG_ACTIVE \
|
||||
0x1401400UL
|
||||
#define XSEM_REG_SLOW_DBG_MODE \
|
||||
0x1401404UL
|
||||
#define XSEM_REG_DBG_FRAME_MODE \
|
||||
0x1401408UL
|
||||
#define XSEM_REG_DBG_MODE1_CFG \
|
||||
0x1401420UL
|
||||
#define XSEM_REG_FAST_MEMORY \
|
||||
0x1440000UL
|
||||
#define YSEM_REG_SYNC_DBG_EMPTY \
|
||||
0x1501160UL
|
||||
#define YSEM_REG_SLOW_DBG_ACTIVE \
|
||||
0x1501400UL
|
||||
#define YSEM_REG_SLOW_DBG_MODE \
|
||||
0x1501404UL
|
||||
#define YSEM_REG_DBG_FRAME_MODE \
|
||||
0x1501408UL
|
||||
#define YSEM_REG_DBG_MODE1_CFG \
|
||||
0x1501420UL
|
||||
#define YSEM_REG_FAST_MEMORY \
|
||||
0x1540000UL
|
||||
#define PSEM_REG_SLOW_DBG_EMPTY \
|
||||
0x1601140UL
|
||||
#define PSEM_REG_SYNC_DBG_EMPTY \
|
||||
0x1601160UL
|
||||
#define PSEM_REG_SLOW_DBG_ACTIVE \
|
||||
0x1601400UL
|
||||
#define PSEM_REG_SLOW_DBG_MODE \
|
||||
0x1601404UL
|
||||
#define PSEM_REG_DBG_FRAME_MODE \
|
||||
0x1601408UL
|
||||
#define PSEM_REG_DBG_MODE1_CFG \
|
||||
0x1601420UL
|
||||
#define PSEM_REG_FAST_MEMORY \
|
||||
0x1640000UL
|
||||
#define TSEM_REG_SLOW_DBG_EMPTY \
|
||||
0x1701140UL
|
||||
#define TSEM_REG_SYNC_DBG_EMPTY \
|
||||
0x1701160UL
|
||||
#define TSEM_REG_SLOW_DBG_ACTIVE \
|
||||
0x1701400UL
|
||||
#define TSEM_REG_SLOW_DBG_MODE \
|
||||
0x1701404UL
|
||||
#define TSEM_REG_DBG_FRAME_MODE \
|
||||
0x1701408UL
|
||||
#define TSEM_REG_DBG_MODE1_CFG \
|
||||
0x1701420UL
|
||||
#define TSEM_REG_FAST_MEMORY \
|
||||
0x1740000UL
|
||||
#define MSEM_REG_SLOW_DBG_EMPTY \
|
||||
0x1801140UL
|
||||
#define MSEM_REG_SYNC_DBG_EMPTY \
|
||||
0x1801160UL
|
||||
#define MSEM_REG_SLOW_DBG_ACTIVE \
|
||||
0x1801400UL
|
||||
#define MSEM_REG_SLOW_DBG_MODE \
|
||||
0x1801404UL
|
||||
#define MSEM_REG_DBG_FRAME_MODE \
|
||||
0x1801408UL
|
||||
#define MSEM_REG_DBG_MODE1_CFG \
|
||||
0x1801420UL
|
||||
#define MSEM_REG_FAST_MEMORY \
|
||||
0x1840000UL
|
||||
#define USEM_REG_SLOW_DBG_EMPTY \
|
||||
0x1901140UL
|
||||
#define USEM_REG_SYNC_DBG_EMPTY \
|
||||
0x1901160UL
|
||||
#define USEM_REG_SLOW_DBG_ACTIVE \
|
||||
0x1901400UL
|
||||
#define USEM_REG_SLOW_DBG_MODE \
|
||||
0x1901404UL
|
||||
#define USEM_REG_DBG_FRAME_MODE \
|
||||
0x1901408UL
|
||||
#define USEM_REG_DBG_MODE1_CFG \
|
||||
0x1901420UL
|
||||
#define USEM_REG_FAST_MEMORY \
|
||||
0x1940000UL
|
||||
#define SEM_FAST_REG_INT_RAM \
|
||||
0x020000UL
|
||||
#define SEM_FAST_REG_INT_RAM_SIZE \
|
||||
20480
|
||||
#define GRC_REG_TRACE_FIFO_VALID_DATA \
|
||||
0x050064UL
|
||||
#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \
|
||||
0x05040cUL
|
||||
#define GRC_REG_PROTECTION_OVERRIDE_WINDOW \
|
||||
0x050500UL
|
||||
#define IGU_REG_ERROR_HANDLING_MEMORY \
|
||||
0x181520UL
|
||||
#define MCP_REG_CPU_MODE \
|
||||
0xe05000UL
|
||||
#define MCP_REG_CPU_MODE_SOFT_HALT \
|
||||
(0x1 << 10)
|
||||
#define BRB_REG_BIG_RAM_ADDRESS \
|
||||
0x340800UL
|
||||
#define BRB_REG_BIG_RAM_DATA \
|
||||
0x341500UL
|
||||
#define SEM_FAST_REG_STALL_0 \
|
||||
0x000488UL
|
||||
#define SEM_FAST_REG_STALLED \
|
||||
0x000494UL
|
||||
#define BTB_REG_BIG_RAM_ADDRESS \
|
||||
0xdb0800UL
|
||||
#define BTB_REG_BIG_RAM_DATA \
|
||||
0xdb0c00UL
|
||||
#define BMB_REG_BIG_RAM_ADDRESS \
|
||||
0x540800UL
|
||||
#define BMB_REG_BIG_RAM_DATA \
|
||||
0x540f00UL
|
||||
#define SEM_FAST_REG_STORM_REG_FILE \
|
||||
0x008000UL
|
||||
#define RSS_REG_RSS_RAM_ADDR \
|
||||
0x238c30UL
|
||||
#define MISCS_REG_BLOCK_256B_EN \
|
||||
0x009074UL
|
||||
#define MCP_REG_SCRATCH_SIZE \
|
||||
57344
|
||||
#define MCP_REG_CPU_REG_FILE \
|
||||
0xe05200UL
|
||||
#define MCP_REG_CPU_REG_FILE_SIZE \
|
||||
32
|
||||
#define DBG_REG_DEBUG_TARGET \
|
||||
0x01005cUL
|
||||
#define DBG_REG_FULL_MODE \
|
||||
0x010060UL
|
||||
#define DBG_REG_CALENDAR_OUT_DATA \
|
||||
0x010480UL
|
||||
#define GRC_REG_TRACE_FIFO \
|
||||
0x050068UL
|
||||
#define IGU_REG_ERROR_HANDLING_DATA_VALID \
|
||||
0x181530UL
|
||||
#define DBG_REG_DBG_BLOCK_ON \
|
||||
0x010454UL
|
||||
#define DBG_REG_FRAMING_MODE \
|
||||
0x010058UL
|
||||
#define SEM_FAST_REG_VFC_DATA_WR \
|
||||
0x000b40UL
|
||||
#define SEM_FAST_REG_VFC_ADDR \
|
||||
0x000b44UL
|
||||
#define SEM_FAST_REG_VFC_DATA_RD \
|
||||
0x000b48UL
|
||||
#define RSS_REG_RSS_RAM_DATA \
|
||||
0x238c20UL
|
||||
#define MISC_REG_BLOCK_256B_EN \
|
||||
0x008c14UL
|
||||
#define NWS_REG_NWS_CMU \
|
||||
0x720000UL
|
||||
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0 \
|
||||
0x000680UL
|
||||
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8 \
|
||||
0x000684UL
|
||||
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0 \
|
||||
0x0006c0UL
|
||||
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8 \
|
||||
0x0006c4UL
|
||||
#define MS_REG_MS_CMU \
|
||||
0x6a4000UL
|
||||
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130 \
|
||||
0x000208UL
|
||||
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132 \
|
||||
0x000210UL
|
||||
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131 \
|
||||
0x00020cUL
|
||||
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133 \
|
||||
0x000214UL
|
||||
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130 \
|
||||
0x000208UL
|
||||
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131 \
|
||||
0x00020cUL
|
||||
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132 \
|
||||
0x000210UL
|
||||
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133 \
|
||||
0x000214UL
|
||||
#define PHY_PCIE_REG_PHY0 \
|
||||
0x620000UL
|
||||
#define PHY_PCIE_REG_PHY1 \
|
||||
0x624000UL
|
||||
|
||||
#endif
|
||||
|
||||
@ -143,6 +143,9 @@
|
||||
#define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2)
|
||||
#define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS)
|
||||
|
||||
/* Tools Version */
|
||||
#define TOOLS_VERSION 10
|
||||
|
||||
/*****************/
|
||||
/* CDU CONSTANTS */
|
||||
/*****************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user