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drm/sun4i: Add support for second clock parent to DW HDMI PHY clk driver

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Expand HDMI PHY clock driver to support second clock parent.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-20-jernej.skrabec@siol.net
This commit is contained in:
Jernej Skrabec 2018-06-25 14:02:59 +02:00 committed by Maxime Ripard
parent aef13fd842
commit c891a65a7f
No known key found for this signature in database
GPG Key ID: D2B4C094214DAF74
3 changed files with 72 additions and 23 deletions
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4
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
View File

@ -99,6 +99,7 @@
#define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN BIT(28) #define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN BIT(28)
#define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 BIT(27) #define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 BIT(27)
#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26) #define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26)
#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT 26
#define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN BIT(25) #define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN BIT(25)
#define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x) ((x) << 22) #define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x) ((x) << 22)
#define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x) ((x) << 20) #define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x) ((x) << 20)
@ -190,6 +191,7 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi);
void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy); void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void); const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);
int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev); int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
bool second_parent);
#endif /* _SUN8I_DW_HDMI_H_ */ #endif /* _SUN8I_DW_HDMI_H_ */

3
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
View File

@ -491,7 +491,8 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
} }
} }
ret = sun8i_phy_clk_create(phy, dev); ret = sun8i_phy_clk_create(phy, dev,
phy->variant->has_second_pll);
if (ret) { if (ret) {
dev_err(dev, "Couldn't create the PHY clock\n"); dev_err(dev, "Couldn't create the PHY clock\n");
goto err_put_clk_pll1; goto err_put_clk_pll1;

88
drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c
View File

@ -22,35 +22,45 @@ static int sun8i_phy_clk_determine_rate(struct clk_hw *hw,
{ {
unsigned long rate = req->rate; unsigned long rate = req->rate;
unsigned long best_rate = 0; unsigned long best_rate = 0;
struct clk_hw *best_parent = NULL;
struct clk_hw *parent; struct clk_hw *parent;
int best_div = 1; int best_div = 1;
int i; int i, p;
parent = clk_hw_get_parent(hw); for (p = 0; p < clk_hw_get_num_parents(hw); p++) {
parent = clk_hw_get_parent_by_index(hw, p);
if (!parent)
continue;
for (i = 1; i <= 16; i++) { for (i = 1; i <= 16; i++) {
unsigned long ideal = rate * i; unsigned long ideal = rate * i;
unsigned long rounded; unsigned long rounded;
rounded = clk_hw_round_rate(parent, ideal); rounded = clk_hw_round_rate(parent, ideal);
if (rounded == ideal) { if (rounded == ideal) {
best_rate = rounded; best_rate = rounded;
best_div = i; best_div = i;
best_parent = parent;
break;
}
if (!best_rate ||
abs(rate - rounded / i) <
abs(rate - best_rate / best_div)) {
best_rate = rounded;
best_div = i;
best_parent = parent;
}
}
if (best_rate / best_div == rate)
break; break;
}
if (!best_rate ||
abs(rate - rounded / i) <
abs(rate - best_rate / best_div)) {
best_rate = rounded;
best_div = i;
}
} }
req->rate = best_rate / best_div; req->rate = best_rate / best_div;
req->best_parent_rate = best_rate; req->best_parent_rate = best_rate;
req->best_parent_hw = parent; req->best_parent_hw = best_parent;
return 0; return 0;
} }
@ -95,22 +105,58 @@ static int sun8i_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
return 0; return 0;
} }
static u8 sun8i_phy_clk_get_parent(struct clk_hw *hw)
{
struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
u32 reg;
regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, &reg);
reg = (reg & SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK) >>
SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT;
return reg;
}
static int sun8i_phy_clk_set_parent(struct clk_hw *hw, u8 index)
{
struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
if (index > 1)
return -EINVAL;
regmap_update_bits(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
index << SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT);
return 0;
}
static const struct clk_ops sun8i_phy_clk_ops = { static const struct clk_ops sun8i_phy_clk_ops = {
.determine_rate = sun8i_phy_clk_determine_rate, .determine_rate = sun8i_phy_clk_determine_rate,
.recalc_rate = sun8i_phy_clk_recalc_rate, .recalc_rate = sun8i_phy_clk_recalc_rate,
.set_rate = sun8i_phy_clk_set_rate, .set_rate = sun8i_phy_clk_set_rate,
.get_parent = sun8i_phy_clk_get_parent,
.set_parent = sun8i_phy_clk_set_parent,
}; };
int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev) int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
bool second_parent)
{ {
struct clk_init_data init; struct clk_init_data init;
struct sun8i_phy_clk *priv; struct sun8i_phy_clk *priv;
const char *parents[1]; const char *parents[2];
parents[0] = __clk_get_name(phy->clk_pll0); parents[0] = __clk_get_name(phy->clk_pll0);
if (!parents[0]) if (!parents[0])
return -ENODEV; return -ENODEV;
if (second_parent) {
parents[1] = __clk_get_name(phy->clk_pll1);
if (!parents[1])
return -ENODEV;
}
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv) if (!priv)
return -ENOMEM; return -ENOMEM;
@ -118,7 +164,7 @@ int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev)
init.name = "hdmi-phy-clk"; init.name = "hdmi-phy-clk";
init.ops = &sun8i_phy_clk_ops; init.ops = &sun8i_phy_clk_ops;
init.parent_names = parents; init.parent_names = parents;
init.num_parents = 1; init.num_parents = second_parent ? 2 : 1;
init.flags = CLK_SET_RATE_PARENT; init.flags = CLK_SET_RATE_PARENT;
priv->phy = phy; priv->phy = phy;