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ARM: S5PC1XX: Change clksrc_clks to use array of clocks

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Remove the individual 'struct clksrc_clks' and place them into an array
so that we can simply use s3c_register_clksrcs to register tham all in one
go.

Since the spdif clock relies on the audio clock, move the audio clocks
into their own arrary.

Thanks to  Marek Szyprowski for testing and pointing out the four clocks
what where missed from the clock list.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Ben Dooks 2010-01-12 12:49:17 +09:00
parent 1d026d9b16
commit c837e88cf9
1 changed files with 178 additions and 236 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

414
arch/arm/plat-s5pc1xx/s5pc100-clock.c
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@ -534,14 +534,44 @@ static struct clksrc_sources clkset_audio2 = {
.nr_sources = ARRAY_SIZE(clkset_audio2_list), .nr_sources = ARRAY_SIZE(clkset_audio2_list),
}; };
static struct clksrc_clk clk_audio0; static struct clksrc_clk clksrc_audio[] = {
static struct clksrc_clk clk_audio1; {
static struct clksrc_clk clk_audio2; .clk = {
.name = "audio-bus",
.id = 0,
.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
.enable = s5pc100_sclk1_ctrl,
},
.sources = &clkset_audio0,
.reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, },
.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, },
}, {
.clk = {
.name = "audio-bus",
.id = 1,
.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
.enable = s5pc100_sclk1_ctrl,
},
.sources = &clkset_audio1,
.reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, },
.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, },
}, {
.clk = {
.name = "audio-bus",
.id = 2,
.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
.enable = s5pc100_sclk1_ctrl,
},
.sources = &clkset_audio2,
.reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, },
.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, },
},
};
static struct clk *clkset_spdif_list[] = { static struct clk *clkset_spdif_list[] = {
&clk_audio0.clk, &clksrc_audio[0].clk,
&clk_audio1.clk, &clksrc_audio[1].clk,
&clk_audio2.clk, &clksrc_audio[2].clk,
}; };
static struct clksrc_sources clkset_spdif = { static struct clksrc_sources clkset_spdif = {
@ -585,195 +615,136 @@ static struct clksrc_sources clkset_usbhost = {
.nr_sources = ARRAY_SIZE(clkset_usbhost_list), .nr_sources = ARRAY_SIZE(clkset_usbhost_list),
}; };
static struct clksrc_clk clk_spi0 = { static struct clksrc_clk clksrc_clks[] = {
.clk = { {
.name = "spi_bus", .clk = {
.id = 0, .name = "spi_bus",
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, .id = 0,
.enable = s5pc100_sclk0_ctrl, .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
.enable = s5pc100_sclk0_ctrl,
}, },
.sources = &clkset_spi, .sources = &clkset_spi,
.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, }, .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, },
.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, }, .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, },
}; }, {
.clk = {
static struct clksrc_clk clk_spi1 = { .name = "spi_bus",
.clk = { .id = 1,
.name = "spi_bus", .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
.id = 1, .enable = s5pc100_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, },
.enable = s5pc100_sclk0_ctrl, .sources = &clkset_spi,
}, .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, },
.sources = &clkset_spi, .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, },
.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, }, }, {
.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, }, .clk = {
}; .name = "spi_bus",
.id = 2,
static struct clksrc_clk clk_spi2 = { .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
.clk = { .enable = s5pc100_sclk0_ctrl,
.name = "spi_bus", },
.id = 2, .sources = &clkset_spi,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, },
.enable = s5pc100_sclk0_ctrl, .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, },
}, }, {
.sources = &clkset_spi, .clk = {
.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, }, .name = "uclk1",
.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, }, .id = -1,
}; .ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
.enable = s5pc100_sclk0_ctrl,
static struct clksrc_clk clk_uart_uclk1 = { },
.clk = { .sources = &clkset_uart,
.name = "uclk1", .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, },
.id = -1, .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, },
.ctrlbit = S5PC100_CLKGATE_SCLK0_UART, }, {
.enable = s5pc100_sclk0_ctrl, .clk = {
}, .name = "spdif",
.sources = &clkset_uart, .id = -1,
.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, }, },
.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, }, .sources = &clkset_spdif,
}; .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, },
}, {
static struct clksrc_clk clk_audio0 = { .clk = {
.clk = { .name = "lcd",
.name = "audio-bus", .id = -1,
.id = 0, .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, .enable = s5pc100_sclk1_ctrl,
.enable = s5pc100_sclk1_ctrl, },
}, .sources = &clkset_lcd_fimc,
.sources = &clkset_audio0, .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, },
.reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, }, .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, },
.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, }, }, {
}; .clk = {
.name = "fimc",
static struct clksrc_clk clk_audio1 = { .id = 0,
.clk = { .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
.name = "audio-bus", .enable = s5pc100_sclk1_ctrl,
.id = 1, },
.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, .sources = &clkset_lcd_fimc,
.enable = s5pc100_sclk1_ctrl, .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, },
}, .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, },
.sources = &clkset_audio1, }, {
.reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, }, .clk = {
.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, }, .name = "fimc",
}; .id = 1,
.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
.enable = s5pc100_sclk1_ctrl,
static struct clksrc_clk clk_audio2 = { },
.clk = { .sources = &clkset_lcd_fimc,
.name = "audio-bus", .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, },
.id = 2, .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, },
.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, }, {
.enable = s5pc100_sclk1_ctrl, .clk = {
}, .name = "fimc",
.sources = &clkset_audio2, .id = 2,
.reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, }, .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, }, .enable = s5pc100_sclk1_ctrl,
}; },
.sources = &clkset_lcd_fimc,
static struct clksrc_clk clk_spdif = { .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, },
.clk = { .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, },
.name = "spdif", }, {
.id = -1, .clk = {
}, .name = "mmc_bus",
.sources = &clkset_spdif, .id = 0,
.reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, }, .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
}; .enable = s5pc100_sclk0_ctrl,
},
static struct clksrc_clk clk_lcd = { .sources = &clkset_mmc,
.clk = { .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, },
.name = "lcd", .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, },
.id = -1, }, {
.ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, .clk = {
.enable = s5pc100_sclk1_ctrl, .name = "mmc_bus",
}, .id = 1,
.sources = &clkset_lcd_fimc, .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, }, .enable = s5pc100_sclk0_ctrl,
.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, }, },
}; .sources = &clkset_mmc,
.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, },
static struct clksrc_clk clk_fimc0 = { .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, },
.clk = { }, {
.name = "fimc", .clk = {
.id = 0, .name = "mmc_bus",
.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, .id = 2,
.enable = s5pc100_sclk1_ctrl, .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
}, .enable = s5pc100_sclk0_ctrl,
.sources = &clkset_lcd_fimc, },
.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, }, .sources = &clkset_mmc,
.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, }, .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, },
}; .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, },
}, {
static struct clksrc_clk clk_fimc1 = { .clk = {
.clk = { .name = "usbhost",
.name = "fimc", .id = -1,
.id = 1, .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, .enable = s5pc100_sclk0_ctrl,
.enable = s5pc100_sclk1_ctrl, },
}, .sources = &clkset_usbhost,
.sources = &clkset_lcd_fimc, .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, },
.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, }, .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, },
.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, }, }
};
static struct clksrc_clk clk_fimc2 = {
.clk = {
.name = "fimc",
.id = 2,
.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
.enable = s5pc100_sclk1_ctrl,
},
.sources = &clkset_lcd_fimc,
.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, },
.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, },
};
static struct clksrc_clk clk_mmc0 = {
.clk = {
.name = "mmc_bus",
.id = 0,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
.enable = s5pc100_sclk0_ctrl,
},
.sources = &clkset_mmc,
.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, },
.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, },
};
static struct clksrc_clk clk_mmc1 = {
.clk = {
.name = "mmc_bus",
.id = 1,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
.enable = s5pc100_sclk0_ctrl,
},
.sources = &clkset_mmc,
.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, },
.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, },
};
static struct clksrc_clk clk_mmc2 = {
.clk = {
.name = "mmc_bus",
.id = 2,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
.enable = s5pc100_sclk0_ctrl,
},
.sources = &clkset_mmc,
.reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, },
.reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, },
};
static struct clksrc_clk clk_usbhost = {
.clk = {
.name = "usbhost",
.id = -1,
.ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
.enable = s5pc100_sclk0_ctrl,
},
.sources = &clkset_usbhost,
.reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, },
.reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, },
}; };
/* Clock initialisation code */ /* Clock initialisation code */
@ -785,22 +756,6 @@ static struct clksrc_clk *init_parents[] = {
&clk_mout_onenand, &clk_mout_onenand,
&clk_mout_epll, &clk_mout_epll,
&clk_mout_hpll, &clk_mout_hpll,
&clk_spi0,
&clk_spi1,
&clk_spi2,
&clk_uart_uclk1,
&clk_audio0,
&clk_audio1,
&clk_audio2,
&clk_spdif,
&clk_lcd,
&clk_fimc0,
&clk_fimc1,
&clk_fimc2,
&clk_mmc0,
&clk_mmc1,
&clk_mmc2,
&clk_usbhost,
}; };
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@ -867,6 +822,12 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s3c_set_clksrc(init_parents[ptr], true); s3c_set_clksrc(init_parents[ptr], true);
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++)
s3c_set_clksrc(clksrc_audio + ptr, true);
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
s3c_set_clksrc(clksrc_clks + ptr, true);
} }
static struct clk *clks[] __initdata = { static struct clk *clks[] __initdata = {
@ -875,8 +836,13 @@ static struct clk *clks[] __initdata = {
&clk_dout_d0_bus, &clk_dout_d0_bus,
&clk_dout_pclkd0, &clk_dout_pclkd0,
&clk_dout_apll2, &clk_dout_apll2,
&clk_mout_apll.clk,
&clk_mout_mpll.clk,
&clk_mout_epll.clk,
&clk_mout_hpll.clk,
&clk_mout_am.clk, &clk_mout_am.clk,
&clk_dout_d1_bus, &clk_dout_d1_bus,
&clk_mout_onenand.clk,
&clk_dout_pclkd1, &clk_dout_pclkd1,
&clk_dout_mpll2, &clk_dout_mpll2,
&clk_dout_cam, &clk_dout_cam,
@ -890,30 +856,6 @@ static struct clk *clks[] __initdata = {
&clk_arm, &clk_arm,
}; };
/* simplest change - will aggregate clocks later */
static struct clksrc_clk *clks_src[] = {
&clk_mout_apll,
&clk_mout_mpll,
&clk_mout_onenand,
&clk_mout_epll,
&clk_spi0,
&clk_spi1,
&clk_spi2,
&clk_uart_uclk1,
&clk_audio0,
&clk_audio1,
&clk_audio2,
&clk_spdif,
&clk_lcd,
&clk_fimc0,
&clk_fimc1,
&clk_fimc2,
&clk_mmc0,
&clk_mmc1,
&clk_mmc2,
&clk_usbhost,
};
void __init s5pc100_register_clocks(void) void __init s5pc100_register_clocks(void)
{ {
struct clk *clkp; struct clk *clkp;
@ -929,6 +871,6 @@ void __init s5pc100_register_clocks(void)
} }
} }
for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++) s3c_register_clksrc(clksrc_audio, ARRAY_SIZE(clksrc_audio));
s3c_register_clksrc(clks_src[ptr], 1); s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
} }