Merge branches 'fixes-for-linus', 'generic', 'cavium', 'module.h-fixes', 'next/ath79' and 'next/lantiq' into mips-for-linux-next
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@@ -15,6 +15,7 @@
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#include <linux/compiler.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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@@ -91,7 +92,7 @@ void (*board_nmi_handler_setup)(void);
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void (*board_ejtag_handler_setup)(void);
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void (*board_bind_eic_interrupt)(int irq, int regset);
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void (*board_ebase_setup)(void);
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void __cpuinitdata(*board_cache_error_setup)(void);
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static void show_raw_backtrace(unsigned long reg29)
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{
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@@ -1490,7 +1491,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
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return set_vi_srs_handler(n, addr, 0);
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}
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extern void cpu_cache_init(void);
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extern void tlb_init(void);
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extern void flush_tlb_handlers(void);
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@@ -1517,7 +1517,7 @@ static int __init ulri_disable(char *s)
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}
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__setup("noulri", ulri_disable);
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void __cpuinit per_cpu_trap_init(void)
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void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
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{
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unsigned int cpu = smp_processor_id();
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unsigned int status_set = ST0_CU0;
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@@ -1616,7 +1616,9 @@ void __cpuinit per_cpu_trap_init(void)
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#ifdef CONFIG_MIPS_MT_SMTC
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if (bootTC) {
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#endif /* CONFIG_MIPS_MT_SMTC */
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cpu_cache_init();
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/* Boot CPU's cache setup in setup_arch(). */
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if (!is_boot_cpu)
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cpu_cache_init();
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tlb_init();
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#ifdef CONFIG_MIPS_MT_SMTC
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} else if (!secondaryTC) {
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@@ -1632,7 +1634,7 @@ void __cpuinit per_cpu_trap_init(void)
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}
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/* Install CPU exception handler */
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void __init set_handler(unsigned long offset, void *addr, unsigned long size)
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void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size)
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{
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memcpy((void *)(ebase + offset), addr, size);
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local_flush_icache_range(ebase + offset, ebase + offset + size);
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@@ -1693,7 +1695,7 @@ void __init trap_init(void)
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if (board_ebase_setup)
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board_ebase_setup();
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per_cpu_trap_init();
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per_cpu_trap_init(true);
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/*
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* Copy the generic exception handlers to their final destination.
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@@ -1797,6 +1799,9 @@ void __init trap_init(void)
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set_except_vector(26, handle_dsp);
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if (board_cache_error_setup)
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board_cache_error_setup();
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if (cpu_has_vce)
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/* Special exception: R4[04]00 uses also the divec space. */
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memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
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