forked from Minki/linux
Fix/Rewrite of the mipsnet driver]
This is Thiemo's patch. ----- Forwarded message from Thiemo Seufer <ths@networkno.de> ----- From: Thiemo Seufer <ths@networkno.de> Date: Sat, 17 Nov 2007 22:29:13 +0000 To: netdev@vger.kernel.org Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH, REPOST] Fix/Rewrite of the mipsnet driver Content-Type: text/plain; charset=us-ascii Hello All, currently the mipsnet driver fails after transmitting a number of packages because SKBs are allocated but never freed. I fixed that and coudn't refrain from removing the most egregious warts. - mipsnet.h folded into mipsnet.c, as it doesn't provide any useful external interface. - Free SKB after transmission. - Call free_irq in mipsnet_close, to balance the request_irq in mipsnet_open. - Removed duplicate read of rxDataCount. - Some identifiers are now less verbose. - Removed dead and/or unnecessarily complex code. - Code formatting fixes. Tested on Qemu's mipssim emulation, with this patch it can boot a Debian NFSroot. Thiemo Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ralf Baechle
David S. Miller
parent
ba64f58ea4
commit
c800c5c9db
@ -4,8 +4,6 @@
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* for more details.
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*/
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#define DEBUG
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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@ -15,11 +13,93 @@
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#include <linux/platform_device.h>
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#include <asm/mips-boards/simint.h>
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#include "mipsnet.h" /* actual device IO mapping */
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#define MIPSNET_VERSION "2007-11-17"
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#define MIPSNET_VERSION "2005-06-20"
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/*
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* Net status/control block as seen by sw in the core.
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*/
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struct mipsnet_regs {
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/*
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* Device info for probing, reads as MIPSNET%d where %d is some
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* form of version.
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*/
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u64 devId; /*0x00 */
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#define mipsnet_reg_address(dev, field) (dev->base_addr + field_offset(field))
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/*
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* read only busy flag.
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* Set and cleared by the Net Device to indicate that an rx or a tx
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* is in progress.
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*/
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u32 busy; /*0x08 */
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/*
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* Set by the Net Device.
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* The device will set it once data has been received.
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* The value is the number of bytes that should be read from
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* rxDataBuffer. The value will decrease till 0 until all the data
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* from rxDataBuffer has been read.
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*/
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u32 rxDataCount; /*0x0c */
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#define MIPSNET_MAX_RXTX_DATACOUNT (1 << 16)
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/*
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* Settable from the MIPS core, cleared by the Net Device.
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* The core should set the number of bytes it wants to send,
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* then it should write those bytes of data to txDataBuffer.
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* The device will clear txDataCount has been processed (not
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* necessarily sent).
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*/
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u32 txDataCount; /*0x10 */
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/*
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* Interrupt control
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*
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* Used to clear the interrupted generated by this dev.
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* Write a 1 to clear the interrupt. (except bit31).
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*
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* Bit0 is set if it was a tx-done interrupt.
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* Bit1 is set when new rx-data is available.
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* Until this bit is cleared there will be no other RXs.
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*
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* Bit31 is used for testing, it clears after a read.
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* Writing 1 to this bit will cause an interrupt to be generated.
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* To clear the test interrupt, write 0 to this register.
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*/
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u32 interruptControl; /*0x14 */
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#define MIPSNET_INTCTL_TXDONE (1u << 0)
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#define MIPSNET_INTCTL_RXDONE (1u << 1)
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#define MIPSNET_INTCTL_TESTBIT (1u << 31)
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/*
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* Readonly core-specific interrupt info for the device to signal
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* the core. The meaning of the contents of this field might change.
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*/
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/* XXX: the whole memIntf interrupt scheme is messy: the device
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* should have no control what so ever of what VPE/register set is
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* being used.
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* The MemIntf should only expose interrupt lines, and something in
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* the config should be responsible for the line<->core/vpe bindings.
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*/
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u32 interruptInfo; /*0x18 */
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/*
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* This is where the received data is read out.
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* There is more data to read until rxDataReady is 0.
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* Only 1 byte at this regs offset is used.
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*/
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u32 rxDataBuffer; /*0x1c */
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/*
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* This is where the data to transmit is written.
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* Data should be written for the amount specified in the
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* txDataCount register.
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* Only 1 byte at this regs offset is used.
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*/
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u32 txDataBuffer; /*0x20 */
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};
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#define regaddr(dev, field) \
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(dev->base_addr + offsetof(struct mipsnet_regs, field))
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static char mipsnet_string[] = "mipsnet";
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@ -29,32 +109,27 @@ static char mipsnet_string[] = "mipsnet";
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static int ioiocpy_frommipsnet(struct net_device *dev, unsigned char *kdata,
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int len)
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{
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uint32_t available_len = inl(mipsnet_reg_address(dev, rxDataCount));
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if (available_len < len)
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return -EFAULT;
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for (; len > 0; len--, kdata++)
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*kdata = inb(mipsnet_reg_address(dev, rxDataBuffer));
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*kdata = inb(regaddr(dev, rxDataBuffer));
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return inl(mipsnet_reg_address(dev, rxDataCount));
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return inl(regaddr(dev, rxDataCount));
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}
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static inline ssize_t mipsnet_put_todevice(struct net_device *dev,
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static inline void mipsnet_put_todevice(struct net_device *dev,
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struct sk_buff *skb)
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{
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int count_to_go = skb->len;
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char *buf_ptr = skb->data;
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outl(skb->len, mipsnet_reg_address(dev, txDataCount));
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outl(skb->len, regaddr(dev, txDataCount));
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for (; count_to_go; buf_ptr++, count_to_go--)
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outb(*buf_ptr, mipsnet_reg_address(dev, txDataBuffer));
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outb(*buf_ptr, regaddr(dev, txDataBuffer));
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dev->stats.tx_packets++;
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dev->stats.tx_bytes += skb->len;
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return skb->len;
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dev_kfree_skb(skb);
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}
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static int mipsnet_xmit(struct sk_buff *skb, struct net_device *dev)
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@ -69,18 +144,20 @@ static int mipsnet_xmit(struct sk_buff *skb, struct net_device *dev)
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return 0;
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}
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static inline ssize_t mipsnet_get_fromdev(struct net_device *dev, size_t count)
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static inline ssize_t mipsnet_get_fromdev(struct net_device *dev, size_t len)
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{
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struct sk_buff *skb;
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size_t len = count;
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skb = alloc_skb(len + 2, GFP_KERNEL);
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if (!len)
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return len;
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skb = dev_alloc_skb(len + NET_IP_ALIGN);
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if (!skb) {
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dev->stats.rx_dropped++;
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return -ENOMEM;
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}
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skb_reserve(skb, 2);
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skb_reserve(skb, NET_IP_ALIGN);
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if (ioiocpy_frommipsnet(dev, skb_put(skb, len), len))
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return -EFAULT;
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@ -92,50 +169,42 @@ static inline ssize_t mipsnet_get_fromdev(struct net_device *dev, size_t count)
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dev->stats.rx_packets++;
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dev->stats.rx_bytes += len;
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return count;
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return len;
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}
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static irqreturn_t mipsnet_interrupt(int irq, void *dev_id)
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{
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struct net_device *dev = dev_id;
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u32 int_flags;
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irqreturn_t ret = IRQ_NONE;
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irqreturn_t retval = IRQ_NONE;
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uint64_t interruptFlags;
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if (irq != dev->irq)
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goto out_badirq;
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if (irq == dev->irq) {
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retval = IRQ_HANDLED;
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interruptFlags =
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inl(mipsnet_reg_address(dev, interruptControl));
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if (interruptFlags & MIPSNET_INTCTL_TXDONE) {
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outl(MIPSNET_INTCTL_TXDONE,
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mipsnet_reg_address(dev, interruptControl));
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/* only one packet at a time, we are done. */
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netif_wake_queue(dev);
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} else if (interruptFlags & MIPSNET_INTCTL_RXDONE) {
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mipsnet_get_fromdev(dev,
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inl(mipsnet_reg_address(dev, rxDataCount)));
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outl(MIPSNET_INTCTL_RXDONE,
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mipsnet_reg_address(dev, interruptControl));
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} else if (interruptFlags & MIPSNET_INTCTL_TESTBIT) {
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/*
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* TESTBIT is cleared on read.
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* And takes effect after a write with 0
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*/
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outl(0, mipsnet_reg_address(dev, interruptControl));
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} else {
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/* Maybe shared IRQ, just ignore, no clearing. */
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retval = IRQ_NONE;
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}
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} else {
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printk(KERN_INFO "%s: %s(): irq %d for unknown device\n",
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dev->name, __FUNCTION__, irq);
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retval = IRQ_NONE;
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/* TESTBIT is cleared on read. */
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int_flags = inl(regaddr(dev, interruptControl));
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if (int_flags & MIPSNET_INTCTL_TESTBIT) {
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/* TESTBIT takes effect after a write with 0. */
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outl(0, regaddr(dev, interruptControl));
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ret = IRQ_HANDLED;
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} else if (int_flags & MIPSNET_INTCTL_TXDONE) {
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/* Only one packet at a time, we are done. */
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dev->stats.tx_packets++;
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netif_wake_queue(dev);
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outl(MIPSNET_INTCTL_TXDONE,
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regaddr(dev, interruptControl));
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ret = IRQ_HANDLED;
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} else if (int_flags & MIPSNET_INTCTL_RXDONE) {
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mipsnet_get_fromdev(dev, inl(regaddr(dev, rxDataCount)));
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outl(MIPSNET_INTCTL_RXDONE, regaddr(dev, interruptControl));
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ret = IRQ_HANDLED;
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}
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return retval;
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return ret;
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out_badirq:
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printk(KERN_INFO "%s: %s(): irq %d for unknown device\n",
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dev->name, __FUNCTION__, irq);
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return ret;
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}
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static int mipsnet_open(struct net_device *dev)
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@ -144,18 +213,15 @@ static int mipsnet_open(struct net_device *dev)
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err = request_irq(dev->irq, &mipsnet_interrupt,
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IRQF_SHARED, dev->name, (void *) dev);
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if (err) {
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release_region(dev->base_addr, MIPSNET_IO_EXTENT);
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release_region(dev->base_addr, sizeof(struct mipsnet_regs));
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return err;
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}
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netif_start_queue(dev);
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/* test interrupt handler */
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outl(MIPSNET_INTCTL_TESTBIT,
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mipsnet_reg_address(dev, interruptControl));
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outl(MIPSNET_INTCTL_TESTBIT, regaddr(dev, interruptControl));
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return 0;
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}
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@ -163,7 +229,7 @@ static int mipsnet_open(struct net_device *dev)
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static int mipsnet_close(struct net_device *dev)
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{
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netif_stop_queue(dev);
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free_irq(dev->irq, dev);
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return 0;
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}
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@ -194,10 +260,11 @@ static int __init mipsnet_probe(struct device *dev)
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*/
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netdev->base_addr = 0x4200;
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netdev->irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB0 +
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inl(mipsnet_reg_address(netdev, interruptInfo));
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inl(regaddr(netdev, interruptInfo));
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/* Get the io region now, get irq on open() */
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if (!request_region(netdev->base_addr, MIPSNET_IO_EXTENT, "mipsnet")) {
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if (!request_region(netdev->base_addr, sizeof(struct mipsnet_regs),
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"mipsnet")) {
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err = -EBUSY;
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goto out_free_netdev;
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}
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@ -217,7 +284,7 @@ static int __init mipsnet_probe(struct device *dev)
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return 0;
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out_free_region:
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release_region(netdev->base_addr, MIPSNET_IO_EXTENT);
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release_region(netdev->base_addr, sizeof(struct mipsnet_regs));
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out_free_netdev:
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free_netdev(netdev);
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@ -231,7 +298,7 @@ static int __devexit mipsnet_device_remove(struct device *device)
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struct net_device *dev = dev_get_drvdata(device);
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unregister_netdev(dev);
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release_region(dev->base_addr, MIPSNET_IO_EXTENT);
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release_region(dev->base_addr, sizeof(struct mipsnet_regs));
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free_netdev(dev);
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dev_set_drvdata(device, NULL);
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@ -1,112 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __MIPSNET_H
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#define __MIPSNET_H
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/*
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* Id of this Net device, as seen by the core.
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*/
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#define MIPS_NET_DEV_ID ((uint64_t) \
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((uint64_t) 'M' << 0)| \
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((uint64_t) 'I' << 8)| \
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((uint64_t) 'P' << 16)| \
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((uint64_t) 'S' << 24)| \
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((uint64_t) 'N' << 32)| \
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((uint64_t) 'E' << 40)| \
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((uint64_t) 'T' << 48)| \
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((uint64_t) '0' << 56))
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/*
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* Net status/control block as seen by sw in the core.
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* (Why not use bit fields? can't be bothered with cross-platform struct
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* packing.)
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*/
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struct net_control_block {
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/*
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* dev info for probing
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* reads as MIPSNET%d where %d is some form of version
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*/
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uint64_t devId; /* 0x00 */
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/*
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* read only busy flag.
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* Set and cleared by the Net Device to indicate that an rx or a tx
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* is in progress.
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*/
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uint32_t busy; /* 0x08 */
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/*
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* Set by the Net Device.
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* The device will set it once data has been received.
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* The value is the number of bytes that should be read from
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* rxDataBuffer. The value will decrease till 0 until all the data
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* from rxDataBuffer has been read.
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*/
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uint32_t rxDataCount; /* 0x0c */
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#define MIPSNET_MAX_RXTX_DATACOUNT (1<<16)
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/*
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* Settable from the MIPS core, cleared by the Net Device. The core
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* should set the number of bytes it wants to send, then it should
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* write those bytes of data to txDataBuffer. The device will clear
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* txDataCount has been processed (not necessarily sent).
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*/
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uint32_t txDataCount; /* 0x10 */
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/*
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* Interrupt control
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*
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* Used to clear the interrupted generated by this dev.
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* Write a 1 to clear the interrupt. (except bit31).
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*
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* Bit0 is set if it was a tx-done interrupt.
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* Bit1 is set when new rx-data is available.
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* Until this bit is cleared there will be no other RXs.
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*
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* Bit31 is used for testing, it clears after a read.
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* Writing 1 to this bit will cause an interrupt to be generated.
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* To clear the test interrupt, write 0 to this register.
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*/
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uint32_t interruptControl; /*0x14 */
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#define MIPSNET_INTCTL_TXDONE ((uint32_t)(1 << 0))
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#define MIPSNET_INTCTL_RXDONE ((uint32_t)(1 << 1))
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#define MIPSNET_INTCTL_TESTBIT ((uint32_t)(1 << 31))
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#define MIPSNET_INTCTL_ALLSOURCES (MIPSNET_INTCTL_TXDONE | \
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MIPSNET_INTCTL_RXDONE | \
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MIPSNET_INTCTL_TESTBIT)
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/*
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* Readonly core-specific interrupt info for the device to signal the
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* core. The meaning of the contents of this field might change.
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*
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* TODO: the whole memIntf interrupt scheme is messy: the device should
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* have no control what so ever of what VPE/register set is being
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* used. The MemIntf should only expose interrupt lines, and
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* something in the config should be responsible for the
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* line<->core/vpe bindings.
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*/
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uint32_t interruptInfo; /* 0x18 */
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/*
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* This is where the received data is read out.
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* There is more data to read until rxDataReady is 0.
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* Only 1 byte at this regs offset is used.
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*/
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uint32_t rxDataBuffer; /* 0x1c */
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/*
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* This is where the data to transmit is written. Data should be
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* written for the amount specified in the txDataCount register. Only
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* 1 byte at this regs offset is used.
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*/
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uint32_t txDataBuffer; /* 0x20 */
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};
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#define MIPSNET_IO_EXTENT 0x40 /* being generous */
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#define field_offset(field) (offsetof(struct net_control_block, field))
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#endif /* __MIPSNET_H */
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