x86/bugs: Optimize SPEC_CTRL MSR writes
When changing SPEC_CTRL for user control, the WRMSR can be delayed until return-to-user when KERNEL_IBRS has been enabled. This avoids an MSR write during context switch. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
committed by
Borislav Petkov
parent
2dbb887e87
commit
c779bc1a90
@@ -253,7 +253,7 @@ static inline void indirect_branch_prediction_barrier(void)
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/* The Intel SPEC CTRL MSR base value cache */
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/* The Intel SPEC CTRL MSR base value cache */
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extern u64 x86_spec_ctrl_base;
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extern u64 x86_spec_ctrl_base;
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extern void write_spec_ctrl_current(u64 val);
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extern void write_spec_ctrl_current(u64 val, bool force);
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/*
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/*
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* With retpoline, we must use IBRS to restrict branch prediction
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* With retpoline, we must use IBRS to restrict branch prediction
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@@ -63,13 +63,19 @@ static DEFINE_MUTEX(spec_ctrl_mutex);
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* Keep track of the SPEC_CTRL MSR value for the current task, which may differ
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* Keep track of the SPEC_CTRL MSR value for the current task, which may differ
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* from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
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* from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
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*/
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*/
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void write_spec_ctrl_current(u64 val)
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void write_spec_ctrl_current(u64 val, bool force)
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{
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{
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if (this_cpu_read(x86_spec_ctrl_current) == val)
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if (this_cpu_read(x86_spec_ctrl_current) == val)
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return;
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return;
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this_cpu_write(x86_spec_ctrl_current, val);
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this_cpu_write(x86_spec_ctrl_current, val);
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wrmsrl(MSR_IA32_SPEC_CTRL, val);
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/*
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* When KERNEL_IBRS this MSR is written on return-to-user, unless
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* forced the update can be delayed until that time.
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*/
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if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
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wrmsrl(MSR_IA32_SPEC_CTRL, val);
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}
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}
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/*
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/*
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@@ -1297,7 +1303,7 @@ static void __init spectre_v2_select_mitigation(void)
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if (spectre_v2_in_eibrs_mode(mode)) {
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if (spectre_v2_in_eibrs_mode(mode)) {
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/* Force it so VMEXIT will restore correctly */
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/* Force it so VMEXIT will restore correctly */
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x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
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x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
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write_spec_ctrl_current(x86_spec_ctrl_base);
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write_spec_ctrl_current(x86_spec_ctrl_base, true);
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}
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}
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switch (mode) {
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switch (mode) {
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@@ -1352,7 +1358,7 @@ static void __init spectre_v2_select_mitigation(void)
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static void update_stibp_msr(void * __unused)
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static void update_stibp_msr(void * __unused)
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{
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{
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write_spec_ctrl_current(x86_spec_ctrl_base);
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write_spec_ctrl_current(x86_spec_ctrl_base, true);
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}
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}
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/* Update x86_spec_ctrl_base in case SMT state changed. */
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/* Update x86_spec_ctrl_base in case SMT state changed. */
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@@ -1595,7 +1601,7 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
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x86_amd_ssb_disable();
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x86_amd_ssb_disable();
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} else {
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} else {
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x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
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x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
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write_spec_ctrl_current(x86_spec_ctrl_base);
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write_spec_ctrl_current(x86_spec_ctrl_base, true);
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}
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}
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}
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}
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@@ -1846,7 +1852,7 @@ int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
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void x86_spec_ctrl_setup_ap(void)
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void x86_spec_ctrl_setup_ap(void)
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{
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{
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if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
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if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
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write_spec_ctrl_current(x86_spec_ctrl_base);
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write_spec_ctrl_current(x86_spec_ctrl_base, true);
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if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
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if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
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x86_amd_ssb_disable();
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x86_amd_ssb_disable();
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@@ -600,7 +600,7 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp,
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}
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}
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if (updmsr)
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if (updmsr)
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write_spec_ctrl_current(msr);
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write_spec_ctrl_current(msr, false);
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}
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}
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static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
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static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
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