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PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability

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Default root port setting hides AER capability. This patch enables the
advertisement of AER capability by root port.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Manikanta Maddireddy
2019-06-18 23:31:46 +05:30
committed by Lorenzo Pieralisi
parent 538123a29a
commit c635a815c8
1 changed files with 15 additions and 0 deletions
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15
drivers/pci/controller/pci-tegra.c
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@@ -180,6 +180,9 @@
#define RP_VEND_XP 0x00000f00 #define RP_VEND_XP 0x00000f00
#define RP_VEND_XP_DL_UP (1 << 30) #define RP_VEND_XP_DL_UP (1 << 30)
#define RP_VEND_CTL1 0x00000f48
#define RP_VEND_CTL1_ERPT (1 << 13)
#define RP_VEND_CTL2 0x00000fa8 #define RP_VEND_CTL2 0x00000fa8
#define RP_VEND_CTL2_PCA_ENABLE (1 << 7) #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
@@ -479,6 +482,16 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
afi_writel(port->pcie, value, ctrl); afi_writel(port->pcie, value, ctrl);
} }
static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
{
u32 value;
/* Enable AER capability */
value = readl(port->base + RP_VEND_CTL1);
value |= RP_VEND_CTL1_ERPT;
writel(value, port->base + RP_VEND_CTL1);
}
static void tegra_pcie_port_enable(struct tegra_pcie_port *port) static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
{ {
unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
@@ -503,6 +516,8 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
value |= RP_VEND_CTL2_PCA_ENABLE; value |= RP_VEND_CTL2_PCA_ENABLE;
writel(value, port->base + RP_VEND_CTL2); writel(value, port->base + RP_VEND_CTL2);
} }
tegra_pcie_enable_rp_features(port);
} }
static void tegra_pcie_port_disable(struct tegra_pcie_port *port) static void tegra_pcie_port_disable(struct tegra_pcie_port *port)