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x86, platforms: Remove SGI Visual Workstation

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The SGI Visual Workstation seems to be dead; remove support so we
don't have to continue maintaining it.

Cc: Andrey Panin <pazke@donpac.ru>
Cc: Michael Reed <mdr@sgi.com>
Link: http://lkml.kernel.org/r/530CFD6C.7040705@zytor.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
H. Peter Anvin 2014-02-25 12:05:34 -08:00
parent 7cf6c94591
commit c5f9ee3d66
33 changed files with 5 additions and 6454 deletions
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2
Documentation/00-INDEX
View File

@ -401,8 +401,6 @@ serial-console.txt
- how to set up Linux with a serial line console as the default.
sgi-ioc4.txt
- description of the SGI IOC4 PCI (multi function) device.
sgi-visws.txt
- short blurb on the SGI Visual Workstations.
sh/
- directory with info on porting Linux to a new architecture.
smsc_ece1099.txt

13
Documentation/sgi-visws.txt
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@ -1,13 +0,0 @@
The SGI Visual Workstations (models 320 and 540) are based around
the Cobalt, Lithium, and Arsenic ASICs. The Cobalt ASIC is the
main system ASIC which interfaces the 1-4 IA32 cpus, the memory
system, and the I/O system in the Lithium ASIC. The Cobalt ASIC
also contains the 3D gfx rendering engine which renders to main
system memory -- part of which is used as the frame buffer which
is DMA'ed to a video connector using the Arsenic ASIC. A PIIX4
chip and NS87307 are used to provide legacy device support (IDE,
serial, floppy, and parallel).
The Visual Workstation chipset largely conforms to the PC architecture
with some notable exceptions such as interrupt handling.

293
Documentation/sound/oss/vwsnd
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@ -1,293 +0,0 @@
vwsnd - Sound driver for the Silicon Graphics 320 and 540 Visual
Workstations' onboard audio.
Copyright 1999 Silicon Graphics, Inc. All rights reserved.
At the time of this writing, March 1999, there are two models of
Visual Workstation, the 320 and the 540. This document only describes
those models. Future Visual Workstation models may have different
sound capabilities, and this driver will probably not work on those
boxes.
The Visual Workstation has an Analog Devices AD1843 "SoundComm" audio
codec chip. The AD1843 is accessed through the Cobalt I/O ASIC, also
known as Lithium. This driver programs both chips.
==============================================================================
QUICK CONFIGURATION
# insmod soundcore
# insmod vwsnd
==============================================================================
I/O CONNECTIONS
On the Visual Workstation, only three of the AD1843 inputs are hooked
up. The analog line in jacks are connected to the AD1843's AUX1
input. The CD audio lines are connected to the AD1843's AUX2 input.
The microphone jack is connected to the AD1843's MIC input. The mic
jack is mono, but the signal is delivered to both the left and right
MIC inputs. You can record in stereo from the mic input, but you will
get the same signal on both channels (within the limits of A/D
accuracy). Full scale on the Line input is +/- 2.0 V. Full scale on
the MIC input is 20 dB less, or +/- 0.2 V.
The AD1843's LOUT1 outputs are connected to the Line Out jacks. The
AD1843's HPOUT outputs are connected to the speaker/headphone jack.
LOUT2 is not connected. Line out's maximum level is +/- 2.0 V peak to
peak. The speaker/headphone out's maximum is +/- 4.0 V peak to peak.
The AD1843's PCM input channel and one of its output channels (DAC1)
are connected to Lithium. The other output channel (DAC2) is not
connected.
==============================================================================
CAPABILITIES
The AD1843 has PCM input and output (Pulse Code Modulation, also known
as wavetable). PCM input and output can be mono or stereo in any of
four formats. The formats are 16 bit signed and 8 bit unsigned,
u-Law, and A-Law format. Any sample rate from 4 KHz to 49 KHz is
available, in 1 Hz increments.
The AD1843 includes an analog mixer that can mix all three input
signals (line, mic and CD) into the analog outputs. The mixer has a
separate gain control and mute switch for each input.
There are two outputs, line out and speaker/headphone out. They
always produce the same signal, and the speaker always has 3 dB more
gain than the line out. The speaker/headphone output can be muted,
but this driver does not export that function.
The hardware can sync audio to the video clock, but this driver does
not have a way to specify syncing to video.
==============================================================================
PROGRAMMING
This section explains the API supported by the driver. Also see the
Open Sound Programming Guide at http://www.opensound.com/pguide/ .
This section assumes familiarity with that document.
The driver has two interfaces, an I/O interface and a mixer interface.
There is no MIDI or sequencer capability.
==============================================================================
PROGRAMMING PCM I/O
The I/O interface is usually accessed as /dev/audio or /dev/dsp.
Using the standard Open Sound System (OSS) ioctl calls, the sample
rate, number of channels, and sample format may be set within the
limitations described above. The driver supports triggering. It also
supports getting the input and output pointers with one-sample
accuracy.
The SNDCTL_DSP_GETCAP ioctl returns these capabilities.
DSP_CAP_DUPLEX - driver supports full duplex.
DSP_CAP_TRIGGER - driver supports triggering.
DSP_CAP_REALTIME - values returned by SNDCTL_DSP_GETIPTR
and SNDCTL_DSP_GETOPTR are accurate to a few samples.
Memory mapping (mmap) is not implemented.
The driver permits subdivided fragment sizes from 64 to 4096 bytes.
The number of fragments can be anything from 3 fragments to however
many fragments fit into 124 kilobytes. It is up to the user to
determine how few/small fragments can be used without introducing
glitches with a given workload. Linux is not realtime, so we can't
promise anything. (sigh...)
When this driver is switched into or out of mu-Law or A-Law mode on
output, it may produce an audible click. This is unavoidable. To
prevent clicking, use signed 16-bit mode instead, and convert from
mu-Law or A-Law format in software.
==============================================================================
PROGRAMMING THE MIXER INTERFACE
The mixer interface is usually accessed as /dev/mixer. It is accessed
through ioctls. The mixer allows the application to control gain or
mute several audio signal paths, and also allows selection of the
recording source.
Each of the constants described here can be read using the
MIXER_READ(SOUND_MIXER_xxx) ioctl. Those that are not read-only can
also be written using the MIXER_WRITE(SOUND_MIXER_xxx) ioctl. In most
cases, <sys/soundcard.h> defines constants SOUND_MIXER_READ_xxx and
SOUND_MIXER_WRITE_xxx which work just as well.
SOUND_MIXER_CAPS Read-only
This is a mask of optional driver capabilities that are implemented.
This driver's only capability is SOUND_CAP_EXCL_INPUT, which means
that only one recording source can be active at a time.
SOUND_MIXER_DEVMASK Read-only
This is a mask of the sound channels. This driver's channels are PCM,
LINE, MIC, CD, and RECLEV.
SOUND_MIXER_STEREODEVS Read-only
This is a mask of which sound channels are capable of stereo. All
channels are capable of stereo. (But see caveat on MIC input in I/O
CONNECTIONS section above).
SOUND_MIXER_OUTMASK Read-only
This is a mask of channels that route inputs through to outputs.
Those are LINE, MIC, and CD.
SOUND_MIXER_RECMASK Read-only
This is a mask of channels that can be recording sources. Those are
PCM, LINE, MIC, CD.
SOUND_MIXER_PCM Default: 0x5757 (0 dB)
This is the gain control for PCM output. The left and right channel
gain are controlled independently. This gain control has 64 levels,
which range from -82.5 dB to +12.0 dB in 1.5 dB steps. Those 64
levels are mapped onto 100 levels at the ioctl, see below.
SOUND_MIXER_LINE Default: 0x4a4a (0 dB)
This is the gain control for mixing the Line In source into the
outputs. The left and right channel gain are controlled
independently. This gain control has 32 levels, which range from
-34.5 dB to +12.0 dB in 1.5 dB steps. Those 32 levels are mapped onto
100 levels at the ioctl, see below.
SOUND_MIXER_MIC Default: 0x4a4a (0 dB)
This is the gain control for mixing the MIC source into the outputs.
The left and right channel gain are controlled independently. This
gain control has 32 levels, which range from -34.5 dB to +12.0 dB in
1.5 dB steps. Those 32 levels are mapped onto 100 levels at the
ioctl, see below.
SOUND_MIXER_CD Default: 0x4a4a (0 dB)
This is the gain control for mixing the CD audio source into the
outputs. The left and right channel gain are controlled
independently. This gain control has 32 levels, which range from
-34.5 dB to +12.0 dB in 1.5 dB steps. Those 32 levels are mapped onto
100 levels at the ioctl, see below.
SOUND_MIXER_RECLEV Default: 0 (0 dB)
This is the gain control for PCM input (RECording LEVel). The left
and right channel gain are controlled independently. This gain
control has 16 levels, which range from 0 dB to +22.5 dB in 1.5 dB
steps. Those 16 levels are mapped onto 100 levels at the ioctl, see
below.
SOUND_MIXER_RECSRC Default: SOUND_MASK_LINE
This is a mask of currently selected PCM input sources (RECording
SouRCes). Because the AD1843 can only have a single recording source
at a time, only one bit at a time can be set in this mask. The
allowable values are SOUND_MASK_PCM, SOUND_MASK_LINE, SOUND_MASK_MIC,
or SOUND_MASK_CD. Selecting SOUND_MASK_PCM sets up internal
resampling which is useful for loopback testing and for hardware
sample rate conversion. But software sample rate conversion is
probably faster, so I don't know how useful that is.
SOUND_MIXER_OUTSRC DEFAULT: SOUND_MASK_LINE|SOUND_MASK_MIC|SOUND_MASK_CD
This is a mask of sources that are currently passed through to the
outputs. Those sources whose bits are not set are muted.
==============================================================================
GAIN CONTROL
There are five gain controls listed above. Each has 16, 32, or 64
steps. Each control has 1.5 dB of gain per step. Each control is
stereo.
The OSS defines the argument to a channel gain ioctl as having two
components, left and right, each of which ranges from 0 to 100. The
two components are packed into the same word, with the left side gain
in the least significant byte, and the right side gain in the second
least significant byte. In C, we would say this.
#include <assert.h>
...
assert(leftgain >= 0 && leftgain <= 100);
assert(rightgain >= 0 && rightgain <= 100);
arg = leftgain | rightgain << 8;
So each OSS gain control has 101 steps. But the hardware has 16, 32,
or 64 steps. The hardware steps are spread across the 101 OSS steps
nearly evenly. The conversion formulas are like this, given N equals
16, 32, or 64.
int round = N/2 - 1;
OSS_gain_steps = (hw_gain_steps * 100 + round) / (N - 1);
hw_gain_steps = (OSS_gain_steps * (N - 1) + round) / 100;
Here is a snippet of C code that will return the left and right gain
of any channel in dB. Pass it one of the predefined gain_desc_t
structures to access any of the five channels' gains.
typedef struct gain_desc {
float min_gain;
float gain_step;
int nbits;
int chan;
} gain_desc_t;
const gain_desc_t gain_pcm = { -82.5, 1.5, 6, SOUND_MIXER_PCM };
const gain_desc_t gain_line = { -34.5, 1.5, 5, SOUND_MIXER_LINE };
const gain_desc_t gain_mic = { -34.5, 1.5, 5, SOUND_MIXER_MIC };
const gain_desc_t gain_cd = { -34.5, 1.5, 5, SOUND_MIXER_CD };
const gain_desc_t gain_reclev = { 0.0, 1.5, 4, SOUND_MIXER_RECLEV };
int get_gain_dB(int fd, const gain_desc_t *gp,
float *left, float *right)
{
int word;
int lg, rg;
int mask = (1 << gp->nbits) - 1;
if (ioctl(fd, MIXER_READ(gp->chan), &word) != 0)
return -1; /* fail */
lg = word & 0xFF;
rg = word >> 8 & 0xFF;
lg = (lg * mask + mask / 2) / 100;
rg = (rg * mask + mask / 2) / 100;
*left = gp->min_gain + gp->gain_step * lg;
*right = gp->min_gain + gp->gain_step * rg;
return 0;
}
And here is the corresponding routine to set a channel's gain in dB.
int set_gain_dB(int fd, const gain_desc_t *gp, float left, float right)
{
float max_gain =
gp->min_gain + (1 << gp->nbits) * gp->gain_step;
float round = gp->gain_step / 2;
int mask = (1 << gp->nbits) - 1;
int word;
int lg, rg;
if (left < gp->min_gain || right < gp->min_gain)
return EINVAL;
lg = (left - gp->min_gain + round) / gp->gain_step;
rg = (right - gp->min_gain + round) / gp->gain_step;
if (lg >= (1 << gp->nbits) || rg >= (1 << gp->nbits))
return EINVAL;
lg = (100 * lg + mask / 2) / mask;
rg = (100 * rg + mask / 2) / mask;
word = lg | rg << 8;
return ioctl(fd, MIXER_WRITE(gp->chan), &word);
}

7
MAINTAINERS
View File

@ -7757,13 +7757,6 @@ F: Documentation/ia64/serial.txt
F: drivers/tty/serial/ioc?_serial.c
F: include/linux/ioc?.h
SGI VISUAL WORKSTATION 320 AND 540
M: Andrey Panin <pazke@donpac.ru>
L: linux-visws-devel@lists.sf.net
W: http://linux-visws.sf.net
S: Maintained for 2.6.
F: Documentation/sgi-visws.txt
SGI XP/XPC/XPNET DRIVER
M: Cliff Whickman <cpw@sgi.com>
M: Robin Holt <robinmholt@gmail.com>

17
arch/x86/Kconfig
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@ -517,19 +517,6 @@ config X86_SUPPORTS_MEMORY_FAILURE
depends on X86_64 || !SPARSEMEM
select ARCH_SUPPORTS_MEMORY_FAILURE
config X86_VISWS
bool "SGI 320/540 (Visual Workstation)"
depends on X86_32 && PCI && X86_MPPARSE && PCI_GODIRECT
depends on X86_32_NON_STANDARD
---help---
The SGI Visual Workstation series is an IA32-based workstation
based on SGI systems chips with some legacy PC hardware attached.
Say Y here to create a kernel to run on the SGI 320 or 540.
A kernel compiled for the Visual Workstation will run on general
PCs as well. See <file:Documentation/sgi-visws.txt> for details.
config STA2X11
bool "STA2X11 Companion Chip Support"
depends on X86_32_NON_STANDARD && PCI
@ -860,10 +847,6 @@ config X86_IO_APIC
def_bool y
depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_IOAPIC || PCI_MSI
config X86_VISWS_APIC
def_bool y
depends on X86_32 && X86_VISWS
config X86_REROUTE_FOR_BROKEN_BOOT_IRQS
bool "Reroute for broken boot IRQs"
depends on X86_IO_APIC

6
arch/x86/include/asm/fixmap.h
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@ -97,12 +97,6 @@ enum fixed_addresses {
#ifdef CONFIG_X86_IO_APIC
FIX_IO_APIC_BASE_0,
FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1,
#endif
#ifdef CONFIG_X86_VISWS_APIC
FIX_CO_CPU, /* Cobalt timer */
FIX_CO_APIC, /* Cobalt APIC Redirection Table */
FIX_LI_PCIA, /* Lithium PCI Bridge A */
FIX_LI_PCIB, /* Lithium PCI Bridge B */
#endif
FIX_RO_IDT, /* Virtual mapping for read-only IDT */
#ifdef CONFIG_X86_32

1
arch/x86/include/asm/hw_irq.h
View File

@ -98,7 +98,6 @@ extern void trace_call_function_single_interrupt(void);
#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1<<(x)) & io_apic_irqs))
extern unsigned long io_apic_irqs;
extern void init_VISWS_APIC_irqs(void);
extern void setup_IO_APIC(void);
extern void disable_IO_APIC(void);

6
arch/x86/include/asm/setup.h
View File

@ -39,12 +39,6 @@ static inline void vsmp_init(void) { }
void setup_bios_corruption_check(void);
#ifdef CONFIG_X86_VISWS
extern void visws_early_detect(void);
#else
static inline void visws_early_detect(void) { }
#endif
extern unsigned long saved_video_mode;
extern void reserve_standard_io_resources(void);

127
arch/x86/include/asm/visws/cobalt.h
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@ -1,127 +0,0 @@
#ifndef _ASM_X86_VISWS_COBALT_H
#define _ASM_X86_VISWS_COBALT_H
#include <asm/fixmap.h>
/*
* Cobalt SGI Visual Workstation system ASIC
*/
#define CO_CPU_NUM_PHYS 0x1e00
#define CO_CPU_TAB_PHYS (CO_CPU_NUM_PHYS + 2)
#define CO_CPU_MAX 4
#define CO_CPU_PHYS 0xc2000000
#define CO_APIC_PHYS 0xc4000000
/* see set_fixmap() and asm/fixmap.h */
#define CO_CPU_VADDR (fix_to_virt(FIX_CO_CPU))
#define CO_APIC_VADDR (fix_to_virt(FIX_CO_APIC))
/* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */
#define CO_CPU_REV 0x08
#define CO_CPU_CTRL 0x10
#define CO_CPU_STAT 0x20
#define CO_CPU_TIMEVAL 0x30
/* CO_CPU_CTRL bits */
#define CO_CTRL_TIMERUN 0x04 /* 0 == disabled */
#define CO_CTRL_TIMEMASK 0x08 /* 0 == unmasked */
/* CO_CPU_STATUS bits */
#define CO_STAT_TIMEINTR 0x02 /* (r) 1 == int pend, (w) 0 == clear */
/* CO_CPU_TIMEVAL value */
#define CO_TIME_HZ 100000000 /* Cobalt core rate */
/* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */
#define CO_APIC_HI(n) (((n) * 0x10) + 4)
#define CO_APIC_LO(n) ((n) * 0x10)
#define CO_APIC_ID 0x0ffc
/* CO_APIC_ID bits */
#define CO_APIC_ENABLE 0x00000100
/* CO_APIC_LO bits */
#define CO_APIC_MASK 0x00010000 /* 0 = enabled */
#define CO_APIC_LEVEL 0x00008000 /* 0 = edge */
/*
* Where things are physically wired to Cobalt
* #defines with no board _<type>_<rev>_ are common to all (thus far)
*/
#define CO_APIC_IDE0 4
#define CO_APIC_IDE1 2 /* Only on 320 */
#define CO_APIC_8259 12 /* serial, floppy, par-l-l */
/* Lithium PCI Bridge A -- "the one with 82557 Ethernet" */
#define CO_APIC_PCIA_BASE0 0 /* and 1 */ /* slot 0, line 0 */
#define CO_APIC_PCIA_BASE123 5 /* and 6 */ /* slot 0, line 1 */
#define CO_APIC_PIIX4_USB 7 /* this one is weird */
/* Lithium PCI Bridge B -- "the one with PIIX4" */
#define CO_APIC_PCIB_BASE0 8 /* and 9-12 *//* slot 0, line 0 */
#define CO_APIC_PCIB_BASE123 13 /* 14.15 */ /* slot 0, line 1 */
#define CO_APIC_VIDOUT0 16
#define CO_APIC_VIDOUT1 17
#define CO_APIC_VIDIN0 18
#define CO_APIC_VIDIN1 19
#define CO_APIC_LI_AUDIO 22
#define CO_APIC_AS 24
#define CO_APIC_RE 25
#define CO_APIC_CPU 28 /* Timer and Cache interrupt */
#define CO_APIC_NMI 29
#define CO_APIC_LAST CO_APIC_NMI
/*
* This is how irqs are assigned on the Visual Workstation.
* Legacy devices get irq's 1-15 (system clock is 0 and is CO_APIC_CPU).
* All other devices (including PCI) go to Cobalt and are irq's 16 on up.
*/
#define CO_IRQ_APIC0 16 /* irq of apic entry 0 */
#define IS_CO_APIC(irq) ((irq) >= CO_IRQ_APIC0)
#define CO_IRQ(apic) (CO_IRQ_APIC0 + (apic)) /* apic ent to irq */
#define CO_APIC(irq) ((irq) - CO_IRQ_APIC0) /* irq to apic ent */
#define CO_IRQ_IDE0 14 /* knowledge of... */
#define CO_IRQ_IDE1 15 /* ... ide driver defaults! */
#define CO_IRQ_8259 CO_IRQ(CO_APIC_8259)
#ifdef CONFIG_X86_VISWS_APIC
static inline void co_cpu_write(unsigned long reg, unsigned long v)
{
*((volatile unsigned long *)(CO_CPU_VADDR+reg))=v;
}
static inline unsigned long co_cpu_read(unsigned long reg)
{
return *((volatile unsigned long *)(CO_CPU_VADDR+reg));
}
static inline void co_apic_write(unsigned long reg, unsigned long v)
{
*((volatile unsigned long *)(CO_APIC_VADDR+reg))=v;
}
static inline unsigned long co_apic_read(unsigned long reg)
{
return *((volatile unsigned long *)(CO_APIC_VADDR+reg));
}
#endif
extern char visws_board_type;
#define VISWS_320 0
#define VISWS_540 1
extern char visws_board_rev;
extern int pci_visws_init(void);
#endif /* _ASM_X86_VISWS_COBALT_H */

53
arch/x86/include/asm/visws/lithium.h
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@ -1,53 +0,0 @@
#ifndef _ASM_X86_VISWS_LITHIUM_H
#define _ASM_X86_VISWS_LITHIUM_H
#include <asm/fixmap.h>
/*
* Lithium is the SGI Visual Workstation I/O ASIC
*/
#define LI_PCI_A_PHYS 0xfc000000 /* Enet is dev 3 */
#define LI_PCI_B_PHYS 0xfd000000 /* PIIX4 is here */
/* see set_fixmap() and asm/fixmap.h */
#define LI_PCIA_VADDR (fix_to_virt(FIX_LI_PCIA))
#define LI_PCIB_VADDR (fix_to_virt(FIX_LI_PCIB))
/* Not a standard PCI? (not in linux/pci.h) */
#define LI_PCI_BUSNUM 0x44 /* lo8: primary, hi8: sub */
#define LI_PCI_INTEN 0x46
/* LI_PCI_INTENT bits */
#define LI_INTA_0 0x0001
#define LI_INTA_1 0x0002
#define LI_INTA_2 0x0004
#define LI_INTA_3 0x0008
#define LI_INTA_4 0x0010
#define LI_INTB 0x0020
#define LI_INTC 0x0040
#define LI_INTD 0x0080
/* More special purpose macros... */
static inline void li_pcia_write16(unsigned long reg, unsigned short v)
{
*((volatile unsigned short *)(LI_PCIA_VADDR+reg))=v;
}
static inline unsigned short li_pcia_read16(unsigned long reg)
{
return *((volatile unsigned short *)(LI_PCIA_VADDR+reg));
}
static inline void li_pcib_write16(unsigned long reg, unsigned short v)
{
*((volatile unsigned short *)(LI_PCIB_VADDR+reg))=v;
}
static inline unsigned short li_pcib_read16(unsigned long reg)
{
return *((volatile unsigned short *)(LI_PCIB_VADDR+reg));
}
#endif /* _ASM_X86_VISWS_LITHIUM_H */

107
arch/x86/include/asm/visws/piix4.h
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@ -1,107 +0,0 @@
#ifndef _ASM_X86_VISWS_PIIX4_H
#define _ASM_X86_VISWS_PIIX4_H
/*
* PIIX4 as used on SGI Visual Workstations
*/
#define PIIX_PM_START 0x0F80
#define SIO_GPIO_START 0x0FC0
#define SIO_PM_START 0x0FC8
#define PMBASE PIIX_PM_START
#define GPIREG0 (PMBASE+0x30)
#define GPIREG(x) (GPIREG0+((x)/8))
#define GPIBIT(x) (1 << ((x)%8))
#define PIIX_GPI_BD_ID1 18
#define PIIX_GPI_BD_ID2 19
#define PIIX_GPI_BD_ID3 20
#define PIIX_GPI_BD_ID4 21
#define PIIX_GPI_BD_REG GPIREG(PIIX_GPI_BD_ID1)
#define PIIX_GPI_BD_MASK (GPIBIT(PIIX_GPI_BD_ID1) | \
GPIBIT(PIIX_GPI_BD_ID2) | \
GPIBIT(PIIX_GPI_BD_ID3) | \
GPIBIT(PIIX_GPI_BD_ID4) )
#define PIIX_GPI_BD_SHIFT (PIIX_GPI_BD_ID1 % 8)
#define SIO_INDEX 0x2e
#define SIO_DATA 0x2f
#define SIO_DEV_SEL 0x7
#define SIO_DEV_ENB 0x30
#define SIO_DEV_MSB 0x60
#define SIO_DEV_LSB 0x61
#define SIO_GP_DEV 0x7
#define SIO_GP_BASE SIO_GPIO_START
#define SIO_GP_MSB (SIO_GP_BASE>>8)
#define SIO_GP_LSB (SIO_GP_BASE&0xff)
#define SIO_GP_DATA1 (SIO_GP_BASE+0)
#define SIO_PM_DEV 0x8
#define SIO_PM_BASE SIO_PM_START
#define SIO_PM_MSB (SIO_PM_BASE>>8)
#define SIO_PM_LSB (SIO_PM_BASE&0xff)
#define SIO_PM_INDEX (SIO_PM_BASE+0)
#define SIO_PM_DATA (SIO_PM_BASE+1)
#define SIO_PM_FER2 0x1
#define SIO_PM_GP_EN 0x80
/*
* This is the dev/reg where generating a config cycle will
* result in a PCI special cycle.
*/
#define SPECIAL_DEV 0xff
#define SPECIAL_REG 0x00
/*
* PIIX4 needs to see a special cycle with the following data
* to be convinced the processor has gone into the stop grant
* state. PIIX4 insists on seeing this before it will power
* down a system.
*/
#define PIIX_SPECIAL_STOP 0x00120002
#define PIIX4_RESET_PORT 0xcf9
#define PIIX4_RESET_VAL 0x6
#define PMSTS_PORT 0xf80 // 2 bytes PM Status
#define PMEN_PORT 0xf82 // 2 bytes PM Enable
#define PMCNTRL_PORT 0xf84 // 2 bytes PM Control
#define PM_SUSPEND_ENABLE 0x2000 // start sequence to suspend state
/*
* PMSTS and PMEN I/O bit definitions.
* (Bits are the same in both registers)
*/
#define PM_STS_RSM (1<<15) // Resume Status
#define PM_STS_PWRBTNOR (1<<11) // Power Button Override
#define PM_STS_RTC (1<<10) // RTC status
#define PM_STS_PWRBTN (1<<8) // Power Button Pressed?
#define PM_STS_GBL (1<<5) // Global Status
#define PM_STS_BM (1<<4) // Bus Master Status
#define PM_STS_TMROF (1<<0) // Timer Overflow Status.
/*
* Stop clock GPI register
*/
#define PIIX_GPIREG0 (0xf80 + 0x30)
/*
* Stop clock GPI bit in GPIREG0
*/
#define PIIX_GPI_STPCLK 0x4 // STPCLK signal routed back in
#endif /* _ASM_X86_VISWS_PIIX4_H */

5
arch/x86/include/asm/visws/sgivw.h
View File

@ -1,5 +0,0 @@
/*
* Frame buffer position and size:
*/
extern unsigned long sgivwfb_mem_phys;
extern unsigned long sgivwfb_mem_size;

1
arch/x86/kernel/apic/apic.c
View File

@ -2132,7 +2132,6 @@ int generic_processor_info(int apicid, int version)
*
* - arch/x86/kernel/mpparse.c: MP_processor_info()
* - arch/x86/mm/amdtopology.c: amd_numa_init()
* - arch/x86/platform/visws/visws_quirks.c: MP_processor_info()
*
* This function is executed with the modified
* boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel

1
arch/x86/kernel/setup.c
View File

@ -869,7 +869,6 @@ void __init setup_arch(char **cmdline_p)
#ifdef CONFIG_X86_32
memcpy(&boot_cpu_data, &new_cpu_data, sizeof(new_cpu_data));
visws_early_detect();
/*
* copy kernel address range established so far and switch

2
arch/x86/pci/Makefile
View File

@ -13,8 +13,6 @@ obj-y += legacy.o irq.o
obj-$(CONFIG_STA2X11) += sta2x11-fixup.o
obj-$(CONFIG_X86_VISWS) += visws.o
obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
obj-$(CONFIG_X86_NUMACHIP) += numachip.o

5
arch/x86/pci/common.c
View File

@ -561,7 +561,6 @@ char * __init pcibios_setup(char *str)
pci_probe |= PCI_PROBE_NOEARLY;
return NULL;
}
#ifndef CONFIG_X86_VISWS
else if (!strcmp(str, "usepirqmask")) {
pci_probe |= PCI_USE_PIRQ_MASK;
return NULL;
@ -571,9 +570,7 @@ char * __init pcibios_setup(char *str)
} else if (!strncmp(str, "lastbus=", 8)) {
pcibios_last_bus = simple_strtol(str+8, NULL, 0);
return NULL;
}
#endif
else if (!strcmp(str, "rom")) {
} else if (!strcmp(str, "rom")) {
pci_probe |= PCI_ASSIGN_ROMS;
return NULL;
} else if (!strcmp(str, "norom")) {

87
arch/x86/pci/visws.c
View File

@ -1,87 +0,0 @@
/*
* Low-Level PCI Support for SGI Visual Workstation
*
* (c) 1999--2000 Martin Mares <mj@ucw.cz>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <asm/setup.h>
#include <asm/pci_x86.h>
#include <asm/visws/cobalt.h>
#include <asm/visws/lithium.h>
static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
static void pci_visws_disable_irq(struct pci_dev *dev) { }
/* int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq; */
/* void (*pcibios_disable_irq)(struct pci_dev *dev) = &pci_visws_disable_irq; */
/* void __init pcibios_penalize_isa_irq(int irq, int active) {} */
unsigned int pci_bus0, pci_bus1;
static int __init visws_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq, bus = dev->bus->number;
pin--;
/* Nothing useful at PIIX4 pin 1 */
if (bus == pci_bus0 && slot == 4 && pin == 0)
return -1;
/* PIIX4 USB is on Bus 0, Slot 4, Line 3 */
if (bus == pci_bus0 && slot == 4 && pin == 3) {
irq = CO_IRQ(CO_APIC_PIIX4_USB);
goto out;
}
/* First pin spread down 1 APIC entry per slot */
if (pin == 0) {
irq = CO_IRQ((bus == pci_bus0 ? CO_APIC_PCIB_BASE0 :
CO_APIC_PCIA_BASE0) + slot);
goto out;
}
/* lines 1,2,3 from any slot is shared in this twirly pattern */
if (bus == pci_bus1) {
/* lines 1-3 from devices 0 1 rotate over 2 apic entries */
irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((slot + (pin - 1)) % 2));
} else { /* bus == pci_bus0 */
/* lines 1-3 from devices 0-3 rotate over 3 apic entries */
if (slot == 0)
slot = 3; /* same pattern */
irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((3 - slot) + (pin - 1) % 3));
}
out:
printk(KERN_DEBUG "PCI: Bus %d Slot %d Line %d -> IRQ %d\n", bus, slot, pin, irq);
return irq;
}
int __init pci_visws_init(void)
{
pcibios_enable_irq = &pci_visws_enable_irq;
pcibios_disable_irq = &pci_visws_disable_irq;
/* The VISWS supports configuration access type 1 only */
pci_probe = (pci_probe | PCI_PROBE_CONF1) &
~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);
pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
"bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
raw_pci_ops = &pci_direct_conf1;
pci_scan_bus_with_sysdata(pci_bus0);
pci_scan_bus_with_sysdata(pci_bus1);
pci_fixup_irqs(pci_common_swizzle, visws_map_irq);
pcibios_resource_survey();
/* Request bus scan */
return 1;
}

1
arch/x86/platform/Makefile
View File

@ -9,5 +9,4 @@ obj-y += olpc/
obj-y += scx200/
obj-y += sfi/
obj-y += ts5500/
obj-y += visws/
obj-y += uv/

1
arch/x86/platform/visws/Makefile
View File

@ -1 +0,0 @@
obj-$(CONFIG_X86_VISWS) += visws_quirks.o

608
arch/x86/platform/visws/visws_quirks.c
View File

@ -1,608 +0,0 @@
/*
* SGI Visual Workstation support and quirks, unmaintained.
*
* Split out from setup.c by davej@suse.de
*
* Copyright (C) 1999 Bent Hagemark, Ingo Molnar
*
* SGI Visual Workstation interrupt controller
*
* The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
* which serves as the main interrupt controller in the system. Non-legacy
* hardware in the system uses this controller directly. Legacy devices
* are connected to the PIIX4 which in turn has its 8259(s) connected to
* a of the Cobalt APIC entry.
*
* 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
*
* 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
*/
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <asm/visws/cobalt.h>
#include <asm/visws/piix4.h>
#include <asm/io_apic.h>
#include <asm/fixmap.h>
#include <asm/reboot.h>
#include <asm/setup.h>
#include <asm/apic.h>
#include <asm/e820.h>
#include <asm/time.h>
#include <asm/io.h>
#include <linux/kernel_stat.h>
#include <asm/i8259.h>
#include <asm/irq_vectors.h>
#include <asm/visws/lithium.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
extern int no_broadcast;
char visws_board_type = -1;
char visws_board_rev = -1;
static void __init visws_time_init(void)
{
printk(KERN_INFO "Starting Cobalt Timer system clock\n");
/* Set the countdown value */
co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
/* Start the timer */
co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
/* Enable (unmask) the timer interrupt */
co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
setup_default_timer_irq();
}
/* Replaces the default init_ISA_irqs in the generic setup */
static void __init visws_pre_intr_init(void);
/* Quirk for machine specific memory setup. */
#define MB (1024 * 1024)
unsigned long sgivwfb_mem_phys;
unsigned long sgivwfb_mem_size;
EXPORT_SYMBOL(sgivwfb_mem_phys);
EXPORT_SYMBOL(sgivwfb_mem_size);
long long mem_size __initdata = 0;
static char * __init visws_memory_setup(void)
{
long long gfx_mem_size = 8 * MB;
mem_size = boot_params.alt_mem_k;
if (!mem_size) {
printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
mem_size = 128 * MB;
}
/*
* this hardcodes the graphics memory to 8 MB
* it really should be sized dynamically (or at least
* set as a boot param)
*/
if (!sgivwfb_mem_size) {
printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
sgivwfb_mem_size = 8 * MB;
}
/*
* Trim to nearest MB
*/
sgivwfb_mem_size &= ~((1 << 20) - 1);
sgivwfb_mem_phys = mem_size - gfx_mem_size;
e820_add_region(0, LOWMEMSIZE(), E820_RAM);
e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
return "PROM";
}
static void visws_machine_emergency_restart(void)
{
/*
* Visual Workstations restart after this
* register is poked on the PIIX4
*/
outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
}
static void visws_machine_power_off(void)
{
unsigned short pm_status;
/* extern unsigned int pci_bus0; */
while ((pm_status = inw(PMSTS_PORT)) & 0x100)
outw(pm_status, PMSTS_PORT);
outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
mdelay(10);
#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
(0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
/* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
outl(PIIX_SPECIAL_STOP, 0xCFC);
}
static void __init visws_get_smp_config(unsigned int early)
{
}
/*
* The Visual Workstation is Intel MP compliant in the hardware
* sense, but it doesn't have a BIOS(-configuration table).
* No problem for Linux.
*/
static void __init MP_processor_info(struct mpc_cpu *m)
{
int ver, logical_apicid;
physid_mask_t apic_cpus;
if (!(m->cpuflag & CPU_ENABLED))
return;
logical_apicid = m->apicid;
printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
m->cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
(m->cpufeature & CPU_MODEL_MASK) >> 4, m->apicver);
if (m->cpuflag & CPU_BOOTPROCESSOR)
boot_cpu_physical_apicid = m->apicid;
ver = m->apicver;
if ((ver >= 0x14 && m->apicid >= 0xff) || m->apicid >= 0xf) {
printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
m->apicid, MAX_LOCAL_APIC);
return;
}
apic->apicid_to_cpu_present(m->apicid, &apic_cpus);
physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
/*
* Validate version
*/
if (ver == 0x0) {
printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
"fixing up to 0x10. (tell your hw vendor)\n",
m->apicid);
ver = 0x10;
}
apic_version[m->apicid] = ver;
}
static void __init visws_find_smp_config(void)
{
struct mpc_cpu *mp = phys_to_virt(CO_CPU_TAB_PHYS);
unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
if (ncpus > CO_CPU_MAX) {
printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
ncpus, mp);
ncpus = CO_CPU_MAX;
}
if (ncpus > setup_max_cpus)
ncpus = setup_max_cpus;
#ifdef CONFIG_X86_LOCAL_APIC
smp_found_config = 1;
#endif
while (ncpus--)
MP_processor_info(mp++);
mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
}
static void visws_trap_init(void);
void __init visws_early_detect(void)
{
int raw;
visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
>> PIIX_GPI_BD_SHIFT;
if (visws_board_type < 0)
return;
/*
* Override the default platform setup functions
*/
x86_init.resources.memory_setup = visws_memory_setup;
x86_init.mpparse.get_smp_config = visws_get_smp_config;
x86_init.mpparse.find_smp_config = visws_find_smp_config;
x86_init.irqs.pre_vector_init = visws_pre_intr_init;
x86_init.irqs.trap_init = visws_trap_init;
x86_init.timers.timer_init = visws_time_init;
x86_init.pci.init = pci_visws_init;
x86_init.pci.init_irq = x86_init_noop;
/*
* Install reboot quirks:
*/
pm_power_off = visws_machine_power_off;
machine_ops.emergency_restart = visws_machine_emergency_restart;
/*
* Do not use broadcast IPIs:
*/
no_broadcast = 0;
#ifdef CONFIG_X86_IO_APIC
/*
* Turn off IO-APIC detection and initialization:
*/
skip_ioapic_setup = 1;
#endif
/*
* Get Board rev.
* First, we have to initialize the 307 part to allow us access
* to the GPIO registers. Let's map them at 0x0fc0 which is right
* after the PIIX4 PM section.
*/
outb_p(SIO_DEV_SEL, SIO_INDEX);
outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */
outb_p(SIO_DEV_MSB, SIO_INDEX);
outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */
outb_p(SIO_DEV_LSB, SIO_INDEX);
outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */
outb_p(SIO_DEV_ENB, SIO_INDEX);
outb_p(1, SIO_DATA); /* Enable GPIO registers. */
/*
* Now, we have to map the power management section to write
* a bit which enables access to the GPIO registers.
* What lunatic came up with this shit?
*/
outb_p(SIO_DEV_SEL, SIO_INDEX);
outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */
outb_p(SIO_DEV_MSB, SIO_INDEX);
outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */
outb_p(SIO_DEV_LSB, SIO_INDEX);
outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */
outb_p(SIO_DEV_ENB, SIO_INDEX);
outb_p(1, SIO_DATA); /* Enable PM registers. */
/*
* Now, write the PM register which enables the GPIO registers.
*/
outb_p(SIO_PM_FER2, SIO_PM_INDEX);
outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
/*
* Now, initialize the GPIO registers.
* We want them all to be inputs which is the
* power on default, so let's leave them alone.
* So, let's just read the board rev!
*/
raw = inb_p(SIO_GP_DATA1);
raw &= 0x7f; /* 7 bits of valid board revision ID. */
if (visws_board_type == VISWS_320) {
if (raw < 0x6) {
visws_board_rev = 4;
} else if (raw < 0xc) {
visws_board_rev = 5;
} else {
visws_board_rev = 6;
}
} else if (visws_board_type == VISWS_540) {
visws_board_rev = 2;
} else {
visws_board_rev = raw;
}
printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
(visws_board_type == VISWS_320 ? "320" :
(visws_board_type == VISWS_540 ? "540" :
"unknown")), visws_board_rev);
}
#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
#define BCD (LI_INTB | LI_INTC | LI_INTD)
#define ALLDEVS (A01234 | BCD)
static __init void lithium_init(void)
{
set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
(li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
/* panic("This machine is not SGI Visual Workstation 320/540"); */
}
if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
(li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
/* panic("This machine is not SGI Visual Workstation 320/540"); */
}
li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
}
static __init void cobalt_init(void)
{
/*
* On normal SMP PC this is used only with SMP, but we have to
* use it and set it up here to start the Cobalt clock
*/
set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
setup_local_APIC();
printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
(unsigned int)apic_read(APIC_LVR),
(unsigned int)apic_read(APIC_ID));
set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
/* Enable Cobalt APIC being careful to NOT change the ID! */
co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
co_apic_read(CO_APIC_ID));
}
static void __init visws_trap_init(void)
{
lithium_init();
cobalt_init();
}
/*
* IRQ controller / APIC support:
*/
static DEFINE_SPINLOCK(cobalt_lock);
/*
* Set the given Cobalt APIC Redirection Table entry to point
* to the given IDT vector/index.
*/
static inline void co_apic_set(int entry, int irq)
{
co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
co_apic_write(CO_APIC_HI(entry), 0);
}
/*
* Cobalt (IO)-APIC functions to handle PCI devices.
*/
static inline int co_apic_ide0_hack(void)
{
extern char visws_board_type;
extern char visws_board_rev;
if (visws_board_type == VISWS_320 && visws_board_rev == 5)
return 5;
return CO_APIC_IDE0;
}
static int is_co_apic(unsigned int irq)
{
if (IS_CO_APIC(irq))
return CO_APIC(irq);
switch (irq) {
case 0: return CO_APIC_CPU;
case CO_IRQ_IDE0: return co_apic_ide0_hack();
case CO_IRQ_IDE1: return CO_APIC_IDE1;
default: return -1;
}
}
/*
* This is the SGI Cobalt (IO-)APIC:
*/
static void enable_cobalt_irq(struct irq_data *data)
{
co_apic_set(is_co_apic(data->irq), data->irq);
}
static void disable_cobalt_irq(struct irq_data *data)
{
int entry = is_co_apic(data->irq);
co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
co_apic_read(CO_APIC_LO(entry));
}
static void ack_cobalt_irq(struct irq_data *data)
{
unsigned long flags;
spin_lock_irqsave(&cobalt_lock, flags);
disable_cobalt_irq(data);
apic_write(APIC_EOI, APIC_EOI_ACK);
spin_unlock_irqrestore(&cobalt_lock, flags);
}
static struct irq_chip cobalt_irq_type = {
.name = "Cobalt-APIC",
.irq_enable = enable_cobalt_irq,
.irq_disable = disable_cobalt_irq,
.irq_ack = ack_cobalt_irq,
};
/*
* This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
* -- not the manner expected by the code in i8259.c.
*
* there is a 'master' physical interrupt source that gets sent to
* the CPU. But in the chipset there are various 'virtual' interrupts
* waiting to be handled. We represent this to Linux through a 'master'
* interrupt controller type, and through a special virtual interrupt-
* controller. Device drivers only see the virtual interrupt sources.
*/
static unsigned int startup_piix4_master_irq(struct irq_data *data)
{
legacy_pic->init(0);
enable_cobalt_irq(data);
return 0;
}
static struct irq_chip piix4_master_irq_type = {
.name = "PIIX4-master",
.irq_startup = startup_piix4_master_irq,
.irq_ack = ack_cobalt_irq,
};
static void pii4_mask(struct irq_data *data) { }
static struct irq_chip piix4_virtual_irq_type = {
.name = "PIIX4-virtual",
.irq_mask = pii4_mask,
};
/*
* PIIX4-8259 master/virtual functions to handle interrupt requests
* from legacy devices: floppy, parallel, serial, rtc.
*
* None of these get Cobalt APIC entries, neither do they have IDT
* entries. These interrupts are purely virtual and distributed from
* the 'master' interrupt source: CO_IRQ_8259.
*
* When the 8259 interrupts its handler figures out which of these
* devices is interrupting and dispatches to its handler.
*
* CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
* enable_irq gets the right irq. This 'master' irq is never directly
* manipulated by any driver.
*/
static irqreturn_t piix4_master_intr(int irq, void *dev_id)
{
unsigned long flags;
int realirq;
raw_spin_lock_irqsave(&i8259A_lock, flags);
/* Find out what's interrupting in the PIIX4 master 8259 */
outb(0x0c, 0x20); /* OCW3 Poll command */
realirq = inb(0x20);
/*
* Bit 7 == 0 means invalid/spurious
*/
if (unlikely(!(realirq & 0x80)))
goto out_unlock;
realirq &= 7;
if (unlikely(realirq == 2)) {
outb(0x0c, 0xa0);
realirq = inb(0xa0);
if (unlikely(!(realirq & 0x80)))
goto out_unlock;
realirq = (realirq & 7) + 8;
}
/* mask and ack interrupt */
cached_irq_mask |= 1 << realirq;
if (unlikely(realirq > 7)) {
inb(0xa1);
outb(cached_slave_mask, 0xa1);
outb(0x60 + (realirq & 7), 0xa0);
outb(0x60 + 2, 0x20);
} else {
inb(0x21);
outb(cached_master_mask, 0x21);
outb(0x60 + realirq, 0x20);
}
raw_spin_unlock_irqrestore(&i8259A_lock, flags);
/*
* handle this 'virtual interrupt' as a Cobalt one now.
*/
generic_handle_irq(realirq);
return IRQ_HANDLED;
out_unlock:
raw_spin_unlock_irqrestore(&i8259A_lock, flags);
return IRQ_NONE;
}
static struct irqaction master_action = {
.handler = piix4_master_intr,
.name = "PIIX4-8259",
.flags = IRQF_NO_THREAD,
};
static struct irqaction cascade_action = {
.handler = no_action,
.name = "cascade",
.flags = IRQF_NO_THREAD,
};
static inline void set_piix4_virtual_irq_type(void)
{
piix4_virtual_irq_type.irq_enable = i8259A_chip.irq_unmask;
piix4_virtual_irq_type.irq_disable = i8259A_chip.irq_mask;
piix4_virtual_irq_type.irq_unmask = i8259A_chip.irq_unmask;
}
static void __init visws_pre_intr_init(void)
{
int i;
set_piix4_virtual_irq_type();
for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
struct irq_chip *chip = NULL;
if (i == 0)
chip = &cobalt_irq_type;
else if (i == CO_IRQ_IDE0)
chip = &cobalt_irq_type;
else if (i == CO_IRQ_IDE1)
chip = &cobalt_irq_type;
else if (i == CO_IRQ_8259)
chip = &piix4_master_irq_type;
else if (i < CO_IRQ_APIC0)
chip = &piix4_virtual_irq_type;
else if (IS_CO_APIC(i))
chip = &cobalt_irq_type;
if (chip)
irq_set_chip(i, chip);
}
setup_irq(CO_IRQ_8259, &master_action);
setup_irq(2, &cascade_action);
}

2
arch/x86/xen/Kconfig
View File

@ -7,7 +7,7 @@ config XEN
depends on PARAVIRT
select PARAVIRT_CLOCK
select XEN_HAVE_PVMMU
depends on X86_64 || (X86_32 && X86_PAE && !X86_VISWS)
depends on X86_64 || (X86_32 && X86_PAE)
depends on X86_TSC
help
This is the Linux Xen port. Enabling this will allow the

1
drivers/pci/Makefile
View File

@ -42,7 +42,6 @@ obj-$(CONFIG_SUPERH) += setup-bus.o setup-irq.o
obj-$(CONFIG_PPC) += setup-bus.o
obj-$(CONFIG_FRV) += setup-bus.o
obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
obj-$(CONFIG_X86_VISWS) += setup-irq.o
obj-$(CONFIG_MN10300) += setup-bus.o
obj-$(CONFIG_MICROBLAZE) += setup-bus.o
obj-$(CONFIG_TILE) += setup-bus.o setup-irq.o

7
drivers/scsi/qla1280.c
View File

@ -379,14 +379,7 @@
#define DEBUG_PRINT_NVRAM 0
#define DEBUG_QLA1280 0
/*
* The SGI VISWS is broken and doesn't support MMIO ;-(
*/
#ifdef CONFIG_X86_VISWS
#define MEMORY_MAPPED_IO 0
#else
#define MEMORY_MAPPED_IO 1
#endif
#include "qla1280.h"

11
drivers/video/Kconfig
View File

@ -802,18 +802,9 @@ config FB_HGA
As this card technology is at least 25 years old,
most people will answer N here.
config FB_SGIVW
tristate "SGI Visual Workstation framebuffer support"
depends on FB && X86_VISWS
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
help
SGI Visual Workstation support for framebuffer graphics.
config FB_GBE
bool "SGI Graphics Backend frame buffer support"
depends on (FB = y) && (SGI_IP32 || X86_VISWS)
depends on (FB = y) && SGI_IP32
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT

1
drivers/video/Makefile
View File

@ -75,7 +75,6 @@ obj-$(CONFIG_FB_CG14) += cg14.o sbuslib.o
obj-$(CONFIG_FB_P9100) += p9100.o sbuslib.o
obj-$(CONFIG_FB_TCX) += tcx.o sbuslib.o
obj-$(CONFIG_FB_LEO) += leo.o sbuslib.o
obj-$(CONFIG_FB_SGIVW) += sgivwfb.o
obj-$(CONFIG_FB_ACORN) += acornfb.o
obj-$(CONFIG_FB_ATARI) += atafb.o c2p_iplan2.o atafb_mfb.o \
atafb_iplan2p2.o atafb_iplan2p4.o atafb_iplan2p8.o

4
drivers/video/gbefb.c
View File

@ -45,10 +45,6 @@ struct gbefb_par {
#define GBE_BASE 0x16000000 /* SGI O2 */
#endif
#ifdef CONFIG_X86_VISWS
#define GBE_BASE 0xd0000000 /* SGI Visual Workstation */
#endif
/* macro for fastest write-though access to the framebuffer */
#ifdef CONFIG_MIPS
#ifdef CONFIG_CPU_R10000

2
drivers/video/logo/Kconfig
View File

@ -54,7 +54,7 @@ config LOGO_PARISC_CLUT224
config LOGO_SGI_CLUT224
bool "224-color SGI Linux logo"
depends on SGI_IP22 || SGI_IP27 || SGI_IP32 || X86_VISWS
depends on SGI_IP22 || SGI_IP27 || SGI_IP32
default y
config LOGO_SUN_CLUT224

2
drivers/video/logo/logo.c
View File

@ -81,7 +81,7 @@ const struct linux_logo * __init_refok fb_find_logo(int depth)
logo = &logo_parisc_clut224;
#endif
#ifdef CONFIG_LOGO_SGI_CLUT224
/* SGI Linux logo on MIPS/MIPS64 and VISWS */
/* SGI Linux logo on MIPS/MIPS64 */
logo = &logo_sgi_clut224;
#endif
#ifdef CONFIG_LOGO_SUN_CLUT224

889
drivers/video/sgivwfb.c
View File

@ -1,889 +0,0 @@
/*
* linux/drivers/video/sgivwfb.c -- SGI DBE frame buffer device
*
* Copyright (C) 1999 Silicon Graphics, Inc.
* Jeffrey Newquist, newquist@engr.sgi.som
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/mtrr.h>
#include <asm/visws/sgivw.h>
#define INCLUDE_TIMING_TABLE_DATA
#define DBE_REG_BASE par->regs
#include <video/sgivw.h>
struct sgivw_par {
struct asregs *regs;
u32 cmap_fifo;
u_long timing_num;
};
#define FLATPANEL_SGI_1600SW 5
/*
* RAM we reserve for the frame buffer. This defines the maximum screen
* size
*
* The default can be overridden if the driver is compiled as a module
*/
static int ypan = 0;
static int ywrap = 0;
static int flatpanel_id = -1;
static struct fb_fix_screeninfo sgivwfb_fix = {
.id = "SGI Vis WS FB",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.mmio_start = DBE_REG_PHYS,
.mmio_len = DBE_REG_SIZE,
.accel = FB_ACCEL_NONE,
.line_length = 640,
};
static struct fb_var_screeninfo sgivwfb_var = {
/* 640x480, 8 bpp */
.xres = 640,
.yres = 480,
.xres_virtual = 640,
.yres_virtual = 480,
.bits_per_pixel = 8,
.red = { 0, 8, 0 },
.green = { 0, 8, 0 },
.blue = { 0, 8, 0 },
.height = -1,
.width = -1,
.pixclock = 20000,
.left_margin = 64,
.right_margin = 64,
.upper_margin = 32,
.lower_margin = 32,
.hsync_len = 64,
.vsync_len = 2,
.vmode = FB_VMODE_NONINTERLACED
};
static struct fb_var_screeninfo sgivwfb_var1600sw = {
/* 1600x1024, 8 bpp */
.xres = 1600,
.yres = 1024,
.xres_virtual = 1600,
.yres_virtual = 1024,
.bits_per_pixel = 8,
.red = { 0, 8, 0 },
.green = { 0, 8, 0 },
.blue = { 0, 8, 0 },
.height = -1,
.width = -1,
.pixclock = 9353,
.left_margin = 20,
.right_margin = 30,
.upper_margin = 37,
.lower_margin = 3,
.hsync_len = 20,
.vsync_len = 3,
.vmode = FB_VMODE_NONINTERLACED
};
/*
* Interface used by the world
*/
int sgivwfb_init(void);
static int sgivwfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
static int sgivwfb_set_par(struct fb_info *info);
static int sgivwfb_setcolreg(u_int regno, u_int red, u_int green,
u_int blue, u_int transp,
struct fb_info *info);
static int sgivwfb_mmap(struct fb_info *info,
struct vm_area_struct *vma);
static struct fb_ops sgivwfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = sgivwfb_check_var,
.fb_set_par = sgivwfb_set_par,
.fb_setcolreg = sgivwfb_setcolreg,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_mmap = sgivwfb_mmap,
};
/*
* Internal routines
*/
static unsigned long bytes_per_pixel(int bpp)
{
switch (bpp) {
case 8:
return 1;
case 16:
return 2;
case 32:
return 4;
default:
printk(KERN_INFO "sgivwfb: unsupported bpp %d\n", bpp);
return 0;
}
}
static unsigned long get_line_length(int xres_virtual, int bpp)
{
return (xres_virtual * bytes_per_pixel(bpp));
}
/*
* Function: dbe_TurnOffDma
* Parameters: (None)
* Description: This should turn off the monitor and dbe. This is used
* when switching between the serial console and the graphics
* console.
*/
static void dbe_TurnOffDma(struct sgivw_par *par)
{
unsigned int readVal;
int i;
// Check to see if things are already turned off:
// 1) Check to see if dbe is not using the internal dotclock.
// 2) Check to see if the xy counter in dbe is already off.
DBE_GETREG(ctrlstat, readVal);
if (GET_DBE_FIELD(CTRLSTAT, PCLKSEL, readVal) < 2)
return;
DBE_GETREG(vt_xy, readVal);
if (GET_DBE_FIELD(VT_XY, VT_FREEZE, readVal) == 1)
return;
// Otherwise, turn off dbe
DBE_GETREG(ovr_control, readVal);
SET_DBE_FIELD(OVR_CONTROL, OVR_DMA_ENABLE, readVal, 0);
DBE_SETREG(ovr_control, readVal);
udelay(1000);
DBE_GETREG(frm_control, readVal);
SET_DBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, readVal, 0);
DBE_SETREG(frm_control, readVal);
udelay(1000);
DBE_GETREG(did_control, readVal);
SET_DBE_FIELD(DID_CONTROL, DID_DMA_ENABLE, readVal, 0);
DBE_SETREG(did_control, readVal);
udelay(1000);
// XXX HACK:
//
// This was necessary for GBE--we had to wait through two
// vertical retrace periods before the pixel DMA was
// turned off for sure. I've left this in for now, in
// case dbe needs it.
for (i = 0; i < 10000; i++) {
DBE_GETREG(frm_inhwctrl, readVal);
if (GET_DBE_FIELD(FRM_INHWCTRL, FRM_DMA_ENABLE, readVal) ==
0)
udelay(10);
else {
DBE_GETREG(ovr_inhwctrl, readVal);
if (GET_DBE_FIELD
(OVR_INHWCTRL, OVR_DMA_ENABLE, readVal) == 0)
udelay(10);
else {
DBE_GETREG(did_inhwctrl, readVal);
if (GET_DBE_FIELD
(DID_INHWCTRL, DID_DMA_ENABLE,
readVal) == 0)
udelay(10);
else
break;
}
}
}
}
/*
* Set the User Defined Part of the Display. Again if par use it to get
* real video mode.
*/
static int sgivwfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct sgivw_par *par = (struct sgivw_par *)info->par;
struct dbe_timing_info *timing;
u_long line_length;
u_long min_mode;
int req_dot;
int test_mode;
/*
* FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
* as FB_VMODE_SMOOTH_XPAN is only used internally
*/
if (var->vmode & FB_VMODE_CONUPDATE) {
var->vmode |= FB_VMODE_YWRAP;
var->xoffset = info->var.xoffset;
var->yoffset = info->var.yoffset;
}
/* XXX FIXME - forcing var's */
var->xoffset = 0;
var->yoffset = 0;
/* Limit bpp to 8, 16, and 32 */
if (var->bits_per_pixel <= 8)
var->bits_per_pixel = 8;
else if (var->bits_per_pixel <= 16)
var->bits_per_pixel = 16;
else if (var->bits_per_pixel <= 32)
var->bits_per_pixel = 32;
else
return -EINVAL;
var->grayscale = 0; /* No grayscale for now */
/* determine valid resolution and timing */
for (min_mode = 0; min_mode < ARRAY_SIZE(dbeVTimings); min_mode++) {
if (dbeVTimings[min_mode].width >= var->xres &&
dbeVTimings[min_mode].height >= var->yres)
break;
}
if (min_mode == ARRAY_SIZE(dbeVTimings))
return -EINVAL; /* Resolution to high */
/* XXX FIXME - should try to pick best refresh rate */
/* for now, pick closest dot-clock within 3MHz */
req_dot = PICOS2KHZ(var->pixclock);
printk(KERN_INFO "sgivwfb: requested pixclock=%d ps (%d KHz)\n",
var->pixclock, req_dot);
test_mode = min_mode;
while (dbeVTimings[min_mode].width == dbeVTimings[test_mode].width) {
if (dbeVTimings[test_mode].cfreq + 3000 > req_dot)
break;
test_mode++;
}
if (dbeVTimings[min_mode].width != dbeVTimings[test_mode].width)
test_mode--;
min_mode = test_mode;
timing = &dbeVTimings[min_mode];
printk(KERN_INFO "sgivwfb: granted dot-clock=%d KHz\n", timing->cfreq);
/* Adjust virtual resolution, if necessary */
if (var->xres > var->xres_virtual || (!ywrap && !ypan))
var->xres_virtual = var->xres;
if (var->yres > var->yres_virtual || (!ywrap && !ypan))
var->yres_virtual = var->yres;
/*
* Memory limit
*/
line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
if (line_length * var->yres_virtual > sgivwfb_mem_size)
return -ENOMEM; /* Virtual resolution to high */
info->fix.line_length = line_length;
switch (var->bits_per_pixel) {
case 8:
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 16: /* RGBA 5551 */
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 6;
var->green.length = 5;
var->blue.offset = 1;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 32: /* RGB 8888 */
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 16;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
break;
}
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
/* set video timing information */
var->pixclock = KHZ2PICOS(timing->cfreq);
var->left_margin = timing->htotal - timing->hsync_end;
var->right_margin = timing->hsync_start - timing->width;
var->upper_margin = timing->vtotal - timing->vsync_end;
var->lower_margin = timing->vsync_start - timing->height;
var->hsync_len = timing->hsync_end - timing->hsync_start;
var->vsync_len = timing->vsync_end - timing->vsync_start;
/* Ouch. This breaks the rules but timing_num is only important if you
* change a video mode */
par->timing_num = min_mode;
printk(KERN_INFO "sgivwfb: new video mode xres=%d yres=%d bpp=%d\n",
var->xres, var->yres, var->bits_per_pixel);
printk(KERN_INFO " vxres=%d vyres=%d\n", var->xres_virtual,
var->yres_virtual);
return 0;
}
/*
* Setup flatpanel related registers.
*/
static void sgivwfb_setup_flatpanel(struct sgivw_par *par, struct dbe_timing_info *currentTiming)
{
int fp_wid, fp_hgt, fp_vbs, fp_vbe;
u32 outputVal = 0;
SET_DBE_FIELD(VT_FLAGS, HDRV_INVERT, outputVal,
(currentTiming->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1);
SET_DBE_FIELD(VT_FLAGS, VDRV_INVERT, outputVal,
(currentTiming->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1);
DBE_SETREG(vt_flags, outputVal);
/* Turn on the flat panel */
switch (flatpanel_id) {
case FLATPANEL_SGI_1600SW:
fp_wid = 1600;
fp_hgt = 1024;
fp_vbs = 0;
fp_vbe = 1600;
currentTiming->pll_m = 4;
currentTiming->pll_n = 1;
currentTiming->pll_p = 0;
break;
default:
fp_wid = fp_hgt = fp_vbs = fp_vbe = 0xfff;
}
outputVal = 0;
SET_DBE_FIELD(FP_DE, FP_DE_ON, outputVal, fp_vbs);
SET_DBE_FIELD(FP_DE, FP_DE_OFF, outputVal, fp_vbe);
DBE_SETREG(fp_de, outputVal);
outputVal = 0;
SET_DBE_FIELD(FP_HDRV, FP_HDRV_OFF, outputVal, fp_wid);
DBE_SETREG(fp_hdrv, outputVal);
outputVal = 0;
SET_DBE_FIELD(FP_VDRV, FP_VDRV_ON, outputVal, 1);
SET_DBE_FIELD(FP_VDRV, FP_VDRV_OFF, outputVal, fp_hgt + 1);
DBE_SETREG(fp_vdrv, outputVal);
}
/*
* Set the hardware according to 'par'.
*/
static int sgivwfb_set_par(struct fb_info *info)
{
struct sgivw_par *par = info->par;
int i, j, htmp, temp;
u32 readVal, outputVal;
int wholeTilesX, maxPixelsPerTileX;
int frmWrite1, frmWrite2, frmWrite3b;
struct dbe_timing_info *currentTiming; /* Current Video Timing */
int xpmax, ypmax; // Monitor resolution
int bytesPerPixel; // Bytes per pixel
currentTiming = &dbeVTimings[par->timing_num];
bytesPerPixel = bytes_per_pixel(info->var.bits_per_pixel);
xpmax = currentTiming->width;
ypmax = currentTiming->height;
/* dbe_InitGraphicsBase(); */
/* Turn on dotclock PLL */
DBE_SETREG(ctrlstat, 0x20000000);
dbe_TurnOffDma(par);
/* dbe_CalculateScreenParams(); */
maxPixelsPerTileX = 512 / bytesPerPixel;
wholeTilesX = xpmax / maxPixelsPerTileX;
if (wholeTilesX * maxPixelsPerTileX < xpmax)
wholeTilesX++;
printk(KERN_DEBUG "sgivwfb: pixPerTile=%d wholeTilesX=%d\n",
maxPixelsPerTileX, wholeTilesX);
/* dbe_InitGammaMap(); */
udelay(10);
for (i = 0; i < 256; i++) {
DBE_ISETREG(gmap, i, (i << 24) | (i << 16) | (i << 8));
}
/* dbe_TurnOn(); */
DBE_GETREG(vt_xy, readVal);
if (GET_DBE_FIELD(VT_XY, VT_FREEZE, readVal) == 1) {
DBE_SETREG(vt_xy, 0x00000000);
udelay(1);
} else
dbe_TurnOffDma(par);
/* dbe_Initdbe(); */
for (i = 0; i < 256; i++) {
for (j = 0; j < 100; j++) {
DBE_GETREG(cm_fifo, readVal);
if (readVal != 0x00000000)
break;
else
udelay(10);
}
// DBE_ISETREG(cmap, i, 0x00000000);
DBE_ISETREG(cmap, i, (i << 8) | (i << 16) | (i << 24));
}
/* dbe_InitFramebuffer(); */
frmWrite1 = 0;
SET_DBE_FIELD(FRM_SIZE_TILE, FRM_WIDTH_TILE, frmWrite1,
wholeTilesX);
SET_DBE_FIELD(FRM_SIZE_TILE, FRM_RHS, frmWrite1, 0);
switch (bytesPerPixel) {
case 1:
SET_DBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, frmWrite1,
DBE_FRM_DEPTH_8);
break;
case 2:
SET_DBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, frmWrite1,
DBE_FRM_DEPTH_16);
break;
case 4:
SET_DBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, frmWrite1,
DBE_FRM_DEPTH_32);
break;
}
frmWrite2 = 0;
SET_DBE_FIELD(FRM_SIZE_PIXEL, FB_HEIGHT_PIX, frmWrite2, ypmax);
// Tell dbe about the framebuffer location and type
// XXX What format is the FRM_TILE_PTR?? 64K aligned address?
frmWrite3b = 0;
SET_DBE_FIELD(FRM_CONTROL, FRM_TILE_PTR, frmWrite3b,
sgivwfb_mem_phys >> 9);
SET_DBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, frmWrite3b, 1);
SET_DBE_FIELD(FRM_CONTROL, FRM_LINEAR, frmWrite3b, 1);
/* Initialize DIDs */
outputVal = 0;
switch (bytesPerPixel) {
case 1:
SET_DBE_FIELD(WID, TYP, outputVal, DBE_CMODE_I8);
break;
case 2:
SET_DBE_FIELD(WID, TYP, outputVal, DBE_CMODE_RGBA5);
break;
case 4:
SET_DBE_FIELD(WID, TYP, outputVal, DBE_CMODE_RGB8);
break;
}
SET_DBE_FIELD(WID, BUF, outputVal, DBE_BMODE_BOTH);
for (i = 0; i < 32; i++) {
DBE_ISETREG(mode_regs, i, outputVal);
}
/* dbe_InitTiming(); */
DBE_SETREG(vt_intr01, 0xffffffff);
DBE_SETREG(vt_intr23, 0xffffffff);
DBE_GETREG(dotclock, readVal);
DBE_SETREG(dotclock, readVal & 0xffff);
DBE_SETREG(vt_xymax, 0x00000000);
outputVal = 0;
SET_DBE_FIELD(VT_VSYNC, VT_VSYNC_ON, outputVal,
currentTiming->vsync_start);
SET_DBE_FIELD(VT_VSYNC, VT_VSYNC_OFF, outputVal,
currentTiming->vsync_end);
DBE_SETREG(vt_vsync, outputVal);
outputVal = 0;
SET_DBE_FIELD(VT_HSYNC, VT_HSYNC_ON, outputVal,
currentTiming->hsync_start);
SET_DBE_FIELD(VT_HSYNC, VT_HSYNC_OFF, outputVal,
currentTiming->hsync_end);
DBE_SETREG(vt_hsync, outputVal);
outputVal = 0;
SET_DBE_FIELD(VT_VBLANK, VT_VBLANK_ON, outputVal,
currentTiming->vblank_start);
SET_DBE_FIELD(VT_VBLANK, VT_VBLANK_OFF, outputVal,
currentTiming->vblank_end);
DBE_SETREG(vt_vblank, outputVal);
outputVal = 0;
SET_DBE_FIELD(VT_HBLANK, VT_HBLANK_ON, outputVal,
currentTiming->hblank_start);
SET_DBE_FIELD(VT_HBLANK, VT_HBLANK_OFF, outputVal,
currentTiming->hblank_end - 3);
DBE_SETREG(vt_hblank, outputVal);
outputVal = 0;
SET_DBE_FIELD(VT_VCMAP, VT_VCMAP_ON, outputVal,
currentTiming->vblank_start);
SET_DBE_FIELD(VT_VCMAP, VT_VCMAP_OFF, outputVal,
currentTiming->vblank_end);
DBE_SETREG(vt_vcmap, outputVal);
outputVal = 0;
SET_DBE_FIELD(VT_HCMAP, VT_HCMAP_ON, outputVal,
currentTiming->hblank_start);
SET_DBE_FIELD(VT_HCMAP, VT_HCMAP_OFF, outputVal,
currentTiming->hblank_end - 3);
DBE_SETREG(vt_hcmap, outputVal);
if (flatpanel_id != -1)
sgivwfb_setup_flatpanel(par, currentTiming);
outputVal = 0;
temp = currentTiming->vblank_start - currentTiming->vblank_end - 1;
if (temp > 0)
temp = -temp;
SET_DBE_FIELD(DID_START_XY, DID_STARTY, outputVal, (u32) temp);
if (currentTiming->hblank_end >= 20)
SET_DBE_FIELD(DID_START_XY, DID_STARTX, outputVal,
currentTiming->hblank_end - 20);
else
SET_DBE_FIELD(DID_START_XY, DID_STARTX, outputVal,
currentTiming->htotal - (20 -
currentTiming->
hblank_end));
DBE_SETREG(did_start_xy, outputVal);
outputVal = 0;
SET_DBE_FIELD(CRS_START_XY, CRS_STARTY, outputVal,
(u32) (temp + 1));
if (currentTiming->hblank_end >= DBE_CRS_MAGIC)
SET_DBE_FIELD(CRS_START_XY, CRS_STARTX, outputVal,
currentTiming->hblank_end - DBE_CRS_MAGIC);
else
SET_DBE_FIELD(CRS_START_XY, CRS_STARTX, outputVal,
currentTiming->htotal - (DBE_CRS_MAGIC -
currentTiming->
hblank_end));
DBE_SETREG(crs_start_xy, outputVal);
outputVal = 0;
SET_DBE_FIELD(VC_START_XY, VC_STARTY, outputVal, (u32) temp);
SET_DBE_FIELD(VC_START_XY, VC_STARTX, outputVal,
currentTiming->hblank_end - 4);
DBE_SETREG(vc_start_xy, outputVal);
DBE_SETREG(frm_size_tile, frmWrite1);
DBE_SETREG(frm_size_pixel, frmWrite2);
outputVal = 0;
SET_DBE_FIELD(DOTCLK, M, outputVal, currentTiming->pll_m - 1);
SET_DBE_FIELD(DOTCLK, N, outputVal, currentTiming->pll_n - 1);
SET_DBE_FIELD(DOTCLK, P, outputVal, currentTiming->pll_p);
SET_DBE_FIELD(DOTCLK, RUN, outputVal, 1);
DBE_SETREG(dotclock, outputVal);
udelay(11 * 1000);
DBE_SETREG(vt_vpixen, 0xffffff);
DBE_SETREG(vt_hpixen, 0xffffff);
outputVal = 0;
SET_DBE_FIELD(VT_XYMAX, VT_MAXX, outputVal, currentTiming->htotal);
SET_DBE_FIELD(VT_XYMAX, VT_MAXY, outputVal, currentTiming->vtotal);
DBE_SETREG(vt_xymax, outputVal);
outputVal = frmWrite1;
SET_DBE_FIELD(FRM_SIZE_TILE, FRM_FIFO_RESET, outputVal, 1);
DBE_SETREG(frm_size_tile, outputVal);
DBE_SETREG(frm_size_tile, frmWrite1);
outputVal = 0;
SET_DBE_FIELD(OVR_WIDTH_TILE, OVR_FIFO_RESET, outputVal, 1);
DBE_SETREG(ovr_width_tile, outputVal);
DBE_SETREG(ovr_width_tile, 0);
DBE_SETREG(frm_control, frmWrite3b);
DBE_SETREG(did_control, 0);
// Wait for dbe to take frame settings
for (i = 0; i < 100000; i++) {
DBE_GETREG(frm_inhwctrl, readVal);
if (GET_DBE_FIELD(FRM_INHWCTRL, FRM_DMA_ENABLE, readVal) !=
0)
break;
else
udelay(1);
}
if (i == 100000)
printk(KERN_INFO
"sgivwfb: timeout waiting for frame DMA enable.\n");
outputVal = 0;
htmp = currentTiming->hblank_end - 19;
if (htmp < 0)
htmp += currentTiming->htotal; /* allow blank to wrap around */
SET_DBE_FIELD(VT_HPIXEN, VT_HPIXEN_ON, outputVal, htmp);
SET_DBE_FIELD(VT_HPIXEN, VT_HPIXEN_OFF, outputVal,
((htmp + currentTiming->width -
2) % currentTiming->htotal));
DBE_SETREG(vt_hpixen, outputVal);
outputVal = 0;
SET_DBE_FIELD(VT_VPIXEN, VT_VPIXEN_OFF, outputVal,
currentTiming->vblank_start);
SET_DBE_FIELD(VT_VPIXEN, VT_VPIXEN_ON, outputVal,
currentTiming->vblank_end);
DBE_SETREG(vt_vpixen, outputVal);
// Turn off mouse cursor
par->regs->crs_ctl = 0;
// XXX What's this section for??
DBE_GETREG(ctrlstat, readVal);
readVal &= 0x02000000;
if (readVal != 0) {
DBE_SETREG(ctrlstat, 0x30000000);
}
return 0;
}
/*
* Set a single color register. The values supplied are already
* rounded down to the hardware's capabilities (according to the
* entries in the var structure). Return != 0 for invalid regno.
*/
static int sgivwfb_setcolreg(u_int regno, u_int red, u_int green,
u_int blue, u_int transp,
struct fb_info *info)
{
struct sgivw_par *par = (struct sgivw_par *) info->par;
if (regno > 255)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
/* wait for the color map FIFO to have a free entry */
while (par->cmap_fifo == 0)
par->cmap_fifo = par->regs->cm_fifo;
par->regs->cmap[regno] = (red << 24) | (green << 16) | (blue << 8);
par->cmap_fifo--; /* assume FIFO is filling up */
return 0;
}
static int sgivwfb_mmap(struct fb_info *info,
struct vm_area_struct *vma)
{
int r;
pgprot_val(vma->vm_page_prot) =
pgprot_val(vma->vm_page_prot) | _PAGE_PCD;
r = vm_iomap_memory(vma, sgivwfb_mem_phys, sgivwfb_mem_size);
printk(KERN_DEBUG "sgivwfb: mmap framebuffer P(%lx)->V(%lx)\n",
sgivwfb_mem_phys + (vma->vm_pgoff << PAGE_SHIFT), vma->vm_start);
return r;
}
int __init sgivwfb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "monitor:", 8)) {
if (!strncmp(this_opt + 8, "crt", 3))
flatpanel_id = -1;
else if (!strncmp(this_opt + 8, "1600sw", 6))
flatpanel_id = FLATPANEL_SGI_1600SW;
}
}
return 0;
}
/*
* Initialisation
*/
static int sgivwfb_probe(struct platform_device *dev)
{
struct sgivw_par *par;
struct fb_info *info;
char *monitor;
info = framebuffer_alloc(sizeof(struct sgivw_par) + sizeof(u32) * 16, &dev->dev);
if (!info)
return -ENOMEM;
par = info->par;
if (!request_mem_region(DBE_REG_PHYS, DBE_REG_SIZE, "sgivwfb")) {
printk(KERN_ERR "sgivwfb: couldn't reserve mmio region\n");
framebuffer_release(info);
return -EBUSY;
}
par->regs = (struct asregs *) ioremap_nocache(DBE_REG_PHYS, DBE_REG_SIZE);
if (!par->regs) {
printk(KERN_ERR "sgivwfb: couldn't ioremap registers\n");
goto fail_ioremap_regs;
}
mtrr_add(sgivwfb_mem_phys, sgivwfb_mem_size, MTRR_TYPE_WRCOMB, 1);
sgivwfb_fix.smem_start = sgivwfb_mem_phys;
sgivwfb_fix.smem_len = sgivwfb_mem_size;
sgivwfb_fix.ywrapstep = ywrap;
sgivwfb_fix.ypanstep = ypan;
info->fix = sgivwfb_fix;
switch (flatpanel_id) {
case FLATPANEL_SGI_1600SW:
info->var = sgivwfb_var1600sw;
monitor = "SGI 1600SW flatpanel";
break;
default:
info->var = sgivwfb_var;
monitor = "CRT";
}
printk(KERN_INFO "sgivwfb: %s monitor selected\n", monitor);
info->fbops = &sgivwfb_ops;
info->pseudo_palette = (void *) (par + 1);
info->flags = FBINFO_DEFAULT;
info->screen_base = ioremap_nocache((unsigned long) sgivwfb_mem_phys, sgivwfb_mem_size);
if (!info->screen_base) {
printk(KERN_ERR "sgivwfb: couldn't ioremap screen_base\n");
goto fail_ioremap_fbmem;
}
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
goto fail_color_map;
if (register_framebuffer(info) < 0) {
printk(KERN_ERR "sgivwfb: couldn't register framebuffer\n");
goto fail_register_framebuffer;
}
platform_set_drvdata(dev, info);
fb_info(info, "SGI DBE frame buffer device, using %ldK of video memory at %#lx\n",
sgivwfb_mem_size >> 10, sgivwfb_mem_phys);
return 0;
fail_register_framebuffer:
fb_dealloc_cmap(&info->cmap);
fail_color_map:
iounmap((char *) info->screen_base);
fail_ioremap_fbmem:
iounmap(par->regs);
fail_ioremap_regs:
release_mem_region(DBE_REG_PHYS, DBE_REG_SIZE);
framebuffer_release(info);
return -ENXIO;
}
static int sgivwfb_remove(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
if (info) {
struct sgivw_par *par = info->par;
unregister_framebuffer(info);
dbe_TurnOffDma(par);
iounmap(par->regs);
iounmap(info->screen_base);
release_mem_region(DBE_REG_PHYS, DBE_REG_SIZE);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
return 0;
}
static struct platform_driver sgivwfb_driver = {
.probe = sgivwfb_probe,
.remove = sgivwfb_remove,
.driver = {
.name = "sgivwfb",
},
};
static struct platform_device *sgivwfb_device;
int __init sgivwfb_init(void)
{
int ret;
#ifndef MODULE
char *option = NULL;
if (fb_get_options("sgivwfb", &option))
return -ENODEV;
sgivwfb_setup(option);
#endif
ret = platform_driver_register(&sgivwfb_driver);
if (!ret) {
sgivwfb_device = platform_device_alloc("sgivwfb", 0);
if (sgivwfb_device) {
ret = platform_device_add(sgivwfb_device);
} else
ret = -ENOMEM;
if (ret) {
platform_driver_unregister(&sgivwfb_driver);
platform_device_put(sgivwfb_device);
}
}
return ret;
}
module_init(sgivwfb_init);
#ifdef MODULE
MODULE_LICENSE("GPL");
static void __exit sgivwfb_exit(void)
{
platform_device_unregister(sgivwfb_device);
platform_driver_unregister(&sgivwfb_driver);
}
module_exit(sgivwfb_exit);
#endif /* MODULE */

681
include/video/sgivw.h
View File

@ -1,681 +0,0 @@
/*
* linux/drivers/video/sgivw.h -- SGI DBE frame buffer device header
*
* Copyright (C) 1999 Silicon Graphics, Inc.
* Jeffrey Newquist, newquist@engr.sgi.som
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#ifndef __SGIVWFB_H__
#define __SGIVWFB_H__
#define DBE_GETREG(reg, dest) ((dest) = DBE_REG_BASE->reg)
#define DBE_SETREG(reg, src) DBE_REG_BASE->reg = (src)
#define DBE_IGETREG(reg, idx, dest) ((dest) = DBE_REG_BASE->reg[idx])
#define DBE_ISETREG(reg, idx, src) (DBE_REG_BASE->reg[idx] = (src))
#define MASK(msb, lsb) ( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) )
#define GET(v, msb, lsb) ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) )
#define SET(v, f, msb, lsb) ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) )
#define GET_DBE_FIELD(reg, field, v) GET((v), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB)
#define SET_DBE_FIELD(reg, field, v, f) SET((v), (f), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB)
/* NOTE: All loads/stores must be 32 bits and uncached */
#define DBE_REG_PHYS 0xd0000000
#define DBE_REG_SIZE 0x01000000
struct asregs {
volatile u32 ctrlstat; /* 0x000000 general control */
volatile u32 dotclock; /* 0x000004 dot clock PLL control */
volatile u32 i2c; /* 0x000008 crt I2C control */
volatile u32 sysclk; /* 0x00000c system clock PLL control */
volatile u32 i2cfp; /* 0x000010 flat panel I2C control */
volatile u32 id; /* 0x000014 device id/chip revision */
volatile u32 config; /* 0x000018 power on configuration */
volatile u32 bist; /* 0x00001c internal bist status */
char _pad0[ 0x010000 - 0x000020 ];
volatile u32 vt_xy; /* 0x010000 current dot coords */
volatile u32 vt_xymax; /* 0x010004 maximum dot coords */
volatile u32 vt_vsync; /* 0x010008 vsync on/off */
volatile u32 vt_hsync; /* 0x01000c hsync on/off */
volatile u32 vt_vblank; /* 0x010010 vblank on/off */
volatile u32 vt_hblank; /* 0x010014 hblank on/off */
volatile u32 vt_flags; /* 0x010018 polarity of vt signals */
volatile u32 vt_f2rf_lock; /* 0x01001c f2rf & framelck y coord */
volatile u32 vt_intr01; /* 0x010020 intr 0,1 y coords */
volatile u32 vt_intr23; /* 0x010024 intr 2,3 y coords */
volatile u32 fp_hdrv; /* 0x010028 flat panel hdrv on/off */
volatile u32 fp_vdrv; /* 0x01002c flat panel vdrv on/off */
volatile u32 fp_de; /* 0x010030 flat panel de on/off */
volatile u32 vt_hpixen; /* 0x010034 intrnl horiz pixel on/off*/
volatile u32 vt_vpixen; /* 0x010038 intrnl vert pixel on/off */
volatile u32 vt_hcmap; /* 0x01003c cmap write (horiz) */
volatile u32 vt_vcmap; /* 0x010040 cmap write (vert) */
volatile u32 did_start_xy; /* 0x010044 eol/f did/xy reset val */
volatile u32 crs_start_xy; /* 0x010048 eol/f crs/xy reset val */
volatile u32 vc_start_xy; /* 0x01004c eol/f vc/xy reset val */
char _pad1[ 0x020000 - 0x010050 ];
volatile u32 ovr_width_tile; /* 0x020000 overlay plane ctrl 0 */
volatile u32 ovr_inhwctrl; /* 0x020004 overlay plane ctrl 1 */
volatile u32 ovr_control; /* 0x020008 overlay plane ctrl 1 */
char _pad2[ 0x030000 - 0x02000C ];
volatile u32 frm_size_tile; /* 0x030000 normal plane ctrl 0 */
volatile u32 frm_size_pixel; /* 0x030004 normal plane ctrl 1 */
volatile u32 frm_inhwctrl; /* 0x030008 normal plane ctrl 2 */
volatile u32 frm_control; /* 0x03000C normal plane ctrl 3 */
char _pad3[ 0x040000 - 0x030010 ];
volatile u32 did_inhwctrl; /* 0x040000 DID control */
volatile u32 did_control; /* 0x040004 DID shadow */
char _pad4[ 0x048000 - 0x040008 ];
volatile u32 mode_regs[32]; /* 0x048000 - 0x04807c WID table */
char _pad5[ 0x050000 - 0x048080 ];
volatile u32 cmap[6144]; /* 0x050000 - 0x055ffc color map */
char _pad6[ 0x058000 - 0x056000 ];
volatile u32 cm_fifo; /* 0x058000 color map fifo status */
char _pad7[ 0x060000 - 0x058004 ];
volatile u32 gmap[256]; /* 0x060000 - 0x0603fc gamma map */
char _pad8[ 0x068000 - 0x060400 ];
volatile u32 gmap10[1024]; /* 0x068000 - 0x068ffc gamma map */
char _pad9[ 0x070000 - 0x069000 ];
volatile u32 crs_pos; /* 0x070000 cusror control 0 */
volatile u32 crs_ctl; /* 0x070004 cusror control 1 */
volatile u32 crs_cmap[3]; /* 0x070008 - 0x070010 crs cmap */
char _pad10[ 0x078000 - 0x070014 ];
volatile u32 crs_glyph[64]; /* 0x078000 - 0x0780fc crs glyph */
char _pad11[ 0x080000 - 0x078100 ];
volatile u32 vc_0; /* 0x080000 video capture crtl 0 */
volatile u32 vc_1; /* 0x080004 video capture crtl 1 */
volatile u32 vc_2; /* 0x080008 video capture crtl 2 */
volatile u32 vc_3; /* 0x08000c video capture crtl 3 */
volatile u32 vc_4; /* 0x080010 video capture crtl 3 */
volatile u32 vc_5; /* 0x080014 video capture crtl 3 */
volatile u32 vc_6; /* 0x080018 video capture crtl 3 */
volatile u32 vc_7; /* 0x08001c video capture crtl 3 */
volatile u32 vc_8; /* 0x08000c video capture crtl 3 */
};
/* Bit mask information */
#define DBE_CTRLSTAT_CHIPID_MSB 3
#define DBE_CTRLSTAT_CHIPID_LSB 0
#define DBE_CTRLSTAT_SENSE_N_MSB 4
#define DBE_CTRLSTAT_SENSE_N_LSB 4
#define DBE_CTRLSTAT_PCLKSEL_MSB 29
#define DBE_CTRLSTAT_PCLKSEL_LSB 28
#define DBE_DOTCLK_M_MSB 7
#define DBE_DOTCLK_M_LSB 0
#define DBE_DOTCLK_N_MSB 13
#define DBE_DOTCLK_N_LSB 8
#define DBE_DOTCLK_P_MSB 15
#define DBE_DOTCLK_P_LSB 14
#define DBE_DOTCLK_RUN_MSB 20
#define DBE_DOTCLK_RUN_LSB 20
#define DBE_VT_XY_VT_FREEZE_MSB 31
#define DBE_VT_XY_VT_FREEZE_LSB 31
#define DBE_FP_VDRV_FP_VDRV_ON_MSB 23
#define DBE_FP_VDRV_FP_VDRV_ON_LSB 12
#define DBE_FP_VDRV_FP_VDRV_OFF_MSB 11
#define DBE_FP_VDRV_FP_VDRV_OFF_LSB 0
#define DBE_FP_HDRV_FP_HDRV_ON_MSB 23
#define DBE_FP_HDRV_FP_HDRV_ON_LSB 12
#define DBE_FP_HDRV_FP_HDRV_OFF_MSB 11
#define DBE_FP_HDRV_FP_HDRV_OFF_LSB 0
#define DBE_FP_DE_FP_DE_ON_MSB 23
#define DBE_FP_DE_FP_DE_ON_LSB 12
#define DBE_FP_DE_FP_DE_OFF_MSB 11
#define DBE_FP_DE_FP_DE_OFF_LSB 0
#define DBE_VT_VSYNC_VT_VSYNC_ON_MSB 23
#define DBE_VT_VSYNC_VT_VSYNC_ON_LSB 12
#define DBE_VT_VSYNC_VT_VSYNC_OFF_MSB 11
#define DBE_VT_VSYNC_VT_VSYNC_OFF_LSB 0
#define DBE_VT_HSYNC_VT_HSYNC_ON_MSB 23
#define DBE_VT_HSYNC_VT_HSYNC_ON_LSB 12
#define DBE_VT_HSYNC_VT_HSYNC_OFF_MSB 11
#define DBE_VT_HSYNC_VT_HSYNC_OFF_LSB 0
#define DBE_VT_VBLANK_VT_VBLANK_ON_MSB 23
#define DBE_VT_VBLANK_VT_VBLANK_ON_LSB 12
#define DBE_VT_VBLANK_VT_VBLANK_OFF_MSB 11
#define DBE_VT_VBLANK_VT_VBLANK_OFF_LSB 0
#define DBE_VT_HBLANK_VT_HBLANK_ON_MSB 23
#define DBE_VT_HBLANK_VT_HBLANK_ON_LSB 12
#define DBE_VT_HBLANK_VT_HBLANK_OFF_MSB 11
#define DBE_VT_HBLANK_VT_HBLANK_OFF_LSB 0
#define DBE_VT_FLAGS_VDRV_INVERT_MSB 0
#define DBE_VT_FLAGS_VDRV_INVERT_LSB 0
#define DBE_VT_FLAGS_HDRV_INVERT_MSB 2
#define DBE_VT_FLAGS_HDRV_INVERT_LSB 2
#define DBE_VT_VCMAP_VT_VCMAP_ON_MSB 23
#define DBE_VT_VCMAP_VT_VCMAP_ON_LSB 12
#define DBE_VT_VCMAP_VT_VCMAP_OFF_MSB 11
#define DBE_VT_VCMAP_VT_VCMAP_OFF_LSB 0
#define DBE_VT_HCMAP_VT_HCMAP_ON_MSB 23
#define DBE_VT_HCMAP_VT_HCMAP_ON_LSB 12
#define DBE_VT_HCMAP_VT_HCMAP_OFF_MSB 11
#define DBE_VT_HCMAP_VT_HCMAP_OFF_LSB 0
#define DBE_VT_XYMAX_VT_MAXX_MSB 11
#define DBE_VT_XYMAX_VT_MAXX_LSB 0
#define DBE_VT_XYMAX_VT_MAXY_MSB 23
#define DBE_VT_XYMAX_VT_MAXY_LSB 12
#define DBE_VT_HPIXEN_VT_HPIXEN_ON_MSB 23
#define DBE_VT_HPIXEN_VT_HPIXEN_ON_LSB 12
#define DBE_VT_HPIXEN_VT_HPIXEN_OFF_MSB 11
#define DBE_VT_HPIXEN_VT_HPIXEN_OFF_LSB 0
#define DBE_VT_VPIXEN_VT_VPIXEN_ON_MSB 23
#define DBE_VT_VPIXEN_VT_VPIXEN_ON_LSB 12
#define DBE_VT_VPIXEN_VT_VPIXEN_OFF_MSB 11
#define DBE_VT_VPIXEN_VT_VPIXEN_OFF_LSB 0
#define DBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB 0
#define DBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB 0
#define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB 0
#define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB 0
#define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB 13
#define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB 13
#define DBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB 0
#define DBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB 0
#define DBE_FRM_CONTROL_FRM_TILE_PTR_MSB 31
#define DBE_FRM_CONTROL_FRM_TILE_PTR_LSB 9
#define DBE_FRM_CONTROL_FRM_LINEAR_MSB 1
#define DBE_FRM_CONTROL_FRM_LINEAR_LSB 1
#define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB 0
#define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB 0
#define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB 12
#define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB 5
#define DBE_FRM_SIZE_TILE_FRM_RHS_MSB 4
#define DBE_FRM_SIZE_TILE_FRM_RHS_LSB 0
#define DBE_FRM_SIZE_TILE_FRM_DEPTH_MSB 14
#define DBE_FRM_SIZE_TILE_FRM_DEPTH_LSB 13
#define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB 15
#define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB 15
#define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB 31
#define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB 16
#define DBE_DID_CONTROL_DID_DMA_ENABLE_MSB 0
#define DBE_DID_CONTROL_DID_DMA_ENABLE_LSB 0
#define DBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB 0
#define DBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB 0
#define DBE_DID_START_XY_DID_STARTY_MSB 23
#define DBE_DID_START_XY_DID_STARTY_LSB 12
#define DBE_DID_START_XY_DID_STARTX_MSB 11
#define DBE_DID_START_XY_DID_STARTX_LSB 0
#define DBE_CRS_START_XY_CRS_STARTY_MSB 23
#define DBE_CRS_START_XY_CRS_STARTY_LSB 12
#define DBE_CRS_START_XY_CRS_STARTX_MSB 11
#define DBE_CRS_START_XY_CRS_STARTX_LSB 0
#define DBE_WID_TYP_MSB 4
#define DBE_WID_TYP_LSB 2
#define DBE_WID_BUF_MSB 1
#define DBE_WID_BUF_LSB 0
#define DBE_VC_START_XY_VC_STARTY_MSB 23
#define DBE_VC_START_XY_VC_STARTY_LSB 12
#define DBE_VC_START_XY_VC_STARTX_MSB 11
#define DBE_VC_START_XY_VC_STARTX_LSB 0
/* Constants */
#define DBE_FRM_DEPTH_8 0
#define DBE_FRM_DEPTH_16 1
#define DBE_FRM_DEPTH_32 2
#define DBE_CMODE_I8 0
#define DBE_CMODE_I12 1
#define DBE_CMODE_RG3B2 2
#define DBE_CMODE_RGB4 3
#define DBE_CMODE_ARGB5 4
#define DBE_CMODE_RGB8 5
#define DBE_CMODE_RGBA5 6
#define DBE_CMODE_RGB10 7
#define DBE_BMODE_BOTH 3
#define DBE_CRS_MAGIC 54
#define DBE_CLOCK_REF_KHZ 27000
/* Config Register (DBE Only) Definitions */
#define DBE_CONFIG_VDAC_ENABLE 0x00000001
#define DBE_CONFIG_VDAC_GSYNC 0x00000002
#define DBE_CONFIG_VDAC_PBLANK 0x00000004
#define DBE_CONFIG_FPENABLE 0x00000008
#define DBE_CONFIG_LENDIAN 0x00000020
#define DBE_CONFIG_TILEHIST 0x00000040
#define DBE_CONFIG_EXT_ADDR 0x00000080
#define DBE_CONFIG_FBDEV ( DBE_CONFIG_VDAC_ENABLE | \
DBE_CONFIG_VDAC_GSYNC | \
DBE_CONFIG_VDAC_PBLANK | \
DBE_CONFIG_LENDIAN | \
DBE_CONFIG_EXT_ADDR )
/*
* Available Video Timings and Corresponding Indices
*/
typedef enum {
DBE_VT_640_480_60,
DBE_VT_800_600_60,
DBE_VT_800_600_75,
DBE_VT_800_600_120,
DBE_VT_1024_768_50,
DBE_VT_1024_768_60,
DBE_VT_1024_768_75,
DBE_VT_1024_768_85,
DBE_VT_1024_768_120,
DBE_VT_1280_1024_50,
DBE_VT_1280_1024_60,
DBE_VT_1280_1024_75,
DBE_VT_1280_1024_85,
DBE_VT_1600_1024_53,
DBE_VT_1600_1024_60,
DBE_VT_1600_1200_50,
DBE_VT_1600_1200_60,
DBE_VT_1600_1200_75,
DBE_VT_1920_1080_50,
DBE_VT_1920_1080_60,
DBE_VT_1920_1080_72,
DBE_VT_1920_1200_50,
DBE_VT_1920_1200_60,
DBE_VT_1920_1200_66,
DBE_VT_UNKNOWN
} dbe_timing_t;
/*
* Crime Video Timing Data Structure
*/
struct dbe_timing_info
{
dbe_timing_t type;
int flags;
short width; /* Monitor resolution */
short height;
int fields_sec; /* fields/sec (Hz -3 dec. places */
int cfreq; /* pixel clock frequency (MHz -3 dec. places) */
short htotal; /* Horizontal total pixels */
short hblank_start; /* Horizontal blank start */
short hblank_end; /* Horizontal blank end */
short hsync_start; /* Horizontal sync start */
short hsync_end; /* Horizontal sync end */
short vtotal; /* Vertical total lines */
short vblank_start; /* Vertical blank start */
short vblank_end; /* Vertical blank end */
short vsync_start; /* Vertical sync start */
short vsync_end; /* Vertical sync end */
short pll_m; /* PLL M parameter */
short pll_n; /* PLL P parameter */
short pll_p; /* PLL N parameter */
};
/* Defines for dbe_vof_info_t flags */
#define DBE_VOF_UNKNOWNMON 1
#define DBE_VOF_STEREO 2
#define DBE_VOF_DO_GENSYNC 4 /* enable incoming sync */
#define DBE_VOF_SYNC_ON_GREEN 8 /* sync on green */
#define DBE_VOF_FLATPANEL 0x1000 /* FLATPANEL Timing */
#define DBE_VOF_MAGICKEY 0x2000 /* Backdoor key */
/*
* DBE Timing Tables
*/
#ifdef INCLUDE_TIMING_TABLE_DATA
struct dbe_timing_info dbeVTimings[] = {
{
DBE_VT_640_480_60,
/* flags, width, height, fields_sec, cfreq */
0, 640, 480, 59940, 25175,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
800, 640, 800, 656, 752,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
525, 480, 525, 490, 492,
/* pll_m, pll_n, pll_p */
15, 2, 3
},
{
DBE_VT_800_600_60,
/* flags, width, height, fields_sec, cfreq */
0, 800, 600, 60317, 40000,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1056, 800, 1056, 840, 968,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
628, 600, 628, 601, 605,
/* pll_m, pll_n, pll_p */
3, 1, 1
},
{
DBE_VT_800_600_75,
/* flags, width, height, fields_sec, cfreq */
0, 800, 600, 75000, 49500,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1056, 800, 1056, 816, 896,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
625, 600, 625, 601, 604,
/* pll_m, pll_n, pll_p */
11, 3, 1
},
{
DBE_VT_800_600_120,
/* flags, width, height, fields_sec, cfreq */
DBE_VOF_STEREO, 800, 600, 119800, 82978,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1040, 800, 1040, 856, 976,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
666, 600, 666, 637, 643,
/* pll_m, pll_n, pll_p */
31, 5, 1
},
{
DBE_VT_1024_768_50,
/* flags, width, height, fields_sec, cfreq */
0, 1024, 768, 50000, 54163,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1344, 1024, 1344, 1048, 1184,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
806, 768, 806, 771, 777,
/* pll_m, pll_n, pll_p */
4, 1, 1
},
{
DBE_VT_1024_768_60,
/* flags, width, height, fields_sec, cfreq */
0, 1024, 768, 60004, 65000,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1344, 1024, 1344, 1048, 1184,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
806, 768, 806, 771, 777,
/* pll_m, pll_n, pll_p */
12, 5, 0
},
{
DBE_VT_1024_768_75,
/* flags, width, height, fields_sec, cfreq */
0, 1024, 768, 75029, 78750,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1312, 1024, 1312, 1040, 1136,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
800, 768, 800, 769, 772,
/* pll_m, pll_n, pll_p */
29, 5, 1
},
{
DBE_VT_1024_768_85,
/* flags, width, height, fields_sec, cfreq */
0, 1024, 768, 84997, 94500,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1376, 1024, 1376, 1072, 1168,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
808, 768, 808, 769, 772,
/* pll_m, pll_n, pll_p */
7, 2, 0
},
{
DBE_VT_1024_768_120,
/* flags, width, height, fields_sec, cfreq */
DBE_VOF_STEREO, 1024, 768, 119800, 133195,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1376, 1024, 1376, 1072, 1168,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
808, 768, 808, 769, 772,
/* pll_m, pll_n, pll_p */
5, 1, 0
},
{
DBE_VT_1280_1024_50,
/* flags, width, height, fields_sec, cfreq */
0, 1280, 1024, 50000, 89460,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1680, 1280, 1680, 1360, 1480,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1065, 1024, 1065, 1027, 1030,
/* pll_m, pll_n, pll_p */
10, 3, 0
},
{
DBE_VT_1280_1024_60,
/* flags, width, height, fields_sec, cfreq */
0, 1280, 1024, 60020, 108000,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1688, 1280, 1688, 1328, 1440,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1066, 1024, 1066, 1025, 1028,
/* pll_m, pll_n, pll_p */
4, 1, 0
},
{
DBE_VT_1280_1024_75,
/* flags, width, height, fields_sec, cfreq */
0, 1280, 1024, 75025, 135000,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1688, 1280, 1688, 1296, 1440,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1066, 1024, 1066, 1025, 1028,
/* pll_m, pll_n, pll_p */
5, 1, 0
},
{
DBE_VT_1280_1024_85,
/* flags, width, height, fields_sec, cfreq */
0, 1280, 1024, 85024, 157500,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1728, 1280, 1728, 1344, 1504,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1072, 1024, 1072, 1025, 1028,
/* pll_m, pll_n, pll_p */
29, 5, 0
},
{
DBE_VT_1600_1024_53,
/* flags, width, height, fields_sec, cfreq */
DBE_VOF_FLATPANEL | DBE_VOF_MAGICKEY,
1600, 1024, 53000, 107447,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1900, 1600, 1900, 1630, 1730,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1067, 1024, 1067, 1027, 1030,
/* pll_m, pll_n, pll_p */
4, 1, 0
},
{
DBE_VT_1600_1024_60,
/* flags, width, height, fields_sec, cfreq */
DBE_VOF_FLATPANEL, 1600, 1024, 60000, 106913,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
1670, 1600, 1670, 1630, 1650,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1067, 1024, 1067, 1027, 1030,
/* pll_m, pll_n, pll_p */
4, 1, 0
},
{
DBE_VT_1600_1200_50,
/* flags, width, height, fields_sec, cfreq */
0, 1600, 1200, 50000, 130500,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
2088, 1600, 2088, 1644, 1764,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1250, 1200, 1250, 1205, 1211,
/* pll_m, pll_n, pll_p */
24, 5, 0
},
{
DBE_VT_1600_1200_60,
/* flags, width, height, fields_sec, cfreq */
0, 1600, 1200, 59940, 162000,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
2160, 1600, 2160, 1644, 1856,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1250, 1200, 1250, 1201, 1204,
/* pll_m, pll_n, pll_p */
6, 1, 0
},
{
DBE_VT_1600_1200_75,
/* flags, width, height, fields_sec, cfreq */
0, 1600, 1200, 75000, 202500,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
2160, 1600, 2160, 1644, 1856,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1250, 1200, 1250, 1201, 1204,
/* pll_m, pll_n, pll_p */
15, 2, 0
},
{
DBE_VT_1920_1080_50,
/* flags, width, height, fields_sec, cfreq */
0, 1920, 1080, 50000, 133200,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
2368, 1920, 2368, 1952, 2096,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1125, 1080, 1125, 1083, 1086,
/* pll_m, pll_n, pll_p */
5, 1, 0
},
{
DBE_VT_1920_1080_60,
/* flags, width, height, fields_sec, cfreq */
0, 1920, 1080, 59940, 159840,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
2368, 1920, 2368, 1952, 2096,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1125, 1080, 1125, 1083, 1086,
/* pll_m, pll_n, pll_p */
6, 1, 0
},
{
DBE_VT_1920_1080_72,
/* flags, width, height, fields_sec, cfreq */
0, 1920, 1080, 72000, 216023,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
2560, 1920, 2560, 1968, 2184,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1172, 1080, 1172, 1083, 1086,
/* pll_m, pll_n, pll_p */
8, 1, 0
},
{
DBE_VT_1920_1200_50,
/* flags, width, height, fields_sec, cfreq */
0, 1920, 1200, 50000, 161500,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
2584, 1920, 2584, 1984, 2240,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1250, 1200, 1250, 1203, 1206,
/* pll_m, pll_n, pll_p */
6, 1, 0
},
{
DBE_VT_1920_1200_60,
/* flags, width, height, fields_sec, cfreq */
0, 1920, 1200, 59940, 193800,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
2584, 1920, 2584, 1984, 2240,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1250, 1200, 1250, 1203, 1206,
/* pll_m, pll_n, pll_p */
29, 4, 0
},
{
DBE_VT_1920_1200_66,
/* flags, width, height, fields_sec, cfreq */
0, 1920, 1200, 66000, 213180,
/* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
2584, 1920, 2584, 1984, 2240,
/* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
1250, 1200, 1250, 1203, 1206,
/* pll_m, pll_n, pll_p */
8, 1, 0
}
};
#endif // INCLUDE_TIMING_TABLE_DATA
#endif // ! __SGIVWFB_H__

9
sound/oss/Kconfig
View File

@ -13,15 +13,6 @@ config SOUND_BCM_CS4297A
note that CONFIG_KGDB should not be enabled at the same
time, since it also attempts to use this UART port.
config SOUND_VWSND
tristate "SGI Visual Workstation Sound"
depends on X86_VISWS
help
Say Y or M if you have an SGI Visual Workstation and you want to be
able to use its on-board audio. Read
<file:Documentation/sound/oss/vwsnd> for more info on this driver's
capabilities.
config SOUND_MSNDCLAS
tristate "Support for Turtle Beach MultiSound Classic, Tahiti, Monterey"
depends on (m || !STANDALONE) && ISA

1
sound/oss/Makefile
View File

@ -24,7 +24,6 @@ obj-$(CONFIG_SOUND_VIDC) += vidc_mod.o
obj-$(CONFIG_SOUND_WAVEARTIST) += waveartist.o
obj-$(CONFIG_SOUND_MSNDCLAS) += msnd.o msnd_classic.o
obj-$(CONFIG_SOUND_MSNDPIN) += msnd.o msnd_pinnacle.o
obj-$(CONFIG_SOUND_VWSND) += vwsnd.o
obj-$(CONFIG_SOUND_BCM_CS4297A) += swarm_cs4297a.o
obj-$(CONFIG_DMASOUND) += dmasound/

3506
sound/oss/vwsnd.c
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