pinctrl: sirf: wrap all gpio banks into one gpio_chip
all gpio banks are in one chip, that makes software clean in mapping irq and gpio. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Barry Song
Linus Walleij
parent
aef95b691f
commit
c5eb757ca8
@ -34,15 +34,19 @@
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#define DRIVER_NAME "pinmux-sirf"
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struct sirfsoc_gpio_bank {
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struct of_mm_gpio_chip chip;
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struct irq_domain *domain;
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int id;
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int parent_irq;
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spinlock_t lock;
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bool is_marco; /* for marco, some registers are different with prima2 */
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};
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static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
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struct sirfsoc_gpio_chip {
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struct of_mm_gpio_chip chip;
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struct irq_domain *domain;
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bool is_marco; /* for marco, some registers are different with prima2 */
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struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
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};
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static struct sirfsoc_gpio_chip sgpio_chip;
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static DEFINE_SPINLOCK(sgpio_lock);
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static struct sirfsoc_pin_group *sirfsoc_pin_groups;
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@ -258,32 +262,12 @@ static struct pinctrl_desc sirfsoc_pinmux_desc = {
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/*
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* Todo: bind irq_chip to every pinctrl_gpio_range
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*/
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static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
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{
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.name = "sirfsoc-gpio*",
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.id = 0,
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.base = 0,
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.pin_base = 0,
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.npins = 32,
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}, {
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.name = "sirfsoc-gpio*",
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.id = 1,
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.base = 32,
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.pin_base = 32,
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.npins = 32,
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}, {
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.name = "sirfsoc-gpio*",
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.id = 2,
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.base = 64,
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.pin_base = 64,
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.npins = 32,
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}, {
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.name = "sirfsoc-gpio*",
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.id = 3,
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.base = 96,
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.pin_base = 96,
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.npins = 19,
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},
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static struct pinctrl_gpio_range sirfsoc_gpio_ranges = {
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.name = "sirfsoc-gpio*",
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.id = 0,
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.base = 0,
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.pin_base = 0,
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.npins = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS,
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};
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static void __iomem *sirfsoc_rsc_of_iomap(void)
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@ -303,19 +287,19 @@ static void __iomem *sirfsoc_rsc_of_iomap(void)
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}
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static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
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const struct of_phandle_args *gpiospec,
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u32 *flags)
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const struct of_phandle_args *gpiospec,
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u32 *flags)
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{
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if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
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if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
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return -EINVAL;
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if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc)
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if (gc != &sgpio_chip.chip.gc)
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return -EINVAL;
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if (flags)
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if (flags)
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*flags = gpiospec->args[1];
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return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE;
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return gpiospec->args[0];
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}
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static const struct of_device_id pinmux_ids[] = {
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@ -331,7 +315,6 @@ static int sirfsoc_pinmux_probe(struct platform_device *pdev)
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struct sirfsoc_pmx *spmx;
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struct device_node *np = pdev->dev.of_node;
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const struct sirfsoc_pinctrl_data *pdata;
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int i;
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/* Create state holders etc for this driver */
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spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
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@ -375,10 +358,8 @@ static int sirfsoc_pinmux_probe(struct platform_device *pdev)
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goto out_no_pmx;
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}
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for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
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sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
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pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
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}
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sirfsoc_gpio_ranges.gc = &sgpio_chip.chip.gc;
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pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges);
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dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
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@ -464,33 +445,23 @@ static int __init sirfsoc_pinmux_init(void)
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}
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arch_initcall(sirfsoc_pinmux_init);
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static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
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{
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struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
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struct sirfsoc_gpio_bank, chip);
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return irq_create_mapping(bank->domain, offset + bank->id *
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SIRFSOC_GPIO_BANK_SIZE);
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return &sgpio_chip.sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
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}
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static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
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static int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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return irq_create_mapping(sgpio_chip.domain, offset);
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}
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static inline int sirfsoc_gpio_to_bankoff(unsigned int gpio)
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{
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return gpio % SIRFSOC_GPIO_BANK_SIZE;
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}
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static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
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{
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return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
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}
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static inline struct sirfsoc_gpio_bank *sirfsoc_gpiochip_to_bank(struct gpio_chip *chip)
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{
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return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
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}
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static void sirfsoc_gpio_irq_ack(struct irq_data *d)
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{
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struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
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int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
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u32 val, offset;
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unsigned long flags;
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@ -499,9 +470,9 @@ static void sirfsoc_gpio_irq_ack(struct irq_data *d)
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spin_lock_irqsave(&sgpio_lock, flags);
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val = readl(bank->chip.regs + offset);
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val = readl(sgpio_chip.chip.regs + offset);
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writel(val, bank->chip.regs + offset);
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writel(val, sgpio_chip.chip.regs + offset);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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}
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@ -515,24 +486,24 @@ static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
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spin_lock_irqsave(&sgpio_lock, flags);
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val = readl(bank->chip.regs + offset);
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val = readl(sgpio_chip.chip.regs + offset);
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val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
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val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
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writel(val, bank->chip.regs + offset);
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writel(val, sgpio_chip.chip.regs + offset);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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}
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static void sirfsoc_gpio_irq_mask(struct irq_data *d)
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{
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struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
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__sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
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}
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static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
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{
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struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
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int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
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u32 val, offset;
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unsigned long flags;
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@ -541,17 +512,17 @@ static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
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spin_lock_irqsave(&sgpio_lock, flags);
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val = readl(bank->chip.regs + offset);
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val = readl(sgpio_chip.chip.regs + offset);
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val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
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val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
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writel(val, bank->chip.regs + offset);
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writel(val, sgpio_chip.chip.regs + offset);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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}
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static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
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{
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struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
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int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
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u32 val, offset;
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unsigned long flags;
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@ -560,7 +531,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
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spin_lock_irqsave(&sgpio_lock, flags);
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val = readl(bank->chip.regs + offset);
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val = readl(sgpio_chip.chip.regs + offset);
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val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
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switch (type) {
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@ -588,7 +559,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
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break;
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}
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writel(val, bank->chip.regs + offset);
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writel(val, sgpio_chip.chip.regs + offset);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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@ -597,10 +568,8 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
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static int sirfsoc_gpio_irq_reqres(struct irq_data *d)
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{
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struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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if (gpio_lock_as_irq(&bank->chip.gc, d->hwirq % SIRFSOC_GPIO_BANK_SIZE)) {
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dev_err(bank->chip.gc.dev,
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if (gpio_lock_as_irq(&sgpio_chip.chip.gc, d->hwirq)) {
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dev_err(sgpio_chip.chip.gc.dev,
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"unable to lock HW IRQ %lu for IRQ\n",
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d->hwirq);
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return -EINVAL;
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@ -610,9 +579,7 @@ static int sirfsoc_gpio_irq_reqres(struct irq_data *d)
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static void sirfsoc_gpio_irq_relres(struct irq_data *d)
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{
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struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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gpio_unlock_as_irq(&bank->chip.gc, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
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gpio_unlock_as_irq(&sgpio_chip.chip.gc, d->hwirq);
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}
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static struct irq_chip sirfsoc_irq_chip = {
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@ -634,7 +601,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
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chained_irq_enter(chip, desc);
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status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
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status = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
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if (!status) {
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printk(KERN_WARNING
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"%s: gpio id %d status %#x no interrupt is flaged\n",
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@ -644,7 +611,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
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}
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while (status) {
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ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
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ctrl = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
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/*
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* Here we must check whether the corresponding GPIO's interrupt
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@ -653,7 +620,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
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if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
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pr_debug("%s: gpio id %d idx %d happens\n",
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__func__, bank->id, idx);
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generic_handle_irq(irq_find_mapping(bank->domain, idx +
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generic_handle_irq(irq_find_mapping(sgpio_chip.domain, idx +
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bank->id * SIRFSOC_GPIO_BANK_SIZE));
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}
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@ -668,14 +635,14 @@ static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsign
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{
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u32 val;
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val = readl(bank->chip.regs + ctrl_offset);
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val = readl(sgpio_chip.chip.regs + ctrl_offset);
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val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
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writel(val, bank->chip.regs + ctrl_offset);
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writel(val, sgpio_chip.chip.regs + ctrl_offset);
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}
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static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpiochip_to_bank(chip);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset);
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unsigned long flags;
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if (pinctrl_request_gpio(chip->base + offset))
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@ -697,7 +664,7 @@ static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
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static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpiochip_to_bank(chip);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset);
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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@ -712,8 +679,8 @@ static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
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static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpiochip_to_bank(chip);
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int idx = sirfsoc_gpio_to_offset(gpio);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio);
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int idx = sirfsoc_gpio_to_bankoff(gpio);
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unsigned long flags;
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unsigned offset;
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@ -736,7 +703,7 @@ static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsig
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spin_lock_irqsave(&bank->lock, flags);
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out_ctrl = readl(bank->chip.regs + offset);
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out_ctrl = readl(sgpio_chip.chip.regs + offset);
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if (value)
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out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
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else
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@ -744,15 +711,15 @@ static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsig
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out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
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out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
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writel(out_ctrl, bank->chip.regs + offset);
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writel(out_ctrl, sgpio_chip.chip.regs + offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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}
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static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpiochip_to_bank(chip);
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int idx = sirfsoc_gpio_to_offset(gpio);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio);
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int idx = sirfsoc_gpio_to_bankoff(gpio);
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u32 offset;
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unsigned long flags;
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@ -769,13 +736,13 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
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static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpiochip_to_bank(chip);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset);
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u32 val;
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
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val = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
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spin_unlock_irqrestore(&bank->lock, flags);
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@ -785,18 +752,18 @@ static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
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static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpiochip_to_bank(chip);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset);
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u32 ctrl;
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
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ctrl = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
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if (value)
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ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
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else
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ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
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writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
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writel(ctrl, sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
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spin_unlock_irqrestore(&bank->lock, flags);
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}
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@ -811,7 +778,6 @@ static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
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irq_set_chip(irq, &sirfsoc_irq_chip);
|
||||
irq_set_handler(irq, handle_level_irq);
|
||||
irq_set_chip_data(irq, bank + hwirq / SIRFSOC_GPIO_BANK_SIZE);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
|
||||
return 0;
|
||||
@ -830,10 +796,10 @@ static void sirfsoc_gpio_set_pullup(const u32 *pullups)
|
||||
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
|
||||
for_each_set_bit(n, p + i, BITS_PER_LONG) {
|
||||
u32 offset = SIRFSOC_GPIO_CTRL(i, n);
|
||||
u32 val = readl(sgpio_bank[i].chip.regs + offset);
|
||||
u32 val = readl(sgpio_chip.chip.regs + offset);
|
||||
val |= SIRFSOC_GPIO_CTL_PULL_MASK;
|
||||
val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
|
||||
writel(val, sgpio_bank[i].chip.regs + offset);
|
||||
writel(val, sgpio_chip.chip.regs + offset);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -846,10 +812,10 @@ static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
|
||||
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
|
||||
for_each_set_bit(n, p + i, BITS_PER_LONG) {
|
||||
u32 offset = SIRFSOC_GPIO_CTRL(i, n);
|
||||
u32 val = readl(sgpio_bank[i].chip.regs + offset);
|
||||
u32 val = readl(sgpio_chip.chip.regs + offset);
|
||||
val |= SIRFSOC_GPIO_CTL_PULL_MASK;
|
||||
val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
|
||||
writel(val, sgpio_bank[i].chip.regs + offset);
|
||||
writel(val, sgpio_chip.chip.regs + offset);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -877,48 +843,47 @@ static int sirfsoc_gpio_probe(struct device_node *np)
|
||||
is_marco = 1;
|
||||
|
||||
domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS,
|
||||
&sirfsoc_gpio_irq_simple_ops, sgpio_bank);
|
||||
&sirfsoc_gpio_irq_simple_ops, &sgpio_chip);
|
||||
if (!domain) {
|
||||
pr_err("%s: Failed to create irqdomain\n", np->full_name);
|
||||
err = -ENOSYS;
|
||||
goto out;
|
||||
}
|
||||
|
||||
sgpio_chip.chip.gc.request = sirfsoc_gpio_request;
|
||||
sgpio_chip.chip.gc.free = sirfsoc_gpio_free;
|
||||
sgpio_chip.chip.gc.direction_input = sirfsoc_gpio_direction_input;
|
||||
sgpio_chip.chip.gc.get = sirfsoc_gpio_get_value;
|
||||
sgpio_chip.chip.gc.direction_output = sirfsoc_gpio_direction_output;
|
||||
sgpio_chip.chip.gc.set = sirfsoc_gpio_set_value;
|
||||
sgpio_chip.chip.gc.to_irq = sirfsoc_gpio_to_irq;
|
||||
sgpio_chip.chip.gc.base = 0;
|
||||
sgpio_chip.chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
|
||||
sgpio_chip.chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
|
||||
sgpio_chip.chip.gc.of_node = np;
|
||||
sgpio_chip.chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
|
||||
sgpio_chip.chip.gc.of_gpio_n_cells = 2;
|
||||
sgpio_chip.chip.gc.dev = &pdev->dev;
|
||||
sgpio_chip.chip.regs = regs;
|
||||
sgpio_chip.is_marco = is_marco;
|
||||
sgpio_chip.domain = domain;
|
||||
|
||||
err = gpiochip_add(&sgpio_chip.chip.gc);
|
||||
if (err) {
|
||||
pr_err("%s: error in probe function with status %d\n",
|
||||
np->full_name, err);
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
|
||||
bank = &sgpio_bank[i];
|
||||
bank = &sgpio_chip.sgpio_bank[i];
|
||||
spin_lock_init(&bank->lock);
|
||||
bank->chip.gc.request = sirfsoc_gpio_request;
|
||||
bank->chip.gc.free = sirfsoc_gpio_free;
|
||||
bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
|
||||
bank->chip.gc.get = sirfsoc_gpio_get_value;
|
||||
bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
|
||||
bank->chip.gc.set = sirfsoc_gpio_set_value;
|
||||
bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
|
||||
bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
|
||||
bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
|
||||
bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
|
||||
bank->chip.gc.of_node = np;
|
||||
bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
|
||||
bank->chip.gc.of_gpio_n_cells = 2;
|
||||
bank->chip.gc.dev = &pdev->dev;
|
||||
bank->chip.regs = regs;
|
||||
bank->id = i;
|
||||
bank->is_marco = is_marco;
|
||||
bank->parent_irq = platform_get_irq(pdev, i);
|
||||
if (bank->parent_irq < 0) {
|
||||
err = bank->parent_irq;
|
||||
goto out;
|
||||
}
|
||||
|
||||
err = gpiochip_add(&bank->chip.gc);
|
||||
if (err) {
|
||||
pr_err("%s: error in probe function with status %d\n",
|
||||
np->full_name, err);
|
||||
goto out;
|
||||
}
|
||||
|
||||
bank->domain = domain;
|
||||
|
||||
irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
|
||||
irq_set_handler_data(bank->parent_irq, bank);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user