forked from Minki/linux
pm80xx: set PHY profiles for ATTO 12Gb SAS controllers
PHY profiles are not saved in NVRAM on ATTO 12Gb SAS controllers. Therefore, in order for the controller to function in a wide range of configurations, the PHY profiles must be statically set. This patch provides the necessary functionality to do so. Signed-off-by: Benjamin Rood <brood@attotech.com> Reviewed-by: Jack Wang <jinpu.wang@profitbricks.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Benjamin Rood
Martin K. Petersen
parent
10efa460fe
commit
c5614df7ff
@ -732,6 +732,131 @@ static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
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return 0;
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}
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struct pm8001_mpi3_phy_pg_trx_config {
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u32 LaneLosCfg;
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u32 LanePgaCfg1;
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u32 LanePisoCfg1;
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u32 LanePisoCfg2;
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u32 LanePisoCfg3;
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u32 LanePisoCfg4;
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u32 LanePisoCfg5;
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u32 LanePisoCfg6;
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u32 LaneBctCtrl;
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};
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/**
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* pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
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* @pm8001_ha : our adapter
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* @phycfg : PHY config page to populate
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*/
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static
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void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
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struct pm8001_mpi3_phy_pg_trx_config *phycfg)
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{
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phycfg->LaneLosCfg = 0x00000132;
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phycfg->LanePgaCfg1 = 0x00203949;
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phycfg->LanePisoCfg1 = 0x000000FF;
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phycfg->LanePisoCfg2 = 0xFF000001;
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phycfg->LanePisoCfg3 = 0xE7011300;
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phycfg->LanePisoCfg4 = 0x631C40C0;
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phycfg->LanePisoCfg5 = 0xF8102036;
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phycfg->LanePisoCfg6 = 0xF74A1000;
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phycfg->LaneBctCtrl = 0x00FB33F8;
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}
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/**
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* pm8001_get_external_phy_settings : Retrieves the external PHY settings
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* @pm8001_ha : our adapter
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* @phycfg : PHY config page to populate
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*/
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static
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void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
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struct pm8001_mpi3_phy_pg_trx_config *phycfg)
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{
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phycfg->LaneLosCfg = 0x00000132;
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phycfg->LanePgaCfg1 = 0x00203949;
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phycfg->LanePisoCfg1 = 0x000000FF;
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phycfg->LanePisoCfg2 = 0xFF000001;
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phycfg->LanePisoCfg3 = 0xE7011300;
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phycfg->LanePisoCfg4 = 0x63349140;
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phycfg->LanePisoCfg5 = 0xF8102036;
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phycfg->LanePisoCfg6 = 0xF80D9300;
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phycfg->LaneBctCtrl = 0x00FB33F8;
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}
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/**
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* pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
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* @pm8001_ha : our adapter
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* @phymask : The PHY mask
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*/
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static
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void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
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{
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switch (pm8001_ha->pdev->subsystem_device) {
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case 0x0070: /* H1280 - 8 external 0 internal */
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case 0x0072: /* H12F0 - 16 external 0 internal */
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*phymask = 0x0000;
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break;
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case 0x0071: /* H1208 - 0 external 8 internal */
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case 0x0073: /* H120F - 0 external 16 internal */
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*phymask = 0xFFFF;
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break;
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case 0x0080: /* H1244 - 4 external 4 internal */
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*phymask = 0x00F0;
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break;
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case 0x0081: /* H1248 - 4 external 8 internal */
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*phymask = 0x0FF0;
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break;
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case 0x0082: /* H1288 - 8 external 8 internal */
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*phymask = 0xFF00;
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break;
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default:
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PM8001_INIT_DBG(pm8001_ha,
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pm8001_printk("Unknown subsystem device=0x%.04x",
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pm8001_ha->pdev->subsystem_device));
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}
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}
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/**
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* pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
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* @pm8001_ha : our adapter
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*/
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static
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int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
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{
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struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
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struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
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int phymask = 0;
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int i = 0;
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memset(&phycfg_int, 0, sizeof(phycfg_int));
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memset(&phycfg_ext, 0, sizeof(phycfg_ext));
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pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
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pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
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pm8001_get_phy_mask(pm8001_ha, &phymask);
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for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
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if (phymask & (1 << i)) {/* Internal PHY */
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pm8001_set_phy_profile_single(pm8001_ha, i,
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sizeof(phycfg_int) / sizeof(u32),
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(u32 *)&phycfg_int);
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} else { /* External PHY */
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pm8001_set_phy_profile_single(pm8001_ha, i,
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sizeof(phycfg_ext) / sizeof(u32),
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(u32 *)&phycfg_ext);
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}
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}
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return 0;
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}
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/**
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* pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
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* @pm8001_ha : our hba.
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@ -740,6 +865,11 @@ static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
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{
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switch (pm8001_ha->pdev->subsystem_vendor) {
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case PCI_VENDOR_ID_ATTO:
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if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
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return 0;
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else
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return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
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case PCI_VENDOR_ID_ADAPTEC2:
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case 0:
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return 0;
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@ -710,6 +710,8 @@ int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
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int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
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void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
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u32 length, u8 *buf);
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void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
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u32 phy, u32 length, u32 *buf);
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int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
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ssize_t pm80xx_get_fatal_dump(struct device *cdev,
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struct device_attribute *attr, char *buf);
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@ -4576,6 +4576,38 @@ void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
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}
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PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
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}
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void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
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u32 phy, u32 length, u32 *buf)
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{
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u32 tag, opc;
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int rc, i;
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struct set_phy_profile_req payload;
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struct inbound_queue_table *circularQ;
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memset(&payload, 0, sizeof(payload));
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rc = pm8001_tag_alloc(pm8001_ha, &tag);
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if (rc)
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PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));
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circularQ = &pm8001_ha->inbnd_q_tbl[0];
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opc = OPC_INB_SET_PHY_PROFILE;
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payload.tag = cpu_to_le32(tag);
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payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
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| (phy & 0xFF));
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for (i = 0; i < length; i++)
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payload.reserved[i] = cpu_to_le32(*(buf + i));
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rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
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if (rc)
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pm8001_tag_free(pm8001_ha, tag);
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PM8001_INIT_DBG(pm8001_ha,
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pm8001_printk("PHY %d settings applied", phy));
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}
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const struct pm8001_dispatch pm8001_80xx_dispatch = {
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.name = "pmc80xx",
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.chip_init = pm80xx_chip_init,
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