leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

EDAC/ie31200: Add Intel Coffee Lake CPU support

Browse Source 
Coffee Lake seems to work like Skylake and Kaby Lake. Add all device IDs
for Coffee Lake-S CPUs according to datasheet.

 [ bp: Massage. ]

Signed-off-by: Marco Elver <elver@google.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Tony Luck <tony.luck@intel.com>
Cc: James Morse <james.morse@arm.com>
Cc: Jason Baron <jbaron@akamai.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Link: https://lkml.kernel.org/r/20190610191422.177931-1-elver@google.com
This commit is contained in:
Marco Elver 2019-06-10 21:14:21 +02:00 committed by Tony Luck
parent 91abaeaaff
commit c452a9d30f
1 changed files with 55 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

58
drivers/edac/ie31200_edac.c
View File

@ -20,11 +20,13 @@
* 0c08: Xeon E3-1200 v3 Processor DRAM Controller * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
* 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
* 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
* 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
* *
* Based on Intel specification: * Based on Intel specification:
* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
* http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
* http://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html * http://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
* https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html
* *
* According to the above datasheet (p.16): * According to the above datasheet (p.16):
* " * "
@ -61,6 +63,26 @@
#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
/* Coffee Lake-S */
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca
/* Test if HB is for Skylake or later. */
#define DEVICE_ID_SKYLAKE_OR_LATER(did) \
(((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
(((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
#define IE31200_DIMMS 4 #define IE31200_DIMMS 4
#define IE31200_RANKS 8 #define IE31200_RANKS 8
#define IE31200_RANKS_PER_CHANNEL 4 #define IE31200_RANKS_PER_CHANNEL 4
@ -381,10 +403,10 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
u32 addr_decode, mad_offset; u32 addr_decode, mad_offset;
/* /*
* Kaby Lake seems to work like Skylake. Please re-visit this logic * Kaby Lake, Coffee Lake seem to work like Skylake. Please re-visit
* when adding new CPU support. * this logic when adding new CPU support.
*/ */
bool skl = (pdev->device >= PCI_DEVICE_ID_INTEL_IE31200_HB_8); bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device);
edac_dbg(0, "MC:\n"); edac_dbg(0, "MC:\n");
@ -569,6 +591,36 @@ static const struct pci_device_id ie31200_pci_tbl[] = {
{ {
PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
IE31200}, IE31200},
{
PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID,
0, 0, IE31200},
{
PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID,
0, 0, IE31200},
{
PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID,
0, 0, IE31200},
{
PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4), PCI_ANY_ID, PCI_ANY_ID,
0, 0, IE31200},
{
PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5), PCI_ANY_ID, PCI_ANY_ID,
0, 0, IE31200},
{
PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6), PCI_ANY_ID, PCI_ANY_ID,
0, 0, IE31200},
{
PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7), PCI_ANY_ID, PCI_ANY_ID,
0, 0, IE31200},
{
PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8), PCI_ANY_ID, PCI_ANY_ID,
0, 0, IE31200},
{
PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9), PCI_ANY_ID, PCI_ANY_ID,
0, 0, IE31200},
{
PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID,
0, 0, IE31200},
{ {
0, 0,
} /* 0 terminated list. */ } /* 0 terminated list. */