forked from Minki/linux
ARM: dts: Add support for Newflow NanoBone board
NanoBone Specification: ----------------------- CPU: TI AM335x Memory: 256MB DDR3 128MB NOR flash 128KB FRAM Ethernet: 2 x 10/100 connected to SMSC LAN8710 PHY USB: 1 x USB2.0 Type A I2C: 2Kbit EEPROM (Microchip 24AA02) RTC (Maxim DS1338) GPIO Expander (Microchip MCP23017) Expansion connector: 6 x UART 1 x MMC/SD 1 x USB2.0 Signed-off-by: Mark Jackson <mpfj@newflow.co.uk> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
This commit is contained in:
Mark Jackson
Benoit Cousson
parent
6a96867844
commit
c351e29018
@ -6088,6 +6088,12 @@ L: linux-omap@vger.kernel.org
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S: Maintained
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F: drivers/gpio/gpio-omap.c
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OMAP/NEWFLOW NANOBONE MACHINE SUPPORT
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M: Mark Jackson <mpfj@newflow.co.uk>
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L: linux-omap@vger.kernel.org
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S: Maintained
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F: arch/arm/boot/dts/am335x-nano.dts
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OMFS FILESYSTEM
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M: Bob Copeland <me@bobcopeland.com>
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L: linux-karma-devel@lists.sourceforge.net
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@ -188,6 +188,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
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am335x-evmsk.dtb \
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am335x-bone.dtb \
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am335x-boneblack.dtb \
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am335x-nano.dtb \
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am335x-base0033.dtb \
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am3517-evm.dtb \
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am3517_mt_ventoux.dtb \
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431
arch/arm/boot/dts/am335x-nano.dts
Normal file
431
arch/arm/boot/dts/am335x-nano.dts
Normal file
@ -0,0 +1,431 @@
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/*
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* Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "am33xx.dtsi"
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/ {
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model = "Newflow AM335x NanoBone";
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compatible = "ti,am33xx";
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cpus {
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cpu@0 {
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cpu0-supply = <&dcdc2_reg>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
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leds {
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compatible = "gpio-leds";
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led@0 {
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label = "nanobone:green:usr1";
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gpios = <&gpio1 5 0>;
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default-state = "off";
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};
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};
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};
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&am33xx_pinmux {
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pinctrl-names = "default";
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pinctrl-0 = <&misc_pins>;
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misc_pins: misc_pins {
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pinctrl-single,pins = <
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0x15c (PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */
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>;
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};
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gpmc_pins: gpmc_pins {
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pinctrl-single,pins = <
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0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
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0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
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0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
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0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
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0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
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0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
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0x20 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
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0x24 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
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0x28 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
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0x2c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
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0x30 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
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0x34 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
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0x38 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
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0x3c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
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0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
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0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
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0x80 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */
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0x84 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */
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0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */
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0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
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0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
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0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
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0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */
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0xa4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */
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0xa8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */
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0xac (PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */
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0xb0 (PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */
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0xb4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */
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0xb8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */
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0xbc (PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */
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0xe0 (PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */
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0xe4 (PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */
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0xe8 (PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */
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>;
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};
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i2c0_pins: i2c0_pins {
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pinctrl-single,pins = <
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0x188 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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0x18c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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>;
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};
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uart0_pins: uart0_pins {
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pinctrl-single,pins = <
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0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
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0x174 (PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */
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>;
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};
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uart1_pins: uart1_pins {
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pinctrl-single,pins = <
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0x178 (PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */
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0x17c (PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */
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0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
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0x184 (PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */
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>;
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};
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uart2_pins: uart2_pins {
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pinctrl-single,pins = <
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0xc0 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */
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0xc4 (PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */
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0x150 (PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
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0x154 (PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
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>;
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};
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uart3_pins: uart3_pins {
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pinctrl-single,pins = <
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0xc8 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */
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0xcc (PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */
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0x160 (PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */
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0x164 (PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
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>;
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};
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uart4_pins: uart4_pins {
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pinctrl-single,pins = <
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0xd0 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */
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0xd4 (PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */
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0x168 (PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */
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0x16c (PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */
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>;
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};
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uart5_pins: uart5_pins {
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pinctrl-single,pins = <
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0xd8 (PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */
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0x144 (PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */
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>;
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};
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mmc1_pins: mmc1_pins {
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pinctrl-single,pins = <
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0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
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0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
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0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
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0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
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0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
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0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
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0x1e8 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
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0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */
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>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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rs485-rts-active-high;
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rs485-rx-during-tx;
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rs485-rts-delay = <1 1>;
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linux,rs485-enabled-at-boot-time;
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "okay";
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rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
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rs485-rts-active-high;
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rs485-rts-delay = <1 1>;
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linux,rs485-enabled-at-boot-time;
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_pins>;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_pins>;
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status = "okay";
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart5_pins>;
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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pinctrl-names = "default";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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gpio@20 {
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compatible = "mcp,mcp23017";
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reg = <0x20>;
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};
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tps: tps@24 {
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reg = <0x24>;
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};
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eeprom@53 {
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compatible = "mcp,24c02";
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reg = <0x53>;
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pagesize = <8>;
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};
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rtc@68 {
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compatible = "dallas,ds1307";
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reg = <0x68>;
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};
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};
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&elm {
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status = "okay";
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};
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&gpmc {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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status = "okay";
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gpmc,num-waitpins = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&gpmc_pins>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x08000000>; /* CS0: NOR 128M */
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nor@0,0 {
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reg = <0 0x00000000 0x08000000>;
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compatible = "cfi-flash";
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linux,mtd-name = "spansion,s29gl010p11t";
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bank-width = <2>;
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gpmc,mux-add-data = <2>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <160>;
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gpmc,cs-wr-off-ns = <160>;
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gpmc,adv-on-ns = <10>;
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gpmc,adv-rd-off-ns = <30>;
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gpmc,adv-wr-off-ns = <30>;
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gpmc,oe-on-ns = <40>;
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gpmc,oe-off-ns = <160>;
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gpmc,we-on-ns = <40>;
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gpmc,we-off-ns = <160>;
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gpmc,rd-cycle-ns = <160>;
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gpmc,wr-cycle-ns = <160>;
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gpmc,access-ns = <150>;
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gpmc,page-burst-access-ns = <10>;
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gpmc,cycle2cycle-samecsen;
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gpmc,cycle2cycle-delay-ns = <20>;
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gpmc,wr-data-mux-bus-ns = <70>;
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gpmc,wr-access-ns = <80>;
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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MTD partition table
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===================
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+------------+-->0x00000000-> U-Boot start
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| |
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| |-->0x000BFFFF-> U-Boot end
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| |-->0x000C0000-> ENV1 start
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| |
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| |-->0x000DFFFF-> ENV1 end
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| |-->0x000E0000-> ENV2 start
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| |
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| |-->0x000FFFFF-> ENV2 end
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| |-->0x00100000-> Kernel start
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| |
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| |-->0x004FFFFF-> Kernel end
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| |-->0x00500000-> File system start
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| |
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| |-->0x014FFFFF-> File system end
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| |-->0x01500000-> User data start
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| |
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| |-->0x03FFFFFF-> User data end
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| |-->0x04000000-> Data storage start
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| |
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+------------+-->0x08000000-> NOR end (Free end)
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*/
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partition@0 {
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label = "boot";
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reg = <0x00000000 0x000c0000>; /* 768KB */
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};
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partition@1 {
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label = "env1";
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reg = <0x000c0000 0x00020000>; /* 128KB */
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};
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partition@2 {
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label = "env2";
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reg = <0x000e0000 0x00020000>; /* 128KB */
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};
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partition@3 {
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label = "kernel";
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reg = <0x00100000 0x00400000>; /* 4MB */
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};
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partition@4 {
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label = "rootfs";
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reg = <0x00500000 0x01000000>; /* 16MB */
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};
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partition@5 {
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label = "user";
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reg = <0x01500000 0x02b00000>; /* 43MB */
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};
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partition@6 {
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label = "data";
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reg = <0x04000000 0x04000000>; /* 64MB */
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};
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};
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};
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&mac {
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dual_emac = <1>;
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};
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&cpsw_emac0 {
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phy_id = <&davinci_mdio>, <0>;
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dual_emac_res_vlan = <1>;
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};
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&cpsw_emac1 {
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phy_id = <&davinci_mdio>, <1>;
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dual_emac_res_vlan = <2>;
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};
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&mmc1 {
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status = "okay";
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vmmc-supply = <&ldo4_reg>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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bus-width = <4>;
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cd-gpios = <&gpio3 8 0>;
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wp-gpios = <&gpio3 18 0>;
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};
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#include "tps65217.dtsi"
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&tps {
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regulators {
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dcdc1_reg: regulator@0 {
|
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/* +1.5V voltage with ±4% tolerance */
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regulator-min-microvolt = <1450000>;
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regulator-max-microvolt = <1550000>;
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regulator-boot-on;
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regulator-always-on;
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};
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dcdc2_reg: regulator@1 {
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/* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */
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regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <915000>;
|
||||
regulator-max-microvolt = <1140000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <915000>;
|
||||
regulator-max-microvolt = <1140000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
/* +1.8V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <1870000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
/* +3.3V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <3175000>;
|
||||
regulator-max-microvolt = <3430000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
/* +1.8V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <1870000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
/* +3.3V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <3175000>;
|
||||
regulator-max-microvolt = <3430000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user