forked from Minki/linux
watchdog: Add tegra watchdog
Add a driver for the hardware watchdogs in NVIDIA Tegra SoCs (Tegra30 and later). This driver will configure one watchdog timer that will reset the system in the case of a watchdog timeout. This driver binds to the nvidia,tegra30-timer device node and gets its register base from there. Signed-off-by: Andrew Chew <achew@nvidia.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Andrew Chew
Wim Van Sebroeck
parent
8d6a140b5f
commit
c33a15974c
@ -325,6 +325,11 @@ soft_noboot: Softdog action, set to 1 to ignore reboots, 0 to reboot
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stmp3xxx_wdt:
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heartbeat: Watchdog heartbeat period in seconds from 1 to 4194304, default 19
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-------------------------------------------------
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tegra_wdt:
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heartbeat: Watchdog heartbeats in seconds. (default = 120)
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nowayout: Watchdog cannot be stopped once started
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(default=kernel config parameter)
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-------------------------------------------------
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ts72xx_wdt:
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timeout: Watchdog timeout in seconds. (1 <= timeout <= 8, default=8)
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nowayout: Disable watchdog shutdown on close
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@ -430,6 +430,17 @@ config SIRFSOC_WATCHDOG
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Support for CSR SiRFprimaII and SiRFatlasVI watchdog. When
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the watchdog triggers the system will be reset.
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config TEGRA_WATCHDOG
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tristate "Tegra watchdog"
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depends on ARCH_TEGRA || COMPILE_TEST
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select WATCHDOG_CORE
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help
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Say Y here to include support for the watchdog timer
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embedded in NVIDIA Tegra SoCs.
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To compile this driver as a module, choose M here: the
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module will be called tegra_wdt.
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# AVR32 Architecture
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config AT32AP700X_WDT
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@ -58,6 +58,7 @@ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
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obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o
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obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o
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obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
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obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o
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# AVR32 Architecture
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obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
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302
drivers/watchdog/tegra_wdt.c
Normal file
302
drivers/watchdog/tegra_wdt.c
Normal file
@ -0,0 +1,302 @@
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/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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/* minimum and maximum watchdog trigger timeout, in seconds */
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#define MIN_WDT_TIMEOUT 1
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#define MAX_WDT_TIMEOUT 255
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/*
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* Base of the WDT registers, from the timer base address. There are
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* actually 5 watchdogs that can be configured (by pairing with an available
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* timer), at bases 0x100 + (WDT ID) * 0x20, where WDT ID is 0 through 4.
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* This driver only configures the first watchdog (WDT ID 0).
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*/
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#define WDT_BASE 0x100
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#define WDT_ID 0
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/*
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* Register base of the timer that's selected for pairing with the watchdog.
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* This driver arbitrarily uses timer 5, which is currently unused by
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* other drivers (in particular, the Tegra clocksource driver). If this
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* needs to change, take care that the new timer is not used by the
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* clocksource driver.
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*/
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#define WDT_TIMER_BASE 0x60
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#define WDT_TIMER_ID 5
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/* WDT registers */
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#define WDT_CFG 0x0
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#define WDT_CFG_PERIOD_SHIFT 4
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#define WDT_CFG_PERIOD_MASK 0xff
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#define WDT_CFG_INT_EN (1 << 12)
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#define WDT_CFG_PMC2CAR_RST_EN (1 << 15)
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#define WDT_STS 0x4
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#define WDT_STS_COUNT_SHIFT 4
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#define WDT_STS_COUNT_MASK 0xff
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#define WDT_STS_EXP_SHIFT 12
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#define WDT_STS_EXP_MASK 0x3
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#define WDT_CMD 0x8
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#define WDT_CMD_START_COUNTER (1 << 0)
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#define WDT_CMD_DISABLE_COUNTER (1 << 1)
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#define WDT_UNLOCK (0xc)
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#define WDT_UNLOCK_PATTERN (0xc45a << 0)
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/* Timer registers */
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#define TIMER_PTV 0x0
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#define TIMER_EN (1 << 31)
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#define TIMER_PERIODIC (1 << 30)
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struct tegra_wdt {
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struct watchdog_device wdd;
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void __iomem *wdt_regs;
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void __iomem *tmr_regs;
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};
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#define WDT_HEARTBEAT 120
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static int heartbeat = WDT_HEARTBEAT;
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module_param(heartbeat, int, 0);
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MODULE_PARM_DESC(heartbeat,
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"Watchdog heartbeats in seconds. (default = "
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__MODULE_STRING(WDT_HEARTBEAT) ")");
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static int tegra_wdt_start(struct watchdog_device *wdd)
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{
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struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
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u32 val;
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/*
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* This thing has a fixed 1MHz clock. Normally, we would set the
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* period to 1 second by writing 1000000ul, but the watchdog system
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* reset actually occurs on the 4th expiration of this counter,
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* so we set the period to 1/4 of this amount.
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*/
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val = 1000000ul / 4;
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val |= (TIMER_EN | TIMER_PERIODIC);
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writel(val, wdt->tmr_regs + TIMER_PTV);
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/*
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* Set number of periods and start counter.
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*
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* Interrupt handler is not required for user space
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* WDT accesses, since the caller is responsible to ping the
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* WDT to reset the counter before expiration, through ioctls.
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*/
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val = WDT_TIMER_ID |
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(wdd->timeout << WDT_CFG_PERIOD_SHIFT) |
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WDT_CFG_PMC2CAR_RST_EN;
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writel(val, wdt->wdt_regs + WDT_CFG);
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writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
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return 0;
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}
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static int tegra_wdt_stop(struct watchdog_device *wdd)
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{
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struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
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writel(WDT_UNLOCK_PATTERN, wdt->wdt_regs + WDT_UNLOCK);
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writel(WDT_CMD_DISABLE_COUNTER, wdt->wdt_regs + WDT_CMD);
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writel(0, wdt->tmr_regs + TIMER_PTV);
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return 0;
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}
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static int tegra_wdt_ping(struct watchdog_device *wdd)
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{
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struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
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writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
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return 0;
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}
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static int tegra_wdt_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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wdd->timeout = timeout;
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if (watchdog_active(wdd))
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return tegra_wdt_start(wdd);
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return 0;
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}
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static unsigned int tegra_wdt_get_timeleft(struct watchdog_device *wdd)
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{
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struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
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u32 val;
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int count;
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int exp;
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val = readl(wdt->wdt_regs + WDT_STS);
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/* Current countdown (from timeout) */
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count = (val >> WDT_STS_COUNT_SHIFT) & WDT_STS_COUNT_MASK;
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/* Number of expirations (we are waiting for the 4th expiration) */
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exp = (val >> WDT_STS_EXP_SHIFT) & WDT_STS_EXP_MASK;
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/*
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* The entire thing is divided by 4 because we are ticking down 4 times
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* faster due to needing to wait for the 4th expiration.
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*/
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return (((3 - exp) * wdd->timeout) + count) / 4;
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}
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static const struct watchdog_info tegra_wdt_info = {
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.options = WDIOF_SETTIMEOUT |
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WDIOF_MAGICCLOSE |
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WDIOF_KEEPALIVEPING,
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.firmware_version = 0,
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.identity = "Tegra Watchdog",
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};
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static struct watchdog_ops tegra_wdt_ops = {
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.owner = THIS_MODULE,
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.start = tegra_wdt_start,
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.stop = tegra_wdt_stop,
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.ping = tegra_wdt_ping,
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.set_timeout = tegra_wdt_set_timeout,
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.get_timeleft = tegra_wdt_get_timeleft,
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};
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static int tegra_wdt_probe(struct platform_device *pdev)
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{
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struct watchdog_device *wdd;
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struct tegra_wdt *wdt;
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struct resource *res;
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void __iomem *regs;
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int ret;
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/* This is the timer base. */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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/*
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* Allocate our watchdog driver data, which has the
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* struct watchdog_device nested within it.
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*/
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wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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/* Initialize struct tegra_wdt. */
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wdt->wdt_regs = regs + WDT_BASE;
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wdt->tmr_regs = regs + WDT_TIMER_BASE;
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/* Initialize struct watchdog_device. */
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wdd = &wdt->wdd;
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wdd->timeout = heartbeat;
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wdd->info = &tegra_wdt_info;
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wdd->ops = &tegra_wdt_ops;
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wdd->min_timeout = MIN_WDT_TIMEOUT;
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wdd->max_timeout = MAX_WDT_TIMEOUT;
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watchdog_set_drvdata(wdd, wdt);
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watchdog_set_nowayout(wdd, nowayout);
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ret = watchdog_register_device(wdd);
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if (ret) {
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dev_err(&pdev->dev,
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"failed to register watchdog device\n");
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return ret;
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}
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platform_set_drvdata(pdev, wdt);
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dev_info(&pdev->dev,
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"initialized (heartbeat = %d sec, nowayout = %d)\n",
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heartbeat, nowayout);
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return 0;
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}
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static int tegra_wdt_remove(struct platform_device *pdev)
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{
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struct tegra_wdt *wdt = platform_get_drvdata(pdev);
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tegra_wdt_stop(&wdt->wdd);
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watchdog_unregister_device(&wdt->wdd);
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dev_info(&pdev->dev, "removed wdt\n");
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int tegra_wdt_runtime_suspend(struct device *dev)
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{
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struct tegra_wdt *wdt = dev_get_drvdata(dev);
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if (watchdog_active(&wdt->wdd))
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tegra_wdt_stop(&wdt->wdd);
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return 0;
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}
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static int tegra_wdt_runtime_resume(struct device *dev)
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{
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struct tegra_wdt *wdt = dev_get_drvdata(dev);
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if (watchdog_active(&wdt->wdd))
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tegra_wdt_start(&wdt->wdd);
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return 0;
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}
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#endif
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static const struct of_device_id tegra_wdt_of_match[] = {
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{ .compatible = "nvidia,tegra30-timer", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, tegra_wdt_of_match);
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static const struct dev_pm_ops tegra_wdt_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(tegra_wdt_runtime_suspend,
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tegra_wdt_runtime_resume)
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};
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static struct platform_driver tegra_wdt_driver = {
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.probe = tegra_wdt_probe,
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.remove = tegra_wdt_remove,
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.driver = {
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.owner = THIS_MODULE,
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.name = "tegra-wdt",
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.pm = &tegra_wdt_pm_ops,
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.of_match_table = tegra_wdt_of_match,
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},
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};
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module_platform_driver(tegra_wdt_driver);
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MODULE_AUTHOR("NVIDIA Corporation");
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MODULE_DESCRIPTION("Tegra Watchdog Driver");
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MODULE_LICENSE("GPL v2");
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