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MIPS: Remove unused R8000 CPU support

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Our R8000 CPU support can only be included if a system selects
CONFIG_SYS_HAS_CPU_R8000. No system does, making all R8000-related CPU
support dead code. Remove it.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
This commit is contained in:
Paul Burton
2019-07-22 22:00:03 +00:00
parent ccd51b9fc3
commit c2aeaaea17
10 changed files with 5 additions and 293 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
arch/mips/Kconfig
View File

@@ -1652,16 +1652,6 @@ config CPU_NEVADA
help help
QED / PMC-Sierra RM52xx-series ("Nevada") processors. QED / PMC-Sierra RM52xx-series ("Nevada") processors.
config CPU_R8000
bool "R8000"
depends on SYS_HAS_CPU_R8000
select CPU_HAS_PREFETCH
select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_64BIT_KERNEL
help
MIPS Technologies R8000 processors. Note these processors are
uncommon and the support for them is incomplete.
config CPU_R10000 config CPU_R10000
bool "R10000" bool "R10000"
depends on SYS_HAS_CPU_R10000 depends on SYS_HAS_CPU_R10000
@@ -1969,9 +1959,6 @@ config SYS_HAS_CPU_R5500
config SYS_HAS_CPU_NEVADA config SYS_HAS_CPU_NEVADA
bool bool
config SYS_HAS_CPU_R8000
bool
config SYS_HAS_CPU_R10000 config SYS_HAS_CPU_R10000
bool bool
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
@@ -2172,13 +2159,13 @@ config PAGE_SIZE_4KB
config PAGE_SIZE_8KB config PAGE_SIZE_8KB
bool "8kB" bool "8kB"
depends on CPU_R8000 || CPU_CAVIUM_OCTEON depends on CPU_CAVIUM_OCTEON
depends on !MIPS_VA_BITS_48 depends on !MIPS_VA_BITS_48
help help
Using 8kB page size will result in higher performance kernel at Using 8kB page size will result in higher performance kernel at
the price of higher memory consumption. This option is available the price of higher memory consumption. This option is available
only on R8000 and cnMIPS processors. Note that you will need a only on cnMIPS processors. Note that you will need a suitable Linux
suitable Linux distribution to support this. distribution to support this.
config PAGE_SIZE_16KB config PAGE_SIZE_16KB
bool "16kB" bool "16kB"
@@ -2269,7 +2256,7 @@ config CPU_HAS_PREFETCH
config CPU_GENERIC_DUMP_TLB config CPU_GENERIC_DUMP_TLB
bool bool
default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX) default y if !(CPU_R3000 || CPU_TX39XX)
config MIPS_FP_SUPPORT config MIPS_FP_SUPPORT
bool "Floating Point support" if EXPERT bool "Floating Point support" if EXPERT
@@ -2298,7 +2285,7 @@ config CPU_R4K_FPU
config CPU_R4K_CACHE_TLB config CPU_R4K_CACHE_TLB
bool bool
default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON) default y if !(CPU_R3000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
config MIPS_MT_SMP config MIPS_MT_SMP
bool "MIPS MT SMP support (1 TC on each available VPE)" bool "MIPS MT SMP support (1 TC on each available VPE)"
@@ -2555,7 +2542,6 @@ config CPU_R4400_WORKAROUNDS
config MIPS_ASID_SHIFT config MIPS_ASID_SHIFT
int int
default 6 if CPU_R3000 || CPU_TX39XX default 6 if CPU_R3000 || CPU_TX39XX
default 4 if CPU_R8000
default 0 default 0
config MIPS_ASID_BITS config MIPS_ASID_BITS

1
arch/mips/Makefile
View File

@@ -183,7 +183,6 @@ cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \
-Wa,--trap -Wa,--trap
cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx) cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx)
cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d) cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d)
cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap
cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \
-Wa,--trap -Wa,--trap
cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap

9
arch/mips/include/asm/addrspace.h
View File

@@ -135,18 +135,9 @@
*/ */
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
#ifndef CONFIG_CPU_R8000
/*
* The R8000 doesn't have the 32-bit compat spaces so we don't define them
* in order to catch bugs in the source code.
*/
#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) #define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
#endif
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) #define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) #define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)

4
arch/mips/include/asm/cpu-type.h
View File

@@ -146,10 +146,6 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_NEVADA: case CPU_NEVADA:
#endif #endif
#ifdef CONFIG_SYS_HAS_CPU_R8000
case CPU_R8000:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R10000 #ifdef CONFIG_SYS_HAS_CPU_R10000
case CPU_R10000: case CPU_R10000:
case CPU_R12000: case CPU_R12000:

5
arch/mips/include/asm/cpu.h
View File

@@ -300,11 +300,6 @@ enum cpu_type_enum {
CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
CPU_SR71000, CPU_TX49XX, CPU_SR71000, CPU_TX49XX,
/*
* R8000 class processors
*/
CPU_R8000,
/* /*
* TX3900 class processors * TX3900 class processors
*/ */

2
arch/mips/include/asm/module.h
View File

@@ -113,8 +113,6 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "R5500 " #define MODULE_PROC_FAMILY "R5500 "
#elif defined CONFIG_CPU_NEVADA #elif defined CONFIG_CPU_NEVADA
#define MODULE_PROC_FAMILY "NEVADA " #define MODULE_PROC_FAMILY "NEVADA "
#elif defined CONFIG_CPU_R8000
#define MODULE_PROC_FAMILY "R8000 "
#elif defined CONFIG_CPU_R10000 #elif defined CONFIG_CPU_R10000
#define MODULE_PROC_FAMILY "R10000 " #define MODULE_PROC_FAMILY "R10000 "
#elif defined CONFIG_CPU_RM7000 #elif defined CONFIG_CPU_RM7000

9
arch/mips/kernel/cpu-probe.c
View File

@@ -1491,15 +1491,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
*/ */
c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
break; break;
case PRID_IMP_R8000:
c->cputype = CPU_R8000;
__cpu_name[cpu] = "RM8000";
set_isa(c, MIPS_CPU_ISA_IV);
c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_LLSC;
c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
break;
case PRID_IMP_R10000: case PRID_IMP_R10000:
c->cputype = CPU_R10000; c->cputype = CPU_R10000;
__cpu_name[cpu] = "R10000"; __cpu_name[cpu] = "R10000";

1
arch/mips/mm/Makefile
View File

@@ -30,7 +30,6 @@ obj-$(CONFIG_DMA_NONCOHERENT) += dma-noncoherent.o
obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o
obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o
obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o

239
arch/mips/mm/tlb-r8k.c
View File

@@ -1,239 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
*/
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
extern void build_tlb_refill_handler(void);
#define TFP_TLB_SIZE 384
#define TFP_TLB_SET_SHIFT 7
/* CP0 hazard avoidance. */
#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
"nop; nop; nop; nop; nop; nop;\n\t" \
".set reorder\n\t")
void local_flush_tlb_all(void)
{
unsigned long flags;
unsigned long old_ctx;
int entry;
local_irq_save(flags);
/* Save old context and create impossible VPN2 value */
old_ctx = read_c0_entryhi();
write_c0_entrylo(0);
for (entry = 0; entry < TFP_TLB_SIZE; entry++) {
write_c0_tlbset(entry >> TFP_TLB_SET_SHIFT);
write_c0_vaddr(entry << PAGE_SHIFT);
write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
mtc0_tlbw_hazard();
tlb_write();
}
tlbw_use_hazard();
write_c0_entryhi(old_ctx);
local_irq_restore(flags);
}
void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
struct mm_struct *mm = vma->vm_mm;
int cpu = smp_processor_id();
unsigned long flags;
int oldpid, newpid, size;
if (!cpu_context(cpu, mm))
return;
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
size = (size + 1) >> 1;
local_irq_save(flags);
if (size > TFP_TLB_SIZE / 2) {
drop_mmu_context(mm);
goto out_restore;
}
oldpid = read_c0_entryhi();
newpid = cpu_asid(cpu, mm);
write_c0_entrylo(0);
start &= PAGE_MASK;
end += (PAGE_SIZE - 1);
end &= PAGE_MASK;
while (start < end) {
signed long idx;
write_c0_vaddr(start);
write_c0_entryhi(start);
start += PAGE_SIZE;
tlb_probe();
idx = read_c0_tlbset();
if (idx < 0)
continue;
write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
tlb_write();
}
write_c0_entryhi(oldpid);
out_restore:
local_irq_restore(flags);
}
/* Usable for KV1 addresses only! */
void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
unsigned long size, flags;
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
size = (size + 1) >> 1;
if (size > TFP_TLB_SIZE / 2) {
local_flush_tlb_all();
return;
}
local_irq_save(flags);
write_c0_entrylo(0);
start &= PAGE_MASK;
end += (PAGE_SIZE - 1);
end &= PAGE_MASK;
while (start < end) {
signed long idx;
write_c0_vaddr(start);
write_c0_entryhi(start);
start += PAGE_SIZE;
tlb_probe();
idx = read_c0_tlbset();
if (idx < 0)
continue;
write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
tlb_write();
}
local_irq_restore(flags);
}
void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
int cpu = smp_processor_id();
unsigned long flags;
int oldpid, newpid;
signed long idx;
if (!cpu_context(cpu, vma->vm_mm))
return;
newpid = cpu_asid(cpu, vma->vm_mm);
page &= PAGE_MASK;
local_irq_save(flags);
oldpid = read_c0_entryhi();
write_c0_vaddr(page);
write_c0_entryhi(newpid);
tlb_probe();
idx = read_c0_tlbset();
if (idx < 0)
goto finish;
write_c0_entrylo(0);
write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
tlb_write();
finish:
write_c0_entryhi(oldpid);
local_irq_restore(flags);
}
/*
* We will need multiple versions of update_mmu_cache(), one that just
* updates the TLB with the new pte(s), and another which also checks
* for the R4k "end of page" hardware bug and does the needy.
*/
void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
{
unsigned long flags;
pgd_t *pgdp;
pmd_t *pmdp;
pte_t *ptep;
int pid;
/*
* Handle debugger faulting in for debugee.
*/
if (current->active_mm != vma->vm_mm)
return;
pid = read_c0_entryhi() & cpu_asid_mask(&current_cpu_data);
local_irq_save(flags);
address &= PAGE_MASK;
write_c0_vaddr(address);
write_c0_entryhi(pid);
pgdp = pgd_offset(vma->vm_mm, address);
pmdp = pmd_offset(pgdp, address);
ptep = pte_offset_map(pmdp, address);
tlb_probe();
write_c0_entrylo(pte_val(*ptep++) >> 6);
tlb_write();
write_c0_entryhi(pid);
local_irq_restore(flags);
}
static void probe_tlb(unsigned long config)
{
struct cpuinfo_mips *c = &current_cpu_data;
c->tlbsize = 3 * 128; /* 3 sets each 128 entries */
}
void tlb_init(void)
{
unsigned int config = read_c0_config();
unsigned long status;
probe_tlb(config);
status = read_c0_status();
status &= ~(ST0_UPS | ST0_KPS);
#ifdef CONFIG_PAGE_SIZE_4KB
status |= (TFP_PAGESIZE_4K << 32) | (TFP_PAGESIZE_4K << 36);
#elif defined(CONFIG_PAGE_SIZE_8KB)
status |= (TFP_PAGESIZE_8K << 32) | (TFP_PAGESIZE_8K << 36);
#elif defined(CONFIG_PAGE_SIZE_16KB)
status |= (TFP_PAGESIZE_16K << 32) | (TFP_PAGESIZE_16K << 36);
#elif defined(CONFIG_PAGE_SIZE_64KB)
status |= (TFP_PAGESIZE_64K << 32) | (TFP_PAGESIZE_64K << 36);
#endif
write_c0_status(status);
write_c0_wired(0);
local_flush_tlb_all();
build_tlb_refill_handler();
}

4
arch/mips/mm/tlbex.c
View File

@@ -2633,10 +2633,6 @@ void build_tlb_refill_handler(void)
#endif #endif
break; break;
case CPU_R8000:
panic("No R8000 TLB refill handler yet");
break;
default: default:
if (cpu_has_ldpte) if (cpu_has_ldpte)
setup_pw(); setup_pw();