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dt-bindings: switch Exynos EHCI/OHCI bindings to use array of generic PHYs

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Commit 69bec72598 ("USB: core: let USB device know device node") added
support for attaching devicetree node for USB devices. Those nodes are
children of their USB host controller. However Exynos EHCI and OHCI
driver bindings already define child-nodes for each physical root hub
port and assigns respective PHY controller and parameters to them. This
leads to the conflict. A workaround for it has been merged as commit
01d4071486 ("usb: exynos: add workaround for the USB device bindings
conflict"), but it disabled support for USB device binding for Exynos
EHCI/OHCI controllers.

To resolve it properly, lets move PHYs from the sub-nodes to a standard
array under the 'phys' property.

Suggested-by: Måns Rullgård <mans@mansr.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20190726081453.9456-2-m.szyprowski@samsung.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Marek Szyprowski 2019-07-26 10:14:51 +02:00 committed by Greg Kroah-Hartman
parent 2a0f4f16d2
commit c27989cc53
1 changed files with 14 additions and 27 deletions
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41
Documentation/devicetree/bindings/usb/exynos-usb.txt
View File

@ -12,13 +12,11 @@ Required properties:
- interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost".
- port: if in the SoC there are EHCI phys, they should be listed here.
One phy per port. Each port should have following entries:
- reg: port number on EHCI controller, e.g
On Exynos5250, port 0 is USB2.0 otg phy
port 1 is HSIC phy0
port 2 is HSIC phy1
- phys: from the *Generic PHY* bindings; specifying phy used by port.
- phys: from the *Generic PHY* bindings; array specifying phy(s) used
by the root port.
- phy-names: from the *Generic PHY* bindings; array of the names for
each phy for the root ports, must be a subset of the following:
"host", "hsic0", "hsic1".
Optional properties:
- samsung,vbus-gpio: if present, specifies the GPIO that
@ -35,12 +33,8 @@ Example:
clocks = <&clock 285>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2phy 1>;
};
phys = <&usb2phy 1>;
phy-names = "host";
};
OHCI
@ -52,13 +46,11 @@ Required properties:
- interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost".
- port: if in the SoC there are OHCI phys, they should be listed here.
One phy per port. Each port should have following entries:
- reg: port number on OHCI controller, e.g
On Exynos5250, port 0 is USB2.0 otg phy
port 1 is HSIC phy0
port 2 is HSIC phy1
- phys: from the *Generic PHY* bindings, specifying phy used by port.
- phys: from the *Generic PHY* bindings; array specifying phy(s) used
by the root port.
- phy-names: from the *Generic PHY* bindings; array of the names for
each phy for the root ports, must be a subset of the following:
"host", "hsic0", "hsic1".
Example:
usb@12120000 {
@ -69,13 +61,8 @@ Example:
clocks = <&clock 285>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2phy 1>;
};
phys = <&usb2phy 1>;
phy-names = "host";
};
DWC3