cpufreq: tegra: Changes for v5.5-rc1

Implements support for suspend/resume on Tegra124.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl29kX8THHRyZWRpbmdA
 bnZpZGlhLmNvbQAKCRDdI6zXfz6zocRwD/4sUOisLpfjLSt4cwAVOQAq0EQkhb7q
 5pP93JM2i0iBjlTphGL/g+vZM6Lc4kZQ764TFQZWSvLE3N0dhHRRgkmLDdbozm1d
 JHt6dc93Qu32zFjxUJbi2t6XWnviD9bYX7Ta26P97RQyb4XKbSPc5yCZ1FYZKAW+
 /wlEJU6QdfQ19T2rJAPS49lVLuZTRMupSEv0aE5S27W66RtuYdzqCVjPLmUIooGl
 vynNxOrdnEWG53H68fCN683Gm7ODgbCq66kj3SRP8164sjaV8KIbWcAMDEs6LgPn
 Sm6U8HZVCmskV4OxZLKFSLFiYeb1DgCI7ArU2BWYqpIeJbL0zNuRTihgUAc6yN88
 ncq6H/TaHyMyb6MC/91tdXe4Phsx4BW2aqaZenSRcGPQ2o40S4DY+ONjVAgT9d5/
 ZDekSWSlz3kGUPeVc47Tiy9GMGGnkNYRf1W0Jrb31/+Aaay9jstC6ahcEWw6B65b
 jle2fdH25NhmqXWC145zDJqBRAtMkKO01UT6YXbY8fb2aq+9u4STi0Fq5EiElLCL
 n+XJ3m+EfE65/GdtRqvuGZowVD82PdmQze+b7WDudB48gow1qscjurfIkilz2VVe
 kE5tVTRMrJpgBh5GlqMj05qsIuQ9ZCwBGYGuWZdICnl9eD3Bmoe8jO7Tq4GkIA08
 NbK5TTcP34ZjQg==
 =1y1w
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-5.5-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes

cpufreq: tegra: Changes for v5.5-rc1

Implements support for suspend/resume on Tegra124.

* tag 'tegra-for-5.5-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  cpufreq: tegra124: Add suspend and resume support

Link: https://lore.kernel.org/r/20191204130753.3614278-3-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-12-06 08:28:11 -08:00
commit c25f318b1f

View File

@ -6,6 +6,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
@ -128,8 +129,66 @@ out_put_np:
return ret;
}
static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev)
{
struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
int err;
/*
* PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to
* use during suspend and resume. So, switch the CPU clock source
* to PLLP and disable DFLL.
*/
err = clk_set_parent(priv->cpu_clk, priv->pllp_clk);
if (err < 0) {
dev_err(dev, "failed to reparent to PLLP: %d\n", err);
return err;
}
clk_disable_unprepare(priv->dfll_clk);
return 0;
}
static int __maybe_unused tegra124_cpufreq_resume(struct device *dev)
{
struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
int err;
/*
* Warmboot code powers up the CPU with PLLP clock source.
* Enable DFLL clock and switch CPU clock source back to DFLL.
*/
err = clk_prepare_enable(priv->dfll_clk);
if (err < 0) {
dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err);
goto disable_cpufreq;
}
err = clk_set_parent(priv->cpu_clk, priv->dfll_clk);
if (err < 0) {
dev_err(dev, "failed to reparent to DFLL clock: %d\n", err);
goto disable_dfll;
}
return 0;
disable_dfll:
clk_disable_unprepare(priv->dfll_clk);
disable_cpufreq:
disable_cpufreq();
return err;
}
static const struct dev_pm_ops tegra124_cpufreq_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend,
tegra124_cpufreq_resume)
};
static struct platform_driver tegra124_cpufreq_platdrv = {
.driver.name = "cpufreq-tegra124",
.driver.pm = &tegra124_cpufreq_pm_ops,
.probe = tegra124_cpufreq_probe,
};