forked from Minki/linux
drm/i915: factor out valleyview_pipestat_irq_handler
This will be used by other platforms too, so factor it out. The only functional change is the reordeing of gmbus_irq_handler() wrt. the hotplug handling, but since it only schedules a work, it isn't an issue. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Don't keep on using the private_t typedef.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1477,15 +1477,53 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
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}
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}
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}
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}
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static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pipe_stats[I915_MAX_PIPES];
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unsigned long irqflags;
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int pipe;
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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for_each_pipe(pipe) {
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int reg = PIPESTAT(pipe);
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pipe_stats[pipe] = I915_READ(reg);
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/*
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* Clear the PIPE*STAT regs before the IIR
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*/
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if (pipe_stats[pipe] & 0x8000ffff)
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I915_WRITE(reg, pipe_stats[pipe]);
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}
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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for_each_pipe(pipe) {
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if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
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drm_handle_vblank(dev, pipe);
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if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
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intel_prepare_page_flip(dev, pipe);
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intel_finish_page_flip(dev, pipe);
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}
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if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
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i9xx_pipe_crc_irq_handler(dev, pipe);
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if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
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DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
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}
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if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
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gmbus_irq_handler(dev);
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}
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static irqreturn_t valleyview_irq_handler(int irq, void *arg)
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static irqreturn_t valleyview_irq_handler(int irq, void *arg)
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{
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{
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struct drm_device *dev = (struct drm_device *) arg;
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struct drm_device *dev = (struct drm_device *) arg;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 iir, gt_iir, pm_iir;
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u32 iir, gt_iir, pm_iir;
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irqreturn_t ret = IRQ_NONE;
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irqreturn_t ret = IRQ_NONE;
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unsigned long irqflags;
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int pipe;
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u32 pipe_stats[I915_MAX_PIPES];
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while (true) {
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while (true) {
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iir = I915_READ(VLV_IIR);
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iir = I915_READ(VLV_IIR);
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@ -1499,35 +1537,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
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snb_gt_irq_handler(dev, dev_priv, gt_iir);
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snb_gt_irq_handler(dev, dev_priv, gt_iir);
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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valleyview_pipestat_irq_handler(dev, iir);
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for_each_pipe(pipe) {
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int reg = PIPESTAT(pipe);
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pipe_stats[pipe] = I915_READ(reg);
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/*
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* Clear the PIPE*STAT regs before the IIR
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*/
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if (pipe_stats[pipe] & 0x8000ffff)
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I915_WRITE(reg, pipe_stats[pipe]);
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}
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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for_each_pipe(pipe) {
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if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
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drm_handle_vblank(dev, pipe);
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if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
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intel_prepare_page_flip(dev, pipe);
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intel_finish_page_flip(dev, pipe);
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}
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if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
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i9xx_pipe_crc_irq_handler(dev, pipe);
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if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
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DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
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}
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/* Consume port. Then clear IIR or we'll miss events */
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/* Consume port. Then clear IIR or we'll miss events */
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if (iir & I915_DISPLAY_PORT_INTERRUPT) {
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if (iir & I915_DISPLAY_PORT_INTERRUPT) {
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@ -1543,8 +1553,6 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
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I915_READ(PORT_HOTPLUG_STAT);
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I915_READ(PORT_HOTPLUG_STAT);
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}
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}
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if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
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gmbus_irq_handler(dev);
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if (pm_iir)
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if (pm_iir)
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gen6_rps_irq_handler(dev_priv, pm_iir);
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gen6_rps_irq_handler(dev_priv, pm_iir);
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