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clk/tegra: Changes for v4.1-rc1

Browse Source 
These are mostly cleanups that I've been carrying in my local tree for
 far too long. In addition to those, there are some preparatory patches
 for the upcoming Tegra210 support and a patch to enable clocks needed
 for HDMI audio support.
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Merge tag 'clk/for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next

clk/tegra: Changes for v4.1-rc1

These are mostly cleanups that I've been carrying in my local tree for
far too long. In addition to those, there are some preparatory patches
for the upcoming Tegra210 support and a patch to enable clocks needed
for HDMI audio support.
This commit is contained in:
Michael Turquette 2015-04-10 18:06:55 -07:00
commit c14deee398
9 changed files with 70 additions and 72 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/clk/tegra/clk-pll.c
View File

@ -981,7 +981,7 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
struct tegra_clk_pll *pll = to_clk_pll(hw);
struct tegra_clk_pll_freq_table cfg, old_cfg;
unsigned long flags = 0;
int ret = 0;
int ret;
ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
if (ret < 0)
@ -1005,7 +1005,7 @@ static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct tegra_clk_pll_freq_table cfg;
int ret = 0, p_div;
int ret, p_div;
u64 output_rate = *prate;
ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
@ -1073,7 +1073,7 @@ static int clk_pllc_enable(struct clk_hw *hw)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
u32 val;
int ret = 0;
int ret;
unsigned long flags = 0;
if (pll->lock)
@ -1223,6 +1223,7 @@ static long _pllre_calc_rate(struct tegra_clk_pll *pll,
return output_rate;
}
static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{

24
drivers/clk/tegra/clk-tegra-fixed.c
View File

@ -30,13 +30,12 @@
#define OSC_CTRL_OSC_FREQ_SHIFT 28
#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
int __init tegra_osc_clk_init(void __iomem *clk_base,
struct tegra_clk *tegra_clks,
unsigned long *input_freqs, int num,
unsigned long *osc_freq,
unsigned long *pll_ref_freq)
int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
unsigned long *input_freqs, unsigned int num,
unsigned int clk_m_div, unsigned long *osc_freq,
unsigned long *pll_ref_freq)
{
struct clk *clk;
struct clk *clk, *osc;
struct clk **dt_clk;
u32 val, pll_ref_div;
unsigned osc_idx;
@ -54,22 +53,25 @@ int __init tegra_osc_clk_init(void __iomem *clk_base,
return -EINVAL;
}
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, tegra_clks);
osc = clk_register_fixed_rate(NULL, "osc", NULL, CLK_IS_ROOT,
*osc_freq);
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
if (!dt_clk)
return 0;
clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
*osc_freq);
clk = clk_register_fixed_factor(NULL, "clk_m", "osc",
0, 1, clk_m_div);
*dt_clk = clk;
/* pll_ref */
val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
pll_ref_div = 1 << val;
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, tegra_clks);
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks);
if (!dt_clk)
return 0;
clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",
0, 1, pll_ref_div);
*dt_clk = clk;

2
drivers/clk/tegra/clk-tegra-periph.c
View File

@ -218,7 +218,7 @@
.clk_id = _clk_id, \
.p.parent_name = _parent_name, \
.periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \
_clk_num, _gate_flags, 0, NULL), \
_clk_num, _gate_flags, NULL, NULL), \
.flags = _flags \
}

36
drivers/clk/tegra/clk-tegra114.c
View File

@ -940,36 +940,6 @@ static struct clk **clks;
static unsigned long osc_freq;
static unsigned long pll_ref_freq;
static int __init tegra114_osc_clk_init(void __iomem *clk_base)
{
struct clk *clk;
u32 val, pll_ref_div;
val = readl_relaxed(clk_base + OSC_CTRL);
osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];
if (!osc_freq) {
WARN_ON(1);
return -EINVAL;
}
/* clk_m */
clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
osc_freq);
clks[TEGRA114_CLK_CLK_M] = clk;
/* pll_ref */
val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
pll_ref_div = 1 << val;
clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
CLK_SET_RATE_PARENT, 1, pll_ref_div);
clks[TEGRA114_CLK_PLL_REF] = clk;
pll_ref_freq = osc_freq / pll_ref_div;
return 0;
}
static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
{
struct clk *clk;
@ -1263,6 +1233,7 @@ static void tegra114_wait_cpu_in_reset(u32 cpu)
cpu_relax();
} while (!(reg & (1 << cpu))); /* check CPU been reset or not */
}
static void tegra114_disable_cpu_clock(u32 cpu)
{
/* flow controller would take care in the power sequence. */
@ -1351,7 +1322,6 @@ static void __init tegra114_clock_apply_init_table(void)
tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
}
/**
* tegra114_car_barrier - wait for pending writes to the CAR to complete
*
@ -1505,7 +1475,9 @@ static void __init tegra114_clock_init(struct device_node *np)
if (!clks)
return;
if (tegra114_osc_clk_init(clk_base) < 0)
if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,
ARRAY_SIZE(tegra114_input_freq), 1, &osc_freq,
&pll_ref_freq) < 0)
return;
tegra114_fixed_clk_init(clk_base);

22
drivers/clk/tegra/clk-tegra124.c
View File

@ -1014,6 +1014,9 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
{ .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
{ .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
{ .con_id = "hda", .dt_id = TEGRA124_CLK_HDA },
{ .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X },
{ .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },
};
static struct clk **clks;
@ -1110,16 +1113,18 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1, 2);
clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0,
clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
clks[TEGRA124_CLK_PLLD_DSI] = clk;
clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;
clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base,
0, 48, periph_clk_enb_refcnt);
clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
clk_base, 0, 48,
periph_clk_enb_refcnt);
clks[TEGRA124_CLK_DSIA] = clk;
clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base,
0, 82, periph_clk_enb_refcnt);
clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
clk_base, 0, 82,
periph_clk_enb_refcnt);
clks[TEGRA124_CLK_DSIB] = clk;
/* emc mux */
@ -1395,6 +1400,8 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
{TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
{TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
{TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0},
{TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0},
/* This MUST be the last entry. */
{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
};
@ -1475,7 +1482,8 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
return;
if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
ARRAY_SIZE(tegra124_input_freq), &osc_freq, &pll_ref_freq) < 0)
ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq,
&pll_ref_freq) < 0)
return;
tegra_fixed_clk_init(tegra124_clks);

23
drivers/clk/tegra/clk-tegra30.c
View File

@ -657,16 +657,16 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
{ .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
{ .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
{ .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
{ .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
{ .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
{ .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
{ .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
{ .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
{ .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
{ .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
{ .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
{ .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
{ .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
{ .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
{ .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
{ .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
{ .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
{ .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
{ .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
{ .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
{ .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
{ .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
{ .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
{ .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
{ .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
@ -1434,7 +1434,8 @@ static void __init tegra30_clock_init(struct device_node *np)
return;
if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
ARRAY_SIZE(tegra30_input_freq), &input_freq, NULL) < 0)
ARRAY_SIZE(tegra30_input_freq), 1, &input_freq,
NULL) < 0)
return;

16
drivers/clk/tegra/clk.c
View File

@ -30,6 +30,7 @@
#define CLK_OUT_ENB_V 0x360
#define CLK_OUT_ENB_W 0x364
#define CLK_OUT_ENB_X 0x280
#define CLK_OUT_ENB_Y 0x298
#define CLK_OUT_ENB_SET_L 0x320
#define CLK_OUT_ENB_CLR_L 0x324
#define CLK_OUT_ENB_SET_H 0x328
@ -42,6 +43,8 @@
#define CLK_OUT_ENB_CLR_W 0x44c
#define CLK_OUT_ENB_SET_X 0x284
#define CLK_OUT_ENB_CLR_X 0x288
#define CLK_OUT_ENB_SET_Y 0x29c
#define CLK_OUT_ENB_CLR_Y 0x2a0
#define RST_DEVICES_L 0x004
#define RST_DEVICES_H 0x008
@ -50,6 +53,7 @@
#define RST_DEVICES_V 0x358
#define RST_DEVICES_W 0x35C
#define RST_DEVICES_X 0x28C
#define RST_DEVICES_Y 0x2a4
#define RST_DEVICES_SET_L 0x300
#define RST_DEVICES_CLR_L 0x304
#define RST_DEVICES_SET_H 0x308
@ -62,6 +66,8 @@
#define RST_DEVICES_CLR_W 0x43c
#define RST_DEVICES_SET_X 0x290
#define RST_DEVICES_CLR_X 0x294
#define RST_DEVICES_SET_Y 0x2a8
#define RST_DEVICES_CLR_Y 0x2ac
/* Global data of Tegra CPU CAR ops */
static struct tegra_cpu_car_ops dummy_car_ops;
@ -122,6 +128,14 @@ static struct tegra_clk_periph_regs periph_regs[] = {
.rst_set_reg = RST_DEVICES_SET_X,
.rst_clr_reg = RST_DEVICES_CLR_X,
},
[6] = {
.enb_reg = CLK_OUT_ENB_Y,
.enb_set_reg = CLK_OUT_ENB_SET_Y,
.enb_clr_reg = CLK_OUT_ENB_CLR_Y,
.rst_reg = RST_DEVICES_Y,
.rst_set_reg = RST_DEVICES_SET_Y,
.rst_clr_reg = RST_DEVICES_CLR_Y,
},
};
static void __iomem *clk_base;
@ -272,7 +286,7 @@ void __init tegra_add_of_provider(struct device_node *np)
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
rst_ctlr.of_node = np;
rst_ctlr.nr_resets = clk_num * 32;
rst_ctlr.nr_resets = periph_banks * 32;
reset_controller_register(&rst_ctlr);
}

10
drivers/clk/tegra/clk.h
View File

@ -548,7 +548,7 @@ struct clk *tegra_clk_register_super_mux(const char *name,
u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
/**
* struct clk_init_tabel - clock initialization table
* struct clk_init_table - clock initialization table
* @clk_id: clock id as mentioned in device tree bindings
* @parent_id: parent clock id as mentioned in device tree bindings
* @rate: rate to set
@ -615,10 +615,10 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks,
unsigned long *input_freqs, int num,
unsigned long *osc_freq,
unsigned long *pll_ref_freq);
int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
unsigned long *input_freqs, unsigned int num,
unsigned int clk_m_div, unsigned long *osc_freq,
unsigned long *pll_ref_freq);
void tegra_super_clk_gen4_init(void __iomem *clk_base,
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
struct tegra_clk_pll_params *pll_params);

2
include/dt-bindings/clock/tegra124-car-common.h
View File

@ -297,7 +297,7 @@
#define TEGRA124_CLK_PLL_C4 270
#define TEGRA124_CLK_PLL_DP 271
#define TEGRA124_CLK_PLL_E_MUX 272
#define TEGRA124_CLK_PLLD_DSI 273
#define TEGRA124_CLK_PLL_D_DSI_OUT 273
/* 274 */
/* 275 */
/* 276 */