leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-next

Browse Source 
Fixes for 4.20.  Highlights:
- VCN DPG fixes for Picasso
- Add support for the latest vega20 vbios
- Scheduler timeout fix
- License fixes for radeon and amdgpu
- Misc other fixes

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181017215427.2804-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie 2018-10-18 12:05:08 +10:00
commit c13bbf4a78
23 changed files with 569 additions and 231 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
View File

@ -826,21 +826,13 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
{
struct drm_minor *minor = adev->ddev->primary;
struct dentry *ent, *root = minor->debugfs_root;
unsigned i, j;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
ent = debugfs_create_file(debugfs_regs_names[i],
S_IFREG | S_IRUGO, root,
adev, debugfs_regs[i]);
if (IS_ERR(ent)) {
for (j = 0; j < i; j++) {
debugfs_remove(adev->debugfs_regs[i]);
adev->debugfs_regs[i] = NULL;
}
return PTR_ERR(ent);
}
if (!i)
if (!i && !IS_ERR_OR_NULL(ent))
i_size_write(ent->d_inode, adev->rmmio_size);
adev->debugfs_regs[i] = ent;
}

2
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
View File

@ -574,7 +574,7 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
/* skip over VMID 0, since it is the system VM */
for (j = 1; j < id_mgr->num_ids; ++j) {
amdgpu_vmid_reset(adev, i, j);
amdgpu_sync_create(&id_mgr->ids[i].active);
amdgpu_sync_create(&id_mgr->ids[j].active);
list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
}
}

2
drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: MIT
/* Copyright Red Hat Inc 2010.
*
* Permission is hereby granted, free of charge, to any person obtaining a

16
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@ -97,6 +97,7 @@ MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
static const struct soc15_reg_golden golden_settings_gc_9_0[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
@ -4904,7 +4905,20 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
{
/* init asci gds info */
adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
switch (adev->asic_type) {
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
adev->gds.mem.total_size = 0x10000;
break;
case CHIP_RAVEN:
adev->gds.mem.total_size = 0x1000;
break;
default:
adev->gds.mem.total_size = 0x10000;
break;
}
adev->gds.gws.total_size = 64;
adev->gds.oa.total_size = 16;

2
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
View File

@ -148,6 +148,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xFE000000, 0x00000000),
};
static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
@ -177,6 +178,7 @@ static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xFE000000, 0x00000000),
};
static const struct soc15_reg_golden golden_settings_sdma_rv1[] =

292
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
View File

@ -37,6 +37,11 @@
#include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
#define mmUVD_RBC_XX_IB_REG_CHECK 0x05ab
#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1
#define mmUVD_REG_XX_MASK 0x05ac
#define mmUVD_REG_XX_MASK_BASE_IDX 1
static int vcn_v1_0_stop(struct amdgpu_device *adev);
static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
@ -320,6 +325,24 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
adev->gfx.config.gb_addr_config);
WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
}
static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
@ -371,16 +394,27 @@ static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
0xFFFFFFFF, 0);
/* VCN global tiling registers */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
}
/**
@ -743,41 +777,24 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
lmi_swap_cntl = 0;
vcn_1_0_disable_static_power_gating(adev);
tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
/* disable clock gating */
vcn_v1_0_disable_clock_gating(adev);
vcn_v1_0_mc_resume_spg_mode(adev);
/* disable interupt */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
~UVD_MASTINT_EN__VCPU_EN_MASK);
/* stall UMC and register bus before resetting VCPU */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
mdelay(1);
/* put LMI, VCPU, RBC etc... into reset */
WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
mdelay(5);
/* initialize VCN memory controller */
WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
(0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
UVD_LMI_CTRL__REQ_MODE_MASK |
0x00100000L);
tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
#ifdef __BIG_ENDIAN
/* swap (8 in 32) RB and IB */
@ -785,29 +802,49 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
#endif
WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040);
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0);
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040);
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0);
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0);
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88);
tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
/* take all subblocks out of reset, except VCPU */
WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
mdelay(5);
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
vcn_v1_0_mc_resume_spg_mode(adev);
WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK, 0x10);
WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK,
RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3);
/* enable VCPU clock */
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL,
UVD_VCPU_CNTL__CLK_EN_MASK);
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
/* boot up the VCPU */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
/* enable UMC */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
/* boot up the VCPU */
WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
mdelay(10);
tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
for (i = 0; i < 10; ++i) {
uint32_t status;
@ -839,24 +876,22 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
}
/* enable master interrupt */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
/* enable system interrupt for JRBC, TODO: move to set interrupt*/
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
/* clear the bit 4 of VCN_STATUS */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
/* clear the busy bit of UVD_STATUS */
tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
/* force RBC into idle state */
rb_bufsz = order_base_2(ring->ring_size);
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
@ -923,7 +958,7 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring = &adev->vcn.ring_dec;
uint32_t rb_bufsz, tmp, reg_data;
uint32_t rb_bufsz, tmp;
uint32_t lmi_swap_cntl;
/* disable byte swapping */
@ -932,47 +967,33 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
vcn_1_0_enable_static_power_gating(adev);
/* enable dynamic power gating mode */
reg_data = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
reg_data |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
reg_data |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data);
tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
/* enable clock gating */
vcn_v1_0_clock_gating_dpg_mode(adev, 0);
/* enable VCPU clock */
reg_data = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
reg_data |= UVD_VCPU_CNTL__CLK_EN_MASK;
reg_data |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, reg_data, 0xFFFFFFFF, 0);
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
/* disable interupt */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
/* stall UMC and register bus before resetting VCPU */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
/* put LMI, VCPU, RBC etc... into reset */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET,
UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
0xFFFFFFFF, 0);
/* initialize VCN memory controller */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
(0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
UVD_LMI_CTRL__REQ_MODE_MASK |
UVD_LMI_CTRL__CRC_RESET_MASK |
UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
0x00100000L, 0xFFFFFFFF, 0);
#ifdef __BIG_ENDIAN
@ -981,45 +1002,54 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
#endif
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_ALU, 0, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 0x88, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL,
0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0,
((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0,
((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX,
((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
vcn_v1_0_mc_resume_dpg_mode(adev);
/* take all subblocks out of reset, except VCPU */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET,
UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0xFFFFFFFF, 0);
/* enable VCPU clock */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL,
UVD_VCPU_CNTL__CLK_EN_MASK, 0xFFFFFFFF, 0);
/* enable UMC */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
/* boot up the VCPU */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
/* enable UMC */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
0xFFFFFFFF, 0);
/* enable master interrupt */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 0);
UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
vcn_v1_0_clock_gating_dpg_mode(adev, 1);
/* setup mmUVD_LMI_CTRL */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
(UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
UVD_LMI_CTRL__CRC_RESET_MASK |
UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
0x00100000L), 0xFFFFFFFF, 1);
(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
UVD_LMI_CTRL__REQ_MODE_MASK |
UVD_LMI_CTRL__CRC_RESET_MASK |
UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
0x00100000L, 0xFFFFFFFF, 1);
tmp = adev->gfx.config.gb_addr_config;
/* setup VCN global tiling registers */
@ -1035,7 +1065,6 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
@ -1095,28 +1124,39 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
*/
static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
{
/* force RBC into idle state */
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
int ret_code, tmp;
/* Stall UMC and register bus before resetting VCPU */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
mdelay(1);
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code);
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
UVD_LMI_STATUS__READ_CLEAN_MASK |
UVD_LMI_STATUS__WRITE_CLEAN_MASK |
UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
/* put VCPU into reset */
WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
mdelay(5);
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
/* disable VCPU clock */
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0);
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
~UVD_VCPU_CNTL__CLK_EN_MASK);
/* Unstall UMC and register bus */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
/* reset LMI UMC/LMI */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
vcn_v1_0_enable_clock_gating(adev);
vcn_1_0_enable_static_power_gating(adev);
@ -1125,13 +1165,23 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
{
int ret_code;
int ret_code = 0;
/* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
if (!ret_code) {
int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
/* wait for read ptr to be equal to write ptr */
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
}
/* disable dynamic power gating mode */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);

3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
View File

@ -705,7 +705,8 @@ int connector_debugfs_init(struct amdgpu_dm_connector *connector)
int i;
struct dentry *ent, *dir = connector->base.debugfs_entry;
if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
ent = debugfs_create_file(dp_debugfs_entries[i].name,
0644,

8
drivers/gpu/drm/amd/display/modules/color/color_gamma.c
View File

@ -1069,10 +1069,14 @@ static void build_evenly_distributed_points(
struct dividers dividers)
{
struct gamma_pixel *p = points;
struct gamma_pixel *p_last = p + numberof_points - 1;
struct gamma_pixel *p_last;
uint32_t i = 0;
// This function should not gets called with 0 as a parameter
ASSERT(numberof_points > 0);
p_last = p + numberof_points - 1;
do {
struct fixed31_32 value = dc_fixpt_from_fraction(i,
numberof_points - 1);
@ -1083,7 +1087,7 @@ static void build_evenly_distributed_points(
++p;
++i;
} while (i != numberof_points);
} while (i < numberof_points);
p->r = dc_fixpt_div(p_last->r, dividers.divider1);
p->g = dc_fixpt_div(p_last->g, dividers.divider1);

14
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
View File

@ -82,6 +82,18 @@
#define mmUVD_LCM_CGC_CNTRL 0x0123
#define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1
#define mmUVD_MIF_CURR_UV_ADDR_CONFIG 0x0184
#define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_REF_UV_ADDR_CONFIG 0x0185
#define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG 0x0186
#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_CURR_ADDR_CONFIG 0x0192
#define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_REF_ADDR_CONFIG 0x0193
#define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x01c5
#define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX 1
// addressBlock: uvd_uvdnpdec
// base address: 0x20000
@ -327,6 +339,8 @@
#define mmUVD_LMI_VM_CTRL_BASE_IDX 1
#define mmUVD_LMI_SWAP_CNTL 0x056d
#define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1
#define mmUVD_MPC_CNTL 0x0577
#define mmUVD_MPC_CNTL_BASE_IDX 1
#define mmUVD_MPC_SET_MUXA0 0x0579
#define mmUVD_MPC_SET_MUXA0_BASE_IDX 1
#define mmUVD_MPC_SET_MUXA1 0x057a

18
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
View File

@ -985,6 +985,7 @@
#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L
#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
@ -993,6 +994,7 @@
#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L
#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L
#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L
//UVD_MASTINT_EN
#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
@ -1045,6 +1047,19 @@
#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L
#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L
#define UVD_LMI_CTRL__RFU_MASK 0xF8000000L
//UVD_LMI_STATUS
#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L
#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L
#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L
#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L
#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L
#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L
//UVD_LMI_SWAP_CNTL
#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
@ -1078,6 +1093,9 @@
#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L
#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L
#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L
//UVD_MPC_CNTL
#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L
//UVD_MPC_SET_MUXA0
#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

88
drivers/gpu/drm/amd/include/atomfirmware.h
View File

@ -1532,6 +1532,94 @@ struct atom_smc_dpm_info_v4_3
uint32_t boardreserved[10];
};
struct smudpm_i2ccontrollerconfig_t {
uint32_t enabled;
uint32_t slaveaddress;
uint32_t controllerport;
uint32_t controllername;
uint32_t thermalthrottler;
uint32_t i2cprotocol;
uint32_t i2cspeed;
};
struct atom_smc_dpm_info_v4_4
{
struct atom_common_table_header table_header;
uint32_t i2c_padding[3];
uint16_t maxvoltagestepgfx;
uint16_t maxvoltagestepsoc;
uint8_t vddgfxvrmapping;
uint8_t vddsocvrmapping;
uint8_t vddmem0vrmapping;
uint8_t vddmem1vrmapping;
uint8_t gfxulvphasesheddingmask;
uint8_t soculvphasesheddingmask;
uint8_t externalsensorpresent;
uint8_t padding8_v;
uint16_t gfxmaxcurrent;
uint8_t gfxoffset;
uint8_t padding_telemetrygfx;
uint16_t socmaxcurrent;
uint8_t socoffset;
uint8_t padding_telemetrysoc;
uint16_t mem0maxcurrent;
uint8_t mem0offset;
uint8_t padding_telemetrymem0;
uint16_t mem1maxcurrent;
uint8_t mem1offset;
uint8_t padding_telemetrymem1;
uint8_t acdcgpio;
uint8_t acdcpolarity;
uint8_t vr0hotgpio;
uint8_t vr0hotpolarity;
uint8_t vr1hotgpio;
uint8_t vr1hotpolarity;
uint8_t padding1;
uint8_t padding2;
uint8_t ledpin0;
uint8_t ledpin1;
uint8_t ledpin2;
uint8_t padding8_4;
uint8_t pllgfxclkspreadenabled;
uint8_t pllgfxclkspreadpercent;
uint16_t pllgfxclkspreadfreq;
uint8_t uclkspreadenabled;
uint8_t uclkspreadpercent;
uint16_t uclkspreadfreq;
uint8_t fclkspreadenabled;
uint8_t fclkspreadpercent;
uint16_t fclkspreadfreq;
uint8_t fllgfxclkspreadenabled;
uint8_t fllgfxclkspreadpercent;
uint16_t fllgfxclkspreadfreq;
struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7];
uint32_t boardreserved[10];
};
/*
***************************************************************************
Data Table asic_profiling_info structure

9
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
View File

@ -894,9 +894,14 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
pr_info("%s was not implemented.\n", __func__);
return ret;
}
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
pr_info("power profile setting is for manual dpm mode only.\n");
return ret;
}
mutex_lock(&hwmgr->smu_lock);
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
mutex_unlock(&hwmgr->smu_lock);
return ret;
}

42
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
View File

@ -3175,6 +3175,34 @@ static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
return result;
}
static int conv_power_profile_to_pplib_workload(int power_profile)
{
int pplib_workload = 0;
switch (power_profile) {
case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
break;
case PP_SMC_POWER_PROFILE_POWERSAVING:
pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
break;
case PP_SMC_POWER_PROFILE_VIDEO:
pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
break;
case PP_SMC_POWER_PROFILE_VR:
pplib_workload = WORKLOAD_PPLIB_VR_BIT;
break;
case PP_SMC_POWER_PROFILE_COMPUTE:
pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
break;
case PP_SMC_POWER_PROFILE_CUSTOM:
pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
break;
}
return pplib_workload;
}
static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
{
DpmActivityMonitorCoeffInt_t activity_monitor;
@ -3210,7 +3238,7 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
workload_type = i + 1;
workload_type = conv_power_profile_to_pplib_workload(i);
result = vega20_get_activity_monitor_coeff(hwmgr,
(uint8_t *)(&activity_monitor), workload_type);
PP_ASSERT_WITH_CODE(!result,
@ -3283,10 +3311,15 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
{
DpmActivityMonitorCoeffInt_t activity_monitor;
int result = 0;
int workload_type, result = 0;
hwmgr->power_profile_mode = input[size];
if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode);
return -EINVAL;
}
if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
if (size < 10)
return -EINVAL;
@ -3353,8 +3386,11 @@ static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, ui
return result);
}
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
workload_type =
conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
1 << hwmgr->power_profile_mode);
1 << workload_type);
return 0;
}

104
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
View File

@ -100,9 +100,8 @@ static void dump_pptable(PPTable_t *pptable)
pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
pr_info("MemoryOnPackage = 0x%02x\n", pptable->MemoryOnPackage);
pr_info("padding8_limits[0] = 0x%02x\n", pptable->padding8_limits[0]);
pr_info("padding8_limits[1] = 0x%02x\n", pptable->padding8_limits[1]);
pr_info("padding8_limits[2] = 0x%02x\n", pptable->padding8_limits[2]);
pr_info("padding8_limits = 0x%02x\n", pptable->padding8_limits);
pr_info("Tvr_SocLimit = %d\n", pptable->Tvr_SocLimit);
pr_info("UlvVoltageOffsetSoc = %d\n", pptable->UlvVoltageOffsetSoc);
pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
@ -417,8 +416,8 @@ static void dump_pptable(PPTable_t *pptable)
pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
pr_info("FanGainLiquid = %d\n", pptable->FanGainLiquid);
pr_info("FanGainVrVddc = %d\n", pptable->FanGainVrVddc);
pr_info("FanGainVrMvdd = %d\n", pptable->FanGainVrMvdd);
pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
pr_info("FanGainPlx = %d\n", pptable->FanGainPlx);
pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
@ -533,23 +532,20 @@ static void dump_pptable(PPTable_t *pptable)
pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
pr_info("MinVoltageUlvSoc = %d\n", pptable->MinVoltageUlvSoc);
for (i = 0; i < 14; i++)
pr_info("MGpuFanBoostLimitRpm = %d\n", pptable->MGpuFanBoostLimitRpm);
pr_info("padding16_Fan = %d\n", pptable->padding16_Fan);
pr_info("FanGainVrMem0 = %d\n", pptable->FanGainVrMem0);
pr_info("FanGainVrMem0 = %d\n", pptable->FanGainVrMem0);
pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
for (i = 0; i < 11; i++)
pr_info("Reserved[%d] = 0x%x\n", i, pptable->Reserved[i]);
pr_info("Liquid1_I2C_address = 0x%x\n", pptable->Liquid1_I2C_address);
pr_info("Liquid2_I2C_address = 0x%x\n", pptable->Liquid2_I2C_address);
pr_info("Vr_I2C_address = 0x%x\n", pptable->Vr_I2C_address);
pr_info("Plx_I2C_address = 0x%x\n", pptable->Plx_I2C_address);
pr_info("Liquid_I2C_LineSCL = 0x%x\n", pptable->Liquid_I2C_LineSCL);
pr_info("Liquid_I2C_LineSDA = 0x%x\n", pptable->Liquid_I2C_LineSDA);
pr_info("Vr_I2C_LineSCL = 0x%x\n", pptable->Vr_I2C_LineSCL);
pr_info("Vr_I2C_LineSDA = 0x%x\n", pptable->Vr_I2C_LineSDA);
pr_info("Plx_I2C_LineSCL = 0x%x\n", pptable->Plx_I2C_LineSCL);
pr_info("Plx_I2C_LineSDA = 0x%x\n", pptable->Plx_I2C_LineSDA);
pr_info("VrSensorPresent = 0x%x\n", pptable->VrSensorPresent);
pr_info("LiquidSensorPresent = 0x%x\n", pptable->LiquidSensorPresent);
for (i = 0; i < 3; i++)
pr_info("Padding32[%d] = 0x%x\n", i, pptable->Padding32[i]);
pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
@ -611,6 +607,24 @@ static void dump_pptable(PPTable_t *pptable)
pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
pr_info("I2cControllers[%d]:\n", i);
pr_info(" .Enabled = %d\n",
pptable->I2cControllers[i].Enabled);
pr_info(" .SlaveAddress = 0x%x\n",
pptable->I2cControllers[i].SlaveAddress);
pr_info(" .ControllerPort = %d\n",
pptable->I2cControllers[i].ControllerPort);
pr_info(" .ControllerName = %d\n",
pptable->I2cControllers[i].ControllerName);
pr_info(" .ThermalThrottler = %d\n",
pptable->I2cControllers[i].ThermalThrottler);
pr_info(" .I2cProtocol = %d\n",
pptable->I2cControllers[i].I2cProtocol);
pr_info(" .I2cSpeed = %d\n",
pptable->I2cControllers[i].I2cSpeed);
}
for (i = 0; i < 10; i++)
pr_info("BoardReserved[%d] = 0x%x\n", i, pptable->BoardReserved[i]);
@ -693,29 +707,19 @@ static int copy_overdrive_feature_capabilities_array(
static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable)
{
struct atom_smc_dpm_info_v4_3 *smc_dpm_table;
struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
int index = GetIndexIntoMasterDataTable(smc_dpm_info);
int i;
PP_ASSERT_WITH_CODE(
smc_dpm_table = smu_atom_get_data_table(hwmgr->adev, index, NULL, NULL, NULL),
"[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!",
return -1);
ppsmc_pptable->Liquid1_I2C_address = smc_dpm_table->liquid1_i2c_address;
ppsmc_pptable->Liquid2_I2C_address = smc_dpm_table->liquid2_i2c_address;
ppsmc_pptable->Vr_I2C_address = smc_dpm_table->vr_i2c_address;
ppsmc_pptable->Plx_I2C_address = smc_dpm_table->plx_i2c_address;
ppsmc_pptable->Liquid_I2C_LineSCL = smc_dpm_table->liquid_i2c_linescl;
ppsmc_pptable->Liquid_I2C_LineSDA = smc_dpm_table->liquid_i2c_linesda;
ppsmc_pptable->Vr_I2C_LineSCL = smc_dpm_table->vr_i2c_linescl;
ppsmc_pptable->Vr_I2C_LineSDA = smc_dpm_table->vr_i2c_linesda;
ppsmc_pptable->Plx_I2C_LineSCL = smc_dpm_table->plx_i2c_linescl;
ppsmc_pptable->Plx_I2C_LineSDA = smc_dpm_table->plx_i2c_linesda;
ppsmc_pptable->VrSensorPresent = smc_dpm_table->vrsensorpresent;
ppsmc_pptable->LiquidSensorPresent = smc_dpm_table->liquidsensorpresent;
memset(ppsmc_pptable->Padding32,
0,
sizeof(struct atom_smc_dpm_info_v4_4) -
sizeof(struct atom_common_table_header));
ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
@ -774,6 +778,24 @@ static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable
ppsmc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
ppsmc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
if ((smc_dpm_table->table_header.format_revision == 4) &&
(smc_dpm_table->table_header.content_revision == 4)) {
for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
ppsmc_pptable->I2cControllers[i].Enabled =
smc_dpm_table->i2ccontrollers[i].enabled;
ppsmc_pptable->I2cControllers[i].SlaveAddress =
smc_dpm_table->i2ccontrollers[i].slaveaddress;
ppsmc_pptable->I2cControllers[i].ControllerPort =
smc_dpm_table->i2ccontrollers[i].controllerport;
ppsmc_pptable->I2cControllers[i].ThermalThrottler =
smc_dpm_table->i2ccontrollers[i].thermalthrottler;
ppsmc_pptable->I2cControllers[i].I2cProtocol =
smc_dpm_table->i2ccontrollers[i].i2cprotocol;
ppsmc_pptable->I2cControllers[i].I2cSpeed =
smc_dpm_table->i2ccontrollers[i].i2cspeed;
}
}
return 0;
}
@ -860,7 +882,15 @@ static int init_powerplay_table_information(
if (pptable_information->smc_pptable == NULL)
return -ENOMEM;
memcpy(pptable_information->smc_pptable, &(powerplay_table->smcPPTable), sizeof(PPTable_t));
if (powerplay_table->smcPPTable.Version <= 2)
memcpy(pptable_information->smc_pptable,
&(powerplay_table->smcPPTable),
sizeof(PPTable_t) -
sizeof(I2cControllerConfig_t) * I2C_CONTROLLER_NAME_COUNT);
else
memcpy(pptable_information->smc_pptable,
&(powerplay_table->smcPPTable),
sizeof(PPTable_t));
result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable));

115
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
View File

@ -27,7 +27,7 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
#define SMU11_DRIVER_IF_VERSION 0x11
#define SMU11_DRIVER_IF_VERSION 0x12
#define PPTABLE_V20_SMU_VERSION 2
@ -165,7 +165,7 @@
#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT )
#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT )
#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT )
#define FEATURE_XGMI_MASK (1 << FEATURE_XGMI_BIT )
#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001
#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002
@ -186,6 +186,9 @@
#define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH 0x00010000
#define DPM_OVERRIDE_ENABLE_GFXOFF_FCLK_SWITCH 0x00020000
#define I2C_CONTROLLER_ENABLED 1
#define I2C_CONTROLLER_DISABLED 0
#define VR_MAPPING_VR_SELECT_MASK 0x01
#define VR_MAPPING_VR_SELECT_SHIFT 0x00
@ -208,15 +211,17 @@
#define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2
#define THROTTLER_STATUS_TEMP_HBM_BIT 3
#define THROTTLER_STATUS_TEMP_VR_GFX_BIT 4
#define THROTTLER_STATUS_TEMP_VR_MEM_BIT 5
#define THROTTLER_STATUS_TEMP_LIQUID_BIT 6
#define THROTTLER_STATUS_TEMP_PLX_BIT 7
#define THROTTLER_STATUS_TEMP_SKIN_BIT 8
#define THROTTLER_STATUS_TDC_GFX_BIT 9
#define THROTTLER_STATUS_TDC_SOC_BIT 10
#define THROTTLER_STATUS_PPT_BIT 11
#define THROTTLER_STATUS_FIT_BIT 12
#define THROTTLER_STATUS_PPM_BIT 13
#define THROTTLER_STATUS_TEMP_VR_SOC_BIT 5
#define THROTTLER_STATUS_TEMP_VR_MEM0_BIT 6
#define THROTTLER_STATUS_TEMP_VR_MEM1_BIT 7
#define THROTTLER_STATUS_TEMP_LIQUID_BIT 8
#define THROTTLER_STATUS_TEMP_PLX_BIT 9
#define THROTTLER_STATUS_TEMP_SKIN_BIT 10
#define THROTTLER_STATUS_TDC_GFX_BIT 11
#define THROTTLER_STATUS_TDC_SOC_BIT 12
#define THROTTLER_STATUS_PPT_BIT 13
#define THROTTLER_STATUS_FIT_BIT 14
#define THROTTLER_STATUS_PPM_BIT 15
#define TABLE_TRANSFER_OK 0x0
@ -236,6 +241,58 @@
#define XGMI_STATE_D0 1
#define XGMI_STATE_D3 0
typedef enum {
I2C_CONTROLLER_PORT_0 = 0,
I2C_CONTROLLER_PORT_1 = 1,
} I2cControllerPort_e;
typedef enum {
I2C_CONTROLLER_NAME_VR_GFX = 0,
I2C_CONTROLLER_NAME_VR_SOC,
I2C_CONTROLLER_NAME_VR_VDDCI,
I2C_CONTROLLER_NAME_VR_HBM,
I2C_CONTROLLER_NAME_LIQUID_0,
I2C_CONTROLLER_NAME_LIQUID_1,
I2C_CONTROLLER_NAME_PLX,
I2C_CONTROLLER_NAME_COUNT,
} I2cControllerName_e;
typedef enum {
I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
I2C_CONTROLLER_THROTTLER_VR_GFX,
I2C_CONTROLLER_THROTTLER_VR_SOC,
I2C_CONTROLLER_THROTTLER_VR_VDDCI,
I2C_CONTROLLER_THROTTLER_VR_HBM,
I2C_CONTROLLER_THROTTLER_LIQUID_0,
I2C_CONTROLLER_THROTTLER_LIQUID_1,
I2C_CONTROLLER_THROTTLER_PLX,
} I2cControllerThrottler_e;
typedef enum {
I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
I2C_CONTROLLER_PROTOCOL_VR_IR35217,
I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
I2C_CONTROLLER_PROTOCOL_SPARE_0,
I2C_CONTROLLER_PROTOCOL_SPARE_1,
I2C_CONTROLLER_PROTOCOL_SPARE_2,
} I2cControllerProtocol_e;
typedef enum {
I2C_CONTROLLER_SPEED_SLOW = 0,
I2C_CONTROLLER_SPEED_FAST = 1,
} I2cControllerSpeed_e;
typedef struct {
uint32_t Enabled;
uint32_t SlaveAddress;
uint32_t ControllerPort;
uint32_t ControllerName;
uint32_t ThermalThrottler;
uint32_t I2cProtocol;
uint32_t I2cSpeed;
} I2cControllerConfig_t;
typedef struct {
uint32_t a;
uint32_t b;
@ -334,8 +391,8 @@ typedef struct {
uint16_t PpmTemperatureThreshold;
uint8_t MemoryOnPackage;
uint8_t padding8_limits[3];
uint8_t padding8_limits;
uint16_t Tvr_SocLimit;
uint16_t UlvVoltageOffsetSoc;
uint16_t UlvVoltageOffsetGfx;
@ -406,8 +463,8 @@ typedef struct {
uint16_t FanGainEdge;
uint16_t FanGainHotspot;
uint16_t FanGainLiquid;
uint16_t FanGainVrVddc;
uint16_t FanGainVrMvdd;
uint16_t FanGainVrGfx;
uint16_t FanGainVrSoc;
uint16_t FanGainPlx;
uint16_t FanGainHbm;
uint16_t FanPwmMin;
@ -444,7 +501,7 @@ typedef struct {
uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];
uint8_t Padding8_GfxBtc[2];
uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT];
int16_t DcBtcMin[AVFS_VOLTAGE_COUNT];
uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT];
@ -467,24 +524,14 @@ typedef struct {
uint16_t MGpuFanBoostLimitRpm;
uint16_t padding16_Fan;
uint32_t Reserved[13];
uint16_t FanGainVrMem0;
uint16_t FanGainVrMem1;
uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT];
uint32_t Reserved[11];
uint8_t Liquid1_I2C_address;
uint8_t Liquid2_I2C_address;
uint8_t Vr_I2C_address;
uint8_t Plx_I2C_address;
uint8_t Liquid_I2C_LineSCL;
uint8_t Liquid_I2C_LineSDA;
uint8_t Vr_I2C_LineSCL;
uint8_t Vr_I2C_LineSDA;
uint8_t Plx_I2C_LineSCL;
uint8_t Plx_I2C_LineSDA;
uint8_t VrSensorPresent;
uint8_t LiquidSensorPresent;
uint32_t Padding32[3];
uint16_t MaxVoltageStepGfx;
uint16_t MaxVoltageStepSoc;
@ -551,6 +598,8 @@ typedef struct {
uint8_t FllGfxclkSpreadPercent;
uint16_t FllGfxclkSpreadFreq;
I2cControllerConfig_t I2cControllers[I2C_CONTROLLER_NAME_COUNT];
uint32_t BoardReserved[10];
@ -607,7 +656,9 @@ typedef struct {
uint16_t TemperatureHotspot ;
uint16_t TemperatureHBM ;
uint16_t TemperatureVrGfx ;
uint16_t TemperatureVrMem ;
uint16_t TemperatureVrSoc ;
uint16_t TemperatureVrMem0 ;
uint16_t TemperatureVrMem1 ;
uint16_t TemperatureLiquid ;
uint16_t TemperaturePlx ;
uint32_t ThrottlerStatus ;

2
drivers/gpu/drm/radeon/mkregtable.c
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: MIT
/* utility to create the register check tables
* this includes inlined list.h safe for userspace.
*

2
drivers/gpu/drm/radeon/r100_track.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* SPDX-License-Identifier: MIT */
#define R100_TRACK_MAX_TEXTURE 3
#define R200_TRACK_MAX_TEXTURE 6

2
drivers/gpu/drm/radeon/radeon_dp_mst.c
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: MIT
#include <drm/drmP.h>
#include <drm/drm_dp_mst_helper.h>

2
drivers/gpu/drm/radeon/radeon_legacy_tv.c
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: MIT
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include "radeon.h"

2
drivers/gpu/drm/radeon/radeon_trace.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* SPDX-License-Identifier: MIT */
#if !defined(_RADEON_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
#define _RADEON_TRACE_H_

2
drivers/gpu/drm/radeon/radeon_trace_points.c
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: MIT
/* Copyright Red Hat Inc 2010.
* Author : Dave Airlie <airlied@redhat.com>
*/

59
drivers/gpu/drm/scheduler/sched_main.c
View File

@ -182,6 +182,20 @@ bool drm_sched_dependency_optimized(struct dma_fence* fence,
}
EXPORT_SYMBOL(drm_sched_dependency_optimized);
/**
* drm_sched_start_timeout - start timeout for reset worker
*
* @sched: scheduler instance to start the worker for
*
* Start the timeout for the given scheduler.
*/
static void drm_sched_start_timeout(struct drm_gpu_scheduler *sched)
{
if (sched->timeout != MAX_SCHEDULE_TIMEOUT &&
!list_empty(&sched->ring_mirror_list))
schedule_delayed_work(&sched->work_tdr, sched->timeout);
}
/* job_finish is called after hw fence signaled
*/
static void drm_sched_job_finish(struct work_struct *work)
@ -203,9 +217,7 @@ static void drm_sched_job_finish(struct work_struct *work)
/* remove job from ring_mirror_list */
list_del(&s_job->node);
/* queue TDR for next job */
if (sched->timeout != MAX_SCHEDULE_TIMEOUT &&
!list_empty(&sched->ring_mirror_list))
schedule_delayed_work(&sched->work_tdr, sched->timeout);
drm_sched_start_timeout(sched);
spin_unlock(&sched->job_list_lock);
dma_fence_put(&s_job->s_fence->finished);
@ -229,10 +241,7 @@ static void drm_sched_job_begin(struct drm_sched_job *s_job)
spin_lock(&sched->job_list_lock);
list_add_tail(&s_job->node, &sched->ring_mirror_list);
if (sched->timeout != MAX_SCHEDULE_TIMEOUT &&
list_first_entry_or_null(&sched->ring_mirror_list,
struct drm_sched_job, node) == s_job)
schedule_delayed_work(&sched->work_tdr, sched->timeout);
drm_sched_start_timeout(sched);
spin_unlock(&sched->job_list_lock);
}
@ -240,13 +249,41 @@ static void drm_sched_job_timedout(struct work_struct *work)
{
struct drm_gpu_scheduler *sched;
struct drm_sched_job *job;
int r;
sched = container_of(work, struct drm_gpu_scheduler, work_tdr.work);
spin_lock(&sched->job_list_lock);
list_for_each_entry_reverse(job, &sched->ring_mirror_list, node) {
struct drm_sched_fence *fence = job->s_fence;
if (!dma_fence_remove_callback(fence->parent, &fence->cb))
goto already_signaled;
}
job = list_first_entry_or_null(&sched->ring_mirror_list,
struct drm_sched_job, node);
spin_unlock(&sched->job_list_lock);
if (job)
job->sched->ops->timedout_job(job);
sched->ops->timedout_job(job);
spin_lock(&sched->job_list_lock);
list_for_each_entry(job, &sched->ring_mirror_list, node) {
struct drm_sched_fence *fence = job->s_fence;
if (!fence->parent || !list_empty(&fence->cb.node))
continue;
r = dma_fence_add_callback(fence->parent, &fence->cb,
drm_sched_process_job);
if (r)
drm_sched_process_job(fence->parent, &fence->cb);
already_signaled:
;
}
spin_unlock(&sched->job_list_lock);
}
/**
@ -313,11 +350,6 @@ void drm_sched_job_recovery(struct drm_gpu_scheduler *sched)
int r;
spin_lock(&sched->job_list_lock);
s_job = list_first_entry_or_null(&sched->ring_mirror_list,
struct drm_sched_job, node);
if (s_job && sched->timeout != MAX_SCHEDULE_TIMEOUT)
schedule_delayed_work(&sched->work_tdr, sched->timeout);
list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) {
struct drm_sched_fence *s_fence = s_job->s_fence;
struct dma_fence *fence;
@ -350,6 +382,7 @@ void drm_sched_job_recovery(struct drm_gpu_scheduler *sched)
}
spin_lock(&sched->job_list_lock);
}
drm_sched_start_timeout(sched);
spin_unlock(&sched->job_list_lock);
}
EXPORT_SYMBOL(drm_sched_job_recovery);

2
include/drm/drm_pciids.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* SPDX-License-Identifier: MIT */
#define radeon_PCI_IDS \
{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \