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drm/amd/display: Continue with stream enable if DP link training fails.

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Not necessarily a fatal problem - some monitors will recover and show
the stream anyway if link training fails.

Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ken Chalmers
2017-05-04 13:34:55 -04:00
committed by Alex Deucher
parent cbfd33fd97
commit c0ba5ec70e
2 changed files with 18 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@@ -1225,7 +1225,7 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
status = DC_OK; status = DC_OK;
} }
else else
status = DC_ERROR_UNEXPECTED; status = DC_FAIL_DP_LINK_TRAINING;
enable_stream_features(pipe_ctx); enable_stream_features(pipe_ctx);
@@ -1833,10 +1833,23 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx)
{ {
struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc);
if (DC_OK != enable_link(pipe_ctx)) { enum dc_status status = enable_link(pipe_ctx);
if (status != DC_OK) {
dm_logger_write(pipe_ctx->stream->ctx->logger,
LOG_WARNING, "enabling link %u failed: %d\n",
pipe_ctx->stream->sink->link->public.link_index,
status);
/* Abort stream enable *unless* the failure was due to
* DP link training - some DP monitors will recover and
* show the stream anyway.
*/
if (status != DC_FAIL_DP_LINK_TRAINING) {
BREAK_TO_DEBUGGER(); BREAK_TO_DEBUGGER();
return; return;
} }
}
/* turn off otg test pattern if enable */ /* turn off otg test pattern if enable */
pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg, pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg,

1
drivers/gpu/drm/amd/display/dc/inc/core_status.h
View File

@@ -41,6 +41,7 @@ enum dc_status {
DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 11, DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 11,
DC_FAIL_BANDWIDTH_VALIDATE = 12, /* BW and Watermark validation */ DC_FAIL_BANDWIDTH_VALIDATE = 12, /* BW and Watermark validation */
DC_FAIL_SCALING = 13, DC_FAIL_SCALING = 13,
DC_FAIL_DP_LINK_TRAINING = 14,
DC_ERROR_UNEXPECTED = -1 DC_ERROR_UNEXPECTED = -1
}; };