forked from Minki/linux
[ARM] VIC: Add power management device
Add power management support to the VIC by registering each VIC as a system device to get suspend/resume events going. Since the VIC registeration is done early, we need to record the VICs in a static array which is used to add the system devices later once the initcalls are run. This means there is now a configuration value for the number of VICs in the system. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Ben Dooks
parent
d87964c460
commit
c07f87f22e
@ -4,6 +4,13 @@ config ARM_GIC
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config ARM_VIC
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bool
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config ARM_VIC_NR
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int
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default 2
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help
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The maximum number of VICs available in the system, for
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power management.
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config ICST525
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bool
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@ -21,6 +21,7 @@
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/sysdev.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/vic.h>
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@ -39,11 +40,219 @@ static void vic_unmask_irq(unsigned int irq)
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writel(1 << irq, base + VIC_INT_ENABLE);
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}
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/**
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* vic_init2 - common initialisation code
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* @base: Base of the VIC.
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*
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* Common initialisation code for registeration
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* and resume.
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*/
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static void vic_init2(void __iomem *base)
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{
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int i;
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for (i = 0; i < 16; i++) {
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void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
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writel(VIC_VECT_CNTL_ENABLE | i, reg);
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}
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writel(32, base + VIC_PL190_DEF_VECT_ADDR);
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}
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#if defined(CONFIG_PM)
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/**
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* struct vic_device - VIC PM device
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* @sysdev: The system device which is registered.
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* @irq: The IRQ number for the base of the VIC.
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* @base: The register base for the VIC.
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* @resume_sources: A bitmask of interrupts for resume.
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* @resume_irqs: The IRQs enabled for resume.
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* @int_select: Save for VIC_INT_SELECT.
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* @int_enable: Save for VIC_INT_ENABLE.
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* @soft_int: Save for VIC_INT_SOFT.
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* @protect: Save for VIC_PROTECT.
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*/
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struct vic_device {
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struct sys_device sysdev;
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void __iomem *base;
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int irq;
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u32 resume_sources;
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u32 resume_irqs;
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u32 int_select;
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u32 int_enable;
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u32 soft_int;
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u32 protect;
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};
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/* we cannot allocate memory when VICs are initially registered */
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static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
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static inline struct vic_device *to_vic(struct sys_device *sys)
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{
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return container_of(sys, struct vic_device, sysdev);
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}
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static int vic_id;
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static int vic_class_resume(struct sys_device *dev)
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{
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struct vic_device *vic = to_vic(dev);
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void __iomem *base = vic->base;
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printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
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/* re-initialise static settings */
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vic_init2(base);
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writel(vic->int_select, base + VIC_INT_SELECT);
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writel(vic->protect, base + VIC_PROTECT);
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/* set the enabled ints and then clear the non-enabled */
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writel(vic->int_enable, base + VIC_INT_ENABLE);
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writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
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/* and the same for the soft-int register */
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writel(vic->soft_int, base + VIC_INT_SOFT);
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writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
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return 0;
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}
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static int vic_class_suspend(struct sys_device *dev, pm_message_t state)
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{
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struct vic_device *vic = to_vic(dev);
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void __iomem *base = vic->base;
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printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
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vic->int_select = readl(base + VIC_INT_SELECT);
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vic->int_enable = readl(base + VIC_INT_ENABLE);
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vic->soft_int = readl(base + VIC_INT_SOFT);
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vic->protect = readl(base + VIC_PROTECT);
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/* set the interrupts (if any) that are used for
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* resuming the system */
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writel(vic->resume_irqs, base + VIC_INT_ENABLE);
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writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
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return 0;
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}
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struct sysdev_class vic_class = {
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.name = "vic",
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.suspend = vic_class_suspend,
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.resume = vic_class_resume,
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};
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/**
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* vic_pm_register - Register a VIC for later power management control
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* @base: The base address of the VIC.
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* @irq: The base IRQ for the VIC.
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* @resume_sources: bitmask of interrupts allowed for resume sources.
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*
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* Register the VIC with the system device tree so that it can be notified
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* of suspend and resume requests and ensure that the correct actions are
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* taken to re-instate the settings on resume.
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*/
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static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
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{
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struct vic_device *v;
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if (vic_id >= ARRAY_SIZE(vic_devices))
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printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
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else {
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v = &vic_devices[vic_id];
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v->base = base;
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v->resume_sources = resume_sources;
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v->irq = irq;
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vic_id++;
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}
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}
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/**
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* vic_pm_init - initicall to register VIC pm
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*
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* This is called via late_initcall() to register
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* the resources for the VICs due to the early
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* nature of the VIC's registration.
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*/
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static int __init vic_pm_init(void)
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{
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struct vic_device *dev = vic_devices;
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int err;
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int id;
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if (vic_id == 0)
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return 0;
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err = sysdev_class_register(&vic_class);
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if (err) {
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printk(KERN_ERR "%s: cannot register class\n", __func__);
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return err;
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}
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for (id = 0; id < vic_id; id++, dev++) {
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dev->sysdev.id = id;
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dev->sysdev.cls = &vic_class;
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err = sysdev_register(&dev->sysdev);
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if (err) {
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printk(KERN_ERR "%s: failed to register device\n",
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__func__);
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return err;
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}
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}
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return 0;
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}
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late_initcall(vic_pm_init);
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static struct vic_device *vic_from_irq(unsigned int irq)
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{
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struct vic_device *v = vic_devices;
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unsigned int base_irq = irq & ~31;
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int id;
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for (id = 0; id < vic_id; id++, v++) {
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if (v->irq == base_irq)
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return v;
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}
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return NULL;
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}
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static int vic_set_wake(unsigned int irq, unsigned int on)
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{
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struct vic_device *v = vic_from_irq(irq);
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unsigned int off = irq & 31;
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if (!v)
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return -EINVAL;
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if (on)
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v->resume_irqs |= 1 << off;
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else
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v->resume_irqs &= ~(1 << off);
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return 0;
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}
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#else
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static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
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#define vic_set_wake NULL
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#endif /* CONFIG_PM */
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static struct irq_chip vic_chip = {
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.name = "VIC",
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.ack = vic_mask_irq,
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.mask = vic_mask_irq,
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.unmask = vic_unmask_irq,
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.set_wake = vic_set_wake,
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};
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/**
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@ -51,9 +260,10 @@ static struct irq_chip vic_chip = {
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* @base: iomem base address
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* @irq_start: starting interrupt number, must be muliple of 32
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* @vic_sources: bitmask of interrupt sources to allow
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* @resume_sources: bitmask of interrupt sources to allow for resume
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*/
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void __init vic_init(void __iomem *base, unsigned int irq_start,
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u32 vic_sources)
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u32 vic_sources, u32 resume_sources)
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{
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unsigned int i;
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@ -77,12 +287,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
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writel(value, base + VIC_PL190_VECT_ADDR);
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}
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for (i = 0; i < 16; i++) {
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void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
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writel(VIC_VECT_CNTL_ENABLE | i, reg);
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}
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writel(32, base + VIC_PL190_DEF_VECT_ADDR);
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vic_init2(base);
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for (i = 0; i < 32; i++) {
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if (vic_sources & (1 << i)) {
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@ -94,4 +299,6 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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}
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vic_pm_register(base, irq_start, resume_sources);
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}
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@ -41,7 +41,7 @@
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#define VIC_PL192_VECT_ADDR 0xF00
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#ifndef __ASSEMBLY__
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void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources);
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void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
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#endif
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#endif
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@ -362,8 +362,8 @@ void __init ep93xx_init_irq(void)
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{
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int gpio_irq;
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vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
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vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
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vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
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vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
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for (gpio_irq = gpio_to_irq(0);
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gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
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@ -168,7 +168,7 @@ void __init netx_init_irq(void)
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{
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int irq;
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vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0);
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vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
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for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
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set_irq_chip(irq, &netx_hif_chip);
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@ -116,7 +116,7 @@ void __init versatile_init_irq(void)
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{
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unsigned int i;
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vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
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vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
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set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
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@ -232,8 +232,8 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
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printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
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/* initialise the pair of VICs */
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vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid);
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vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid);
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vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid, 0);
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vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid, 0);
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/* add the timer sub-irqs */
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