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drm/i915: implement w/a for incorrect guarband clipping

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According to Bsepc, this should be set by default, but isn't. See vo1c.4
"Render Engine Command Streamer", Section 1.1.14.3 "3D_CHICKEN3"

Bspec also says that we always need to set all mask bits.

v2: Add comment about the mask bits wtf.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2012-04-11 20:42:41 +02:00
parent 48ecfa1090
commit bf97b276ca
2 changed files with 5 additions and 0 deletions
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1
drivers/gpu/drm/i915/i915_reg.h
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@ -497,6 +497,7 @@
*/
# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
#define _3D_CHICKEN3 0x02090
#define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 << 5)
#define MI_MODE 0x0209c
# define VS_TIMER_DISPATCH (1 << 6)

4
drivers/gpu/drm/i915/intel_display.c
View File

@ -8897,6 +8897,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
/* Bspec says we need to always set all mask bits. */
I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
_3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
/*
* According to the spec the following bits should be
* set in order to enable memory self-refresh and fbc: