drm/nouveau/pmu: switch to device pri macros
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
83f56106ea
commit
bef002e87f
@ -37,11 +37,12 @@ static int
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nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2],
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u32 process, u32 message, u32 data0, u32 data1)
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{
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struct nvkm_subdev *subdev = nv_subdev(pmu);
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struct nvkm_subdev *subdev = &pmu->subdev;
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struct nvkm_device *device = subdev->device;
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u32 addr;
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/* wait for a free slot in the fifo */
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addr = nv_rd32(pmu, 0x10a4a0);
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addr = nvkm_rd32(device, 0x10a4a0);
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if (!nv_wait_ne(pmu, 0x10a4b0, 0xffffffff, addr ^ 8))
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return -EBUSY;
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@ -57,20 +58,20 @@ nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2],
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/* acquire data segment access */
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do {
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nv_wr32(pmu, 0x10a580, 0x00000001);
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} while (nv_rd32(pmu, 0x10a580) != 0x00000001);
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nvkm_wr32(device, 0x10a580, 0x00000001);
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} while (nvkm_rd32(device, 0x10a580) != 0x00000001);
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/* write the packet */
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nv_wr32(pmu, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) +
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nvkm_wr32(device, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) +
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pmu->send.base));
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nv_wr32(pmu, 0x10a1c4, process);
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nv_wr32(pmu, 0x10a1c4, message);
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nv_wr32(pmu, 0x10a1c4, data0);
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nv_wr32(pmu, 0x10a1c4, data1);
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nv_wr32(pmu, 0x10a4a0, (addr + 1) & 0x0f);
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nvkm_wr32(device, 0x10a1c4, process);
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nvkm_wr32(device, 0x10a1c4, message);
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nvkm_wr32(device, 0x10a1c4, data0);
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nvkm_wr32(device, 0x10a1c4, data1);
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nvkm_wr32(device, 0x10a4a0, (addr + 1) & 0x0f);
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/* release data segment access */
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nv_wr32(pmu, 0x10a580, 0x00000000);
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nvkm_wr32(device, 0x10a580, 0x00000000);
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/* wait for reply, if requested */
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if (reply) {
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@ -87,29 +88,30 @@ static void
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nvkm_pmu_recv(struct work_struct *work)
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{
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struct nvkm_pmu *pmu = container_of(work, struct nvkm_pmu, recv.work);
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struct nvkm_device *device = pmu->subdev.device;
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u32 process, message, data0, data1;
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/* nothing to do if GET == PUT */
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u32 addr = nv_rd32(pmu, 0x10a4cc);
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if (addr == nv_rd32(pmu, 0x10a4c8))
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u32 addr = nvkm_rd32(device, 0x10a4cc);
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if (addr == nvkm_rd32(device, 0x10a4c8))
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return;
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/* acquire data segment access */
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do {
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nv_wr32(pmu, 0x10a580, 0x00000002);
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} while (nv_rd32(pmu, 0x10a580) != 0x00000002);
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nvkm_wr32(device, 0x10a580, 0x00000002);
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} while (nvkm_rd32(device, 0x10a580) != 0x00000002);
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/* read the packet */
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nv_wr32(pmu, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) +
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nvkm_wr32(device, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) +
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pmu->recv.base));
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process = nv_rd32(pmu, 0x10a1c4);
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message = nv_rd32(pmu, 0x10a1c4);
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data0 = nv_rd32(pmu, 0x10a1c4);
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data1 = nv_rd32(pmu, 0x10a1c4);
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nv_wr32(pmu, 0x10a4cc, (addr + 1) & 0x0f);
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process = nvkm_rd32(device, 0x10a1c4);
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message = nvkm_rd32(device, 0x10a1c4);
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data0 = nvkm_rd32(device, 0x10a1c4);
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data1 = nvkm_rd32(device, 0x10a1c4);
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nvkm_wr32(device, 0x10a4cc, (addr + 1) & 0x0f);
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/* release data segment access */
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nv_wr32(pmu, 0x10a580, 0x00000000);
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nvkm_wr32(device, 0x10a580, 0x00000000);
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/* wake process if it's waiting on a synchronous reply */
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if (pmu->recv.process) {
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@ -137,36 +139,37 @@ nvkm_pmu_recv(struct work_struct *work)
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static void
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nvkm_pmu_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_pmu *pmu = (void *)subdev;
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u32 disp = nv_rd32(pmu, 0x10a01c);
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u32 intr = nv_rd32(pmu, 0x10a008) & disp & ~(disp >> 16);
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struct nvkm_pmu *pmu = container_of(subdev, typeof(*pmu), subdev);
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struct nvkm_device *device = pmu->subdev.device;
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u32 disp = nvkm_rd32(device, 0x10a01c);
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u32 intr = nvkm_rd32(device, 0x10a008) & disp & ~(disp >> 16);
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if (intr & 0x00000020) {
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u32 stat = nv_rd32(pmu, 0x10a16c);
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u32 stat = nvkm_rd32(device, 0x10a16c);
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if (stat & 0x80000000) {
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nv_error(pmu, "UAS fault at 0x%06x addr 0x%08x\n",
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stat & 0x00ffffff, nv_rd32(pmu, 0x10a168));
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nv_wr32(pmu, 0x10a16c, 0x00000000);
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stat & 0x00ffffff, nvkm_rd32(device, 0x10a168));
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nvkm_wr32(device, 0x10a16c, 0x00000000);
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intr &= ~0x00000020;
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}
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}
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if (intr & 0x00000040) {
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schedule_work(&pmu->recv.work);
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nv_wr32(pmu, 0x10a004, 0x00000040);
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nvkm_wr32(device, 0x10a004, 0x00000040);
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intr &= ~0x00000040;
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}
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if (intr & 0x00000080) {
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nv_info(pmu, "wr32 0x%06x 0x%08x\n", nv_rd32(pmu, 0x10a7a0),
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nv_rd32(pmu, 0x10a7a4));
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nv_wr32(pmu, 0x10a004, 0x00000080);
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nv_info(pmu, "wr32 0x%06x 0x%08x\n", nvkm_rd32(device, 0x10a7a0),
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nvkm_rd32(device, 0x10a7a4));
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nvkm_wr32(device, 0x10a004, 0x00000080);
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intr &= ~0x00000080;
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}
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if (intr) {
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nv_error(pmu, "intr 0x%08x\n", intr);
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nv_wr32(pmu, 0x10a004, intr);
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nvkm_wr32(device, 0x10a004, intr);
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}
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}
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@ -174,8 +177,9 @@ int
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_nvkm_pmu_fini(struct nvkm_object *object, bool suspend)
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{
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struct nvkm_pmu *pmu = (void *)object;
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struct nvkm_device *device = pmu->subdev.device;
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nv_wr32(pmu, 0x10a014, 0x00000060);
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nvkm_wr32(device, 0x10a014, 0x00000060);
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flush_work(&pmu->recv.work);
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return nvkm_subdev_fini(&pmu->subdev, suspend);
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@ -186,6 +190,7 @@ _nvkm_pmu_init(struct nvkm_object *object)
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{
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const struct nvkm_pmu_impl *impl = (void *)object->oclass;
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struct nvkm_pmu *pmu = (void *)object;
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struct nvkm_device *device = pmu->subdev.device;
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int ret, i;
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ret = nvkm_subdev_init(&pmu->subdev);
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@ -197,44 +202,44 @@ _nvkm_pmu_init(struct nvkm_object *object)
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pmu->pgob = nvkm_pmu_pgob;
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/* prevent previous ucode from running, wait for idle, reset */
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nv_wr32(pmu, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
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nvkm_wr32(device, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
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nv_wait(pmu, 0x10a04c, 0xffffffff, 0x00000000);
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nv_mask(pmu, 0x000200, 0x00002000, 0x00000000);
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nv_mask(pmu, 0x000200, 0x00002000, 0x00002000);
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nv_rd32(pmu, 0x000200);
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nvkm_mask(device, 0x000200, 0x00002000, 0x00000000);
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nvkm_mask(device, 0x000200, 0x00002000, 0x00002000);
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nvkm_rd32(device, 0x000200);
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nv_wait(pmu, 0x10a10c, 0x00000006, 0x00000000);
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/* upload data segment */
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nv_wr32(pmu, 0x10a1c0, 0x01000000);
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nvkm_wr32(device, 0x10a1c0, 0x01000000);
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for (i = 0; i < impl->data.size / 4; i++)
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nv_wr32(pmu, 0x10a1c4, impl->data.data[i]);
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nvkm_wr32(device, 0x10a1c4, impl->data.data[i]);
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/* upload code segment */
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nv_wr32(pmu, 0x10a180, 0x01000000);
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nvkm_wr32(device, 0x10a180, 0x01000000);
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for (i = 0; i < impl->code.size / 4; i++) {
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if ((i & 0x3f) == 0)
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nv_wr32(pmu, 0x10a188, i >> 6);
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nv_wr32(pmu, 0x10a184, impl->code.data[i]);
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nvkm_wr32(device, 0x10a188, i >> 6);
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nvkm_wr32(device, 0x10a184, impl->code.data[i]);
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}
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/* start it running */
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nv_wr32(pmu, 0x10a10c, 0x00000000);
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nv_wr32(pmu, 0x10a104, 0x00000000);
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nv_wr32(pmu, 0x10a100, 0x00000002);
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nvkm_wr32(device, 0x10a10c, 0x00000000);
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nvkm_wr32(device, 0x10a104, 0x00000000);
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nvkm_wr32(device, 0x10a100, 0x00000002);
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/* wait for valid host->pmu ring configuration */
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if (!nv_wait_ne(pmu, 0x10a4d0, 0xffffffff, 0x00000000))
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return -EBUSY;
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pmu->send.base = nv_rd32(pmu, 0x10a4d0) & 0x0000ffff;
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pmu->send.size = nv_rd32(pmu, 0x10a4d0) >> 16;
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pmu->send.base = nvkm_rd32(device, 0x10a4d0) & 0x0000ffff;
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pmu->send.size = nvkm_rd32(device, 0x10a4d0) >> 16;
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/* wait for valid pmu->host ring configuration */
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if (!nv_wait_ne(pmu, 0x10a4dc, 0xffffffff, 0x00000000))
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return -EBUSY;
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pmu->recv.base = nv_rd32(pmu, 0x10a4dc) & 0x0000ffff;
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pmu->recv.size = nv_rd32(pmu, 0x10a4dc) >> 16;
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pmu->recv.base = nvkm_rd32(device, 0x10a4dc) & 0x0000ffff;
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pmu->recv.size = nvkm_rd32(device, 0x10a4dc) >> 16;
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nv_wr32(pmu, 0x10a010, 0x000000e0);
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nvkm_wr32(device, 0x10a010, 0x000000e0);
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return 0;
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}
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@ -31,49 +31,49 @@
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#include <subdev/timer.h>
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static void
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magic_(struct nvkm_pmu *pmu, u32 ctrl, int size)
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magic_(struct nvkm_device *device, u32 ctrl, int size)
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{
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nv_wr32(pmu, 0x00c800, 0x00000000);
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nv_wr32(pmu, 0x00c808, 0x00000000);
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nv_wr32(pmu, 0x00c800, ctrl);
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if (nv_wait(pmu, 0x00c800, 0x40000000, 0x40000000)) {
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nvkm_wr32(device, 0x00c800, 0x00000000);
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nvkm_wr32(device, 0x00c808, 0x00000000);
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nvkm_wr32(device, 0x00c800, ctrl);
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if (nv_wait(device, 0x00c800, 0x40000000, 0x40000000)) {
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while (size--)
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nv_wr32(pmu, 0x00c804, 0x00000000);
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nvkm_wr32(device, 0x00c804, 0x00000000);
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}
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nv_wr32(pmu, 0x00c800, 0x00000000);
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nvkm_wr32(device, 0x00c800, 0x00000000);
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}
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static void
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magic(struct nvkm_pmu *pmu, u32 ctrl)
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magic(struct nvkm_device *device, u32 ctrl)
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{
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magic_(pmu, 0x8000a41f | ctrl, 6);
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magic_(pmu, 0x80000421 | ctrl, 1);
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magic_(device, 0x8000a41f | ctrl, 6);
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magic_(device, 0x80000421 | ctrl, 1);
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}
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static void
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gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
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{
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struct nvkm_device *device = nv_device(pmu);
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struct nvkm_device *device = pmu->subdev.device;
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nv_mask(pmu, 0x000200, 0x00001000, 0x00000000);
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nv_rd32(pmu, 0x000200);
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nv_mask(pmu, 0x000200, 0x08000000, 0x08000000);
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nvkm_mask(device, 0x000200, 0x00001000, 0x00000000);
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nvkm_rd32(device, 0x000200);
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nvkm_mask(device, 0x000200, 0x08000000, 0x08000000);
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msleep(50);
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nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000002);
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nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001);
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nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000);
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nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000002);
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nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001);
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nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000);
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nv_mask(pmu, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000);
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nvkm_mask(device, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000);
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msleep(50);
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nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000000);
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nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001);
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nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000);
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nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000000);
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nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001);
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nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000);
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nv_mask(pmu, 0x000200, 0x08000000, 0x00000000);
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nv_mask(pmu, 0x000200, 0x00001000, 0x00001000);
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nv_rd32(pmu, 0x000200);
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nvkm_mask(device, 0x000200, 0x08000000, 0x00000000);
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nvkm_mask(device, 0x000200, 0x00001000, 0x00001000);
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nvkm_rd32(device, 0x000200);
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if (nv_device_match(device, 0x11fc, 0x17aa, 0x2211) /* Lenovo W541 */
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|| nv_device_match(device, 0x11fc, 0x17aa, 0x221e) /* Lenovo W541 */
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@ -81,18 +81,18 @@ gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
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nv_info(pmu, "hw bug workaround enabled\n");
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switch (device->chipset) {
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case 0xe4:
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magic(pmu, 0x04000000);
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magic(pmu, 0x06000000);
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magic(pmu, 0x0c000000);
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magic(pmu, 0x0e000000);
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magic(device, 0x04000000);
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magic(device, 0x06000000);
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magic(device, 0x0c000000);
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magic(device, 0x0e000000);
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break;
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case 0xe6:
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magic(pmu, 0x02000000);
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magic(pmu, 0x04000000);
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magic(pmu, 0x0a000000);
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magic(device, 0x02000000);
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magic(device, 0x04000000);
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magic(device, 0x0a000000);
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break;
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case 0xe7:
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magic(pmu, 0x02000000);
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magic(device, 0x02000000);
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break;
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default:
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break;
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@ -31,6 +31,7 @@
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void
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gk110_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
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{
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struct nvkm_device *device = pmu->subdev.device;
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static const struct {
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u32 addr;
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u32 data;
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@ -54,28 +55,28 @@ gk110_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
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};
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int i;
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nv_mask(pmu, 0x000200, 0x00001000, 0x00000000);
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nv_rd32(pmu, 0x000200);
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nv_mask(pmu, 0x000200, 0x08000000, 0x08000000);
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nvkm_mask(device, 0x000200, 0x00001000, 0x00000000);
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nvkm_rd32(device, 0x000200);
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nvkm_mask(device, 0x000200, 0x08000000, 0x08000000);
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msleep(50);
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nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000002);
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nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001);
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nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000);
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nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000002);
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nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001);
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nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000);
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nv_mask(pmu, 0x0206b4, 0x00000000, 0x00000000);
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nvkm_mask(device, 0x0206b4, 0x00000000, 0x00000000);
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for (i = 0; i < ARRAY_SIZE(magic); i++) {
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nv_wr32(pmu, magic[i].addr, magic[i].data);
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nvkm_wr32(device, magic[i].addr, magic[i].data);
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nv_wait(pmu, magic[i].addr, 0x80000000, 0x00000000);
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}
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nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000000);
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nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001);
|
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nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000);
|
||||
nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000000);
|
||||
nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001);
|
||||
nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000);
|
||||
|
||||
nv_mask(pmu, 0x000200, 0x08000000, 0x00000000);
|
||||
nv_mask(pmu, 0x000200, 0x00001000, 0x00001000);
|
||||
nv_rd32(pmu, 0x000200);
|
||||
nvkm_mask(device, 0x000200, 0x08000000, 0x00000000);
|
||||
nvkm_mask(device, 0x000200, 0x00001000, 0x00001000);
|
||||
nvkm_rd32(device, 0x000200);
|
||||
}
|
||||
|
||||
struct nvkm_oclass *
|
||||
|
||||
@ -98,16 +98,18 @@ static int
|
||||
gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu *pmu,
|
||||
struct gk20a_pmu_dvfs_dev_status *status)
|
||||
{
|
||||
status->busy = nv_rd32(pmu, 0x10a508 + (BUSY_SLOT * 0x10));
|
||||
status->total= nv_rd32(pmu, 0x10a508 + (CLK_SLOT * 0x10));
|
||||
struct nvkm_device *device = pmu->base.subdev.device;
|
||||
status->busy = nvkm_rd32(device, 0x10a508 + (BUSY_SLOT * 0x10));
|
||||
status->total= nvkm_rd32(device, 0x10a508 + (CLK_SLOT * 0x10));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
gk20a_pmu_dvfs_reset_dev_status(struct gk20a_pmu *pmu)
|
||||
{
|
||||
nv_wr32(pmu, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000);
|
||||
nv_wr32(pmu, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000);
|
||||
struct nvkm_device *device = pmu->base.subdev.device;
|
||||
nvkm_wr32(device, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000);
|
||||
nvkm_wr32(device, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -173,6 +175,7 @@ static int
|
||||
gk20a_pmu_init(struct nvkm_object *object)
|
||||
{
|
||||
struct gk20a_pmu *pmu = (void *)object;
|
||||
struct nvkm_device *device = pmu->base.subdev.device;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_subdev_init(&pmu->base.subdev);
|
||||
@ -182,9 +185,9 @@ gk20a_pmu_init(struct nvkm_object *object)
|
||||
pmu->base.pgob = nvkm_pmu_pgob;
|
||||
|
||||
/* init pwr perf counter */
|
||||
nv_wr32(pmu, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
|
||||
nv_wr32(pmu, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002);
|
||||
nv_wr32(pmu, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
|
||||
nvkm_wr32(device, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
|
||||
nvkm_wr32(device, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002);
|
||||
nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
|
||||
|
||||
nvkm_timer_alarm(pmu, 2000000000, &pmu->alarm);
|
||||
return ret;
|
||||
|
||||
@ -28,8 +28,9 @@ static int
|
||||
gt215_pmu_init(struct nvkm_object *object)
|
||||
{
|
||||
struct nvkm_pmu *pmu = (void *)object;
|
||||
nv_mask(pmu, 0x022210, 0x00000001, 0x00000000);
|
||||
nv_mask(pmu, 0x022210, 0x00000001, 0x00000001);
|
||||
struct nvkm_device *device = pmu->subdev.device;
|
||||
nvkm_mask(device, 0x022210, 0x00000001, 0x00000000);
|
||||
nvkm_mask(device, 0x022210, 0x00000001, 0x00000001);
|
||||
return nvkm_pmu_init(pmu);
|
||||
}
|
||||
|
||||
|
||||
@ -16,13 +16,13 @@ struct nvkm_memx {
|
||||
static void
|
||||
memx_out(struct nvkm_memx *memx)
|
||||
{
|
||||
struct nvkm_pmu *pmu = memx->pmu;
|
||||
struct nvkm_device *device = memx->pmu->subdev.device;
|
||||
int i;
|
||||
|
||||
if (memx->c.mthd) {
|
||||
nv_wr32(pmu, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd);
|
||||
nvkm_wr32(device, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd);
|
||||
for (i = 0; i < memx->c.size; i++)
|
||||
nv_wr32(pmu, 0x10a1c4, memx->c.data[i]);
|
||||
nvkm_wr32(device, 0x10a1c4, memx->c.data[i]);
|
||||
memx->c.mthd = 0;
|
||||
memx->c.size = 0;
|
||||
}
|
||||
@ -42,6 +42,7 @@ memx_cmd(struct nvkm_memx *memx, u32 mthd, u32 size, u32 data[])
|
||||
int
|
||||
nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx)
|
||||
{
|
||||
struct nvkm_device *device = pmu->subdev.device;
|
||||
struct nvkm_memx *memx;
|
||||
u32 reply[2];
|
||||
int ret;
|
||||
@ -60,9 +61,9 @@ nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx)
|
||||
|
||||
/* acquire data segment access */
|
||||
do {
|
||||
nv_wr32(pmu, 0x10a580, 0x00000003);
|
||||
} while (nv_rd32(pmu, 0x10a580) != 0x00000003);
|
||||
nv_wr32(pmu, 0x10a1c0, 0x01000000 | memx->base);
|
||||
nvkm_wr32(device, 0x10a580, 0x00000003);
|
||||
} while (nvkm_rd32(device, 0x10a580) != 0x00000003);
|
||||
nvkm_wr32(device, 0x10a1c0, 0x01000000 | memx->base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -71,14 +72,15 @@ nvkm_memx_fini(struct nvkm_memx **pmemx, bool exec)
|
||||
{
|
||||
struct nvkm_memx *memx = *pmemx;
|
||||
struct nvkm_pmu *pmu = memx->pmu;
|
||||
struct nvkm_device *device = pmu->subdev.device;
|
||||
u32 finish, reply[2];
|
||||
|
||||
/* flush the cache... */
|
||||
memx_out(memx);
|
||||
|
||||
/* release data segment access */
|
||||
finish = nv_rd32(pmu, 0x10a1c0) & 0x00ffffff;
|
||||
nv_wr32(pmu, 0x10a580, 0x00000000);
|
||||
finish = nvkm_rd32(device, 0x10a1c0) & 0x00ffffff;
|
||||
nvkm_wr32(device, 0x10a580, 0x00000000);
|
||||
|
||||
/* call MEMX process to execute the script, and wait for reply */
|
||||
if (exec) {
|
||||
@ -120,16 +122,16 @@ nvkm_memx_nsec(struct nvkm_memx *memx, u32 nsec)
|
||||
void
|
||||
nvkm_memx_wait_vblank(struct nvkm_memx *memx)
|
||||
{
|
||||
struct nvkm_pmu *pmu = memx->pmu;
|
||||
struct nvkm_device *device = memx->pmu->subdev.device;
|
||||
u32 heads, x, y, px = 0;
|
||||
int i, head_sync;
|
||||
|
||||
if (nv_device(pmu)->chipset < 0xd0) {
|
||||
heads = nv_rd32(pmu, 0x610050);
|
||||
if (device->chipset < 0xd0) {
|
||||
heads = nvkm_rd32(device, 0x610050);
|
||||
for (i = 0; i < 2; i++) {
|
||||
/* Heuristic: sync to head with biggest resolution */
|
||||
if (heads & (2 << (i << 3))) {
|
||||
x = nv_rd32(pmu, 0x610b40 + (0x540 * i));
|
||||
x = nvkm_rd32(device, 0x610b40 + (0x540 * i));
|
||||
y = (x & 0xffff0000) >> 16;
|
||||
x &= 0x0000ffff;
|
||||
if ((x * y) > px) {
|
||||
@ -160,6 +162,7 @@ nvkm_memx_train(struct nvkm_memx *memx)
|
||||
int
|
||||
nvkm_memx_train_result(struct nvkm_pmu *pmu, u32 *res, int rsize)
|
||||
{
|
||||
struct nvkm_device *device = pmu->subdev.device;
|
||||
u32 reply[2], base, size, i;
|
||||
int ret;
|
||||
|
||||
@ -174,10 +177,10 @@ nvkm_memx_train_result(struct nvkm_pmu *pmu, u32 *res, int rsize)
|
||||
return -ENOMEM;
|
||||
|
||||
/* read the packet */
|
||||
nv_wr32(pmu, 0x10a1c0, 0x02000000 | base);
|
||||
nvkm_wr32(device, 0x10a1c0, 0x02000000 | base);
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
res[i] = nv_rd32(pmu, 0x10a1c4);
|
||||
res[i] = nvkm_rd32(device, 0x10a1c4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user