iommu/ipmmu-vmsa: Remove stage 2 PTE bits definitions
We don't support stage 2 translation yet. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -201,14 +201,6 @@ static LIST_HEAD(ipmmu_devices);
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#define ARM_VMSA_PTE_ATTRINDX_SHIFT 2
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#define ARM_VMSA_PTE_nG (((pteval_t)1) << 11)
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/* Stage-2 PTE */
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#define ARM_VMSA_PTE_HAP_FAULT (((pteval_t)0) << 6)
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#define ARM_VMSA_PTE_HAP_READ (((pteval_t)1) << 6)
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#define ARM_VMSA_PTE_HAP_WRITE (((pteval_t)2) << 6)
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#define ARM_VMSA_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2)
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#define ARM_VMSA_PTE_MEMATTR_NC (((pteval_t)0x5) << 2)
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#define ARM_VMSA_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2)
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#define ARM_VMSA_PTE_CONT_ENTRIES 16
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#define ARM_VMSA_PTE_CONT_SIZE (PAGE_SIZE * ARM_VMSA_PTE_CONT_ENTRIES)
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