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drm/amd/display: improve cursor programming reliability

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This change will cache cursor attributes and reprogram them
when enabling cursor after power gating if the attributes were not
yet reprogrammed

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
2017-04-21 09:34:09 -04:00
committed by Alex Deucher
parent 03f5c686c3
commit beb16b6a0f
7 changed files with 30 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
View File

@@ -182,7 +182,6 @@ bool dc_stream_set_cursor_attributes(
struct core_stream *stream;
struct core_dc *core_dc;
struct resource_context *res_ctx;
bool ret = false;
if (NULL == dc_stream) {
dm_error("DC: dc_stream is NULL!\n");
@@ -200,28 +199,26 @@ bool dc_stream_set_cursor_attributes(
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
if ((pipe_ctx->stream == stream) &&
(pipe_ctx->ipp != NULL)) {
struct input_pixel_processor *ipp = pipe_ctx->ipp;
if (pipe_ctx->stream != stream || !pipe_ctx->ipp)
continue;
if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface)
continue;
if (ipp->funcs->ipp_cursor_set_attributes(
ipp, attributes))
ret = true;
}
pipe_ctx->ipp->funcs->ipp_cursor_set_attributes(
pipe_ctx->ipp, attributes);
}
return ret;
return true;
}
bool dc_stream_set_cursor_position(
const struct dc_stream *dc_stream,
struct dc_cursor_position *position)
const struct dc_cursor_position *position)
{
int i;
struct core_stream *stream;
struct core_dc *core_dc;
struct resource_context *res_ctx;
bool ret = false;
if (NULL == dc_stream) {
dm_error("DC: dc_stream is NULL!\n");
@@ -239,27 +236,27 @@ bool dc_stream_set_cursor_position(
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
struct input_pixel_processor *ipp = pipe_ctx->ipp;
struct dc_cursor_position pos_cpy = *position;
struct dc_cursor_mi_param param = {
.pixel_clk_khz = dc_stream->timing.pix_clk_khz,
.ref_clk_khz = res_ctx->pool->ref_clock_inKhz,
.viewport_x_start = pipe_ctx->scl_data.viewport.x,
.viewport_width = pipe_ctx->scl_data.viewport.width,
.h_scale_ratio = pipe_ctx->scl_data.ratios.horz
};
if (pipe_ctx->stream == stream &&
pipe_ctx->ipp && pipe_ctx->surface) {
struct input_pixel_processor *ipp = pipe_ctx->ipp;
struct dc_cursor_mi_param param = {
.pixel_clk_khz = dc_stream->timing.pix_clk_khz,
.ref_clk_khz = res_ctx->pool->ref_clock_inKhz,
.viewport_x_start = pipe_ctx->scl_data.viewport.x,
.viewport_width = pipe_ctx->scl_data.viewport.width,
.h_scale_ratio = pipe_ctx->scl_data.ratios.horz,
};
if (pipe_ctx->stream != stream ||
!pipe_ctx->ipp || !pipe_ctx->surface)
continue;
if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface)
position->enable = false;
if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface)
pos_cpy.enable = false;
ipp->funcs->ipp_cursor_set_position(ipp, position, &param);
ret = true;
}
ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
}
return ret;
return true;
}
uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream)

2
drivers/gpu/drm/amd/display/dc/dc.h
View File

@@ -764,7 +764,7 @@ bool dc_stream_set_cursor_attributes(
bool dc_stream_set_cursor_position(
const struct dc_stream *stream,
struct dc_cursor_position *position);
const struct dc_cursor_position *position);
/* Newer interfaces */
struct dc_cursor {

2
drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h
View File

@@ -54,7 +54,7 @@ void dce110_ipp_cursor_set_position(
const struct dc_cursor_position *position,
const struct dc_cursor_mi_param *param);
bool dce110_ipp_cursor_set_attributes(
void dce110_ipp_cursor_set_attributes(
struct input_pixel_processor *ipp,
const struct dc_cursor_attributes *attributes);

4
drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c
View File

@@ -95,7 +95,7 @@ void dce110_ipp_cursor_set_position(
lock(ipp110, false);
}
bool dce110_ipp_cursor_set_attributes(
void dce110_ipp_cursor_set_attributes(
struct input_pixel_processor *ipp,
const struct dc_cursor_attributes *attributes)
{
@@ -122,8 +122,6 @@ bool dce110_ipp_cursor_set_attributes(
/* Unlock Cursor registers. */
lock(ipp110, false);
return true;
}
static void enable(

2
drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h
View File

@@ -42,7 +42,7 @@ void dce120_ipp_cursor_set_position(
const struct dc_cursor_position *position,
const struct dc_cursor_mi_param *param);
bool dce120_ipp_cursor_set_attributes(
void dce120_ipp_cursor_set_attributes(
struct input_pixel_processor *ipp,
const struct dc_cursor_attributes *attributes);

4
drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c
View File

@@ -160,7 +160,7 @@ void dce120_ipp_cursor_set_position(
lock(ipp110, false);
}
bool dce120_ipp_cursor_set_attributes(
void dce120_ipp_cursor_set_attributes(
struct input_pixel_processor *ipp,
const struct dc_cursor_attributes *attributes)
{
@@ -189,7 +189,5 @@ bool dce120_ipp_cursor_set_attributes(
/* Unlock Cursor registers. */
lock(ipp110, false);
return true;
}

4
drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
View File

@@ -37,8 +37,6 @@ struct input_pixel_processor {
struct dc_context *ctx;
unsigned int inst;
const struct ipp_funcs *funcs;
unsigned int cusor_width;
};
enum ipp_prescale_mode {
@@ -88,7 +86,7 @@ struct ipp_funcs {
const struct dc_cursor_position *position,
const struct dc_cursor_mi_param *param);
bool (*ipp_cursor_set_attributes)(
void (*ipp_cursor_set_attributes)(
struct input_pixel_processor *ipp,
const struct dc_cursor_attributes *attributes);