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drm/i915: add POWER_DOMAIN_PLLS

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And get/put it when needed. The special thing about this commit is
that it will now return false in ibx_pch_dpll_get_hw_state() in case
the power domain is not enabled. This will fix some WARNs we have when
we run pm_rpm on SNB.

Testcase: igt/pm_rpm
Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=80463
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Paulo Zanoni 2014-07-04 11:27:38 -03:00 committed by Daniel Vetter
parent 96f6128cbb
commit bd2bb1b9a1
4 changed files with 14 additions and 0 deletions
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2
drivers/gpu/drm/i915/i915_debugfs.c
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@ -2043,6 +2043,8 @@ static const char *power_domain_str(enum intel_display_power_domain domain)
return "VGA"; return "VGA";
case POWER_DOMAIN_AUDIO: case POWER_DOMAIN_AUDIO:
return "AUDIO"; return "AUDIO";
case POWER_DOMAIN_PLLS:
return "PLLS";
case POWER_DOMAIN_INIT: case POWER_DOMAIN_INIT:
return "INIT"; return "INIT";
default: default:

1
drivers/gpu/drm/i915/i915_drv.h
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@ -129,6 +129,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_OTHER, POWER_DOMAIN_PORT_OTHER,
POWER_DOMAIN_VGA, POWER_DOMAIN_VGA,
POWER_DOMAIN_AUDIO, POWER_DOMAIN_AUDIO,
POWER_DOMAIN_PLLS,
POWER_DOMAIN_INIT, POWER_DOMAIN_INIT,
POWER_DOMAIN_NUM, POWER_DOMAIN_NUM,

10
drivers/gpu/drm/i915/intel_display.c
View File

@ -1814,6 +1814,8 @@ static void intel_enable_shared_dpll(struct intel_crtc *crtc)
} }
WARN_ON(pll->on); WARN_ON(pll->on);
intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
DRM_DEBUG_KMS("enabling %s\n", pll->name); DRM_DEBUG_KMS("enabling %s\n", pll->name);
pll->enable(dev_priv, pll); pll->enable(dev_priv, pll);
pll->on = true; pll->on = true;
@ -1850,6 +1852,8 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
DRM_DEBUG_KMS("disabling %s\n", pll->name); DRM_DEBUG_KMS("disabling %s\n", pll->name);
pll->disable(dev_priv, pll); pll->disable(dev_priv, pll);
pll->on = false; pll->on = false;
intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
} }
static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
@ -11302,6 +11306,9 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
{ {
uint32_t val; uint32_t val;
if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
return false;
val = I915_READ(PCH_DPLL(pll->id)); val = I915_READ(PCH_DPLL(pll->id));
hw_state->dpll = val; hw_state->dpll = val;
hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
@ -12867,6 +12874,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
pll->name, pll->refcount, pll->on); pll->name, pll->refcount, pll->on);
if (pll->refcount)
intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
} }
list_for_each_entry(encoder, &dev->mode_config.encoder_list, list_for_each_entry(encoder, &dev->mode_config.encoder_list,

1
drivers/gpu/drm/i915/intel_pm.c
View File

@ -6346,6 +6346,7 @@ EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
BIT(POWER_DOMAIN_PORT_CRT) | \ BIT(POWER_DOMAIN_PORT_CRT) | \
BIT(POWER_DOMAIN_PLLS) | \
BIT(POWER_DOMAIN_INIT)) BIT(POWER_DOMAIN_INIT))
#define HSW_DISPLAY_POWER_DOMAINS ( \ #define HSW_DISPLAY_POWER_DOMAINS ( \
(POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \