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drm/radeon: fix amd afusion gpu setup aka sumo v2

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Set the proper number of tile pipe that should be a multiple of
pipe depending on the number of se engine.

Fix:
https://bugs.freedesktop.org/show_bug.cgi?id=56405
https://bugs.freedesktop.org/show_bug.cgi?id=56720

v2: Don't change sumo2

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Cc: stable@vger.kernel.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jerome Glisse 2012-12-11 11:56:52 -05:00 committed by Alex Deucher
parent d025e9e2b8
commit bd25f0783d
2 changed files with 6 additions and 4 deletions
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8
drivers/gpu/drm/radeon/evergreen.c
View File

@ -1821,7 +1821,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
case CHIP_SUMO: case CHIP_SUMO:
rdev->config.evergreen.num_ses = 1; rdev->config.evergreen.num_ses = 1;
rdev->config.evergreen.max_pipes = 4; rdev->config.evergreen.max_pipes = 4;
rdev->config.evergreen.max_tile_pipes = 2; rdev->config.evergreen.max_tile_pipes = 4;
if (rdev->pdev->device == 0x9648) if (rdev->pdev->device == 0x9648)
rdev->config.evergreen.max_simds = 3; rdev->config.evergreen.max_simds = 3;
else if ((rdev->pdev->device == 0x9647) || else if ((rdev->pdev->device == 0x9647) ||
@ -1844,7 +1844,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
rdev->config.evergreen.sc_prim_fifo_size = 0x40; rdev->config.evergreen.sc_prim_fifo_size = 0x40;
rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN;
break; break;
case CHIP_SUMO2: case CHIP_SUMO2:
rdev->config.evergreen.num_ses = 1; rdev->config.evergreen.num_ses = 1;
@ -1866,7 +1866,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
rdev->config.evergreen.sc_prim_fifo_size = 0x40; rdev->config.evergreen.sc_prim_fifo_size = 0x40;
rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
break; break;
case CHIP_BARTS: case CHIP_BARTS:
rdev->config.evergreen.num_ses = 2; rdev->config.evergreen.num_ses = 2;
@ -1914,7 +1914,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
break; break;
case CHIP_CAICOS: case CHIP_CAICOS:
rdev->config.evergreen.num_ses = 1; rdev->config.evergreen.num_ses = 1;
rdev->config.evergreen.max_pipes = 4; rdev->config.evergreen.max_pipes = 2;
rdev->config.evergreen.max_tile_pipes = 2; rdev->config.evergreen.max_tile_pipes = 2;
rdev->config.evergreen.max_simds = 2; rdev->config.evergreen.max_simds = 2;
rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;

2
drivers/gpu/drm/radeon/evergreend.h
View File

@ -45,6 +45,8 @@
#define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
#define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001
#define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001
#define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002
#define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002
/* Registers */ /* Registers */