forked from Minki/linux
Merge branches 'sh/wdt' and 'sh/rsk-updates' into sh-latest
Conflicts: arch/sh/Kconfig Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
commit
bcb86e0adb
@ -295,6 +295,13 @@ config CPU_SUBTYPE_SH7264
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select SYS_SUPPORTS_CMT
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select SYS_SUPPORTS_MTU2
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config CPU_SUBTYPE_SH7269
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bool "Support SH7269 processor"
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select CPU_SH2A
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select CPU_HAS_FPU
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select SYS_SUPPORTS_CMT
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select SYS_SUPPORTS_MTU2
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config CPU_SUBTYPE_MXG
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bool "Support MX-G processor"
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select CPU_SH2A
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@ -602,7 +609,8 @@ config SH_CLK_CPG_LEGACY
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depends on SH_CLK_CPG
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def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
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!CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \
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!CPU_SUBTYPE_SH7734 && !CPU_SUBTYPE_SH7264
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!CPU_SUBTYPE_SH7734 && !CPU_SUBTYPE_SH7264 && \
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!CPU_SUBTYPE_SH7269
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source "kernel/time/Kconfig"
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@ -133,7 +133,8 @@ config SH_RTS7751R2D
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config SH_RSK
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bool "Renesas Starter Kit"
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depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7264
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depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || \
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CPU_SUBTYPE_SH7264 || CPU_SUBTYPE_SH7269
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help
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Select this option if configuring for any of the RSK+ MCU
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evaluation platforms.
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@ -18,6 +18,11 @@ config SH_RSK7264
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select ARCH_REQUIRE_GPIOLIB
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depends on CPU_SUBTYPE_SH7264
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config SH_RSK7269
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bool "RSK2+SH7269"
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select ARCH_REQUIRE_GPIOLIB
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depends on CPU_SUBTYPE_SH7269
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endchoice
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endif
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@ -1,3 +1,4 @@
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obj-y := setup.o
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obj-$(CONFIG_SH_RSK7203) += devices-rsk7203.o
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obj-$(CONFIG_SH_RSK7264) += devices-rsk7264.o
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obj-$(CONFIG_SH_RSK7269) += devices-rsk7269.o
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60
arch/sh/boards/mach-rsk/devices-rsk7269.c
Normal file
60
arch/sh/boards/mach-rsk/devices-rsk7269.c
Normal file
@ -0,0 +1,60 @@
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/*
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* RSK+SH7269 Support
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*
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* Copyright (C) 2012 Renesas Electronics Europe Ltd
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* Copyright (C) 2012 Phil Edworthy
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/input.h>
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#include <linux/smsc911x.h>
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#include <linux/gpio.h>
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#include <asm/machvec.h>
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#include <asm/io.h>
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static struct smsc911x_platform_config smsc911x_config = {
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.phy_interface = PHY_INTERFACE_MODE_MII,
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
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.flags = SMSC911X_USE_16BIT | SMSC911X_SWAP_FIFO,
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};
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static struct resource smsc911x_resources[] = {
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[0] = {
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.start = 0x24000000,
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.end = 0x240000ff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 85,
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.end = 85,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smsc911x_device = {
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.name = "smsc911x",
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.id = -1,
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.num_resources = ARRAY_SIZE(smsc911x_resources),
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.resource = smsc911x_resources,
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.dev = {
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.platform_data = &smsc911x_config,
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},
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};
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static struct platform_device *rsk7269_devices[] __initdata = {
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&smsc911x_device,
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};
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static int __init rsk7269_devices_setup(void)
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{
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return platform_add_devices(rsk7269_devices,
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ARRAY_SIZE(rsk7269_devices));
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}
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device_initcall(rsk7269_devices_setup);
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65
arch/sh/configs/rsk7269_defconfig
Normal file
65
arch/sh/configs/rsk7269_defconfig
Normal file
@ -0,0 +1,65 @@
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CONFIG_LOG_BUF_SHIFT=14
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_EMBEDDED=y
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# CONFIG_VM_EVENT_COUNTERS is not set
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CONFIG_SLAB=y
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# CONFIG_LBDAF is not set
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# CONFIG_BLK_DEV_BSG is not set
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# CONFIG_IOSCHED_DEADLINE is not set
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# CONFIG_IOSCHED_CFQ is not set
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CONFIG_SWAP_IO_SPACE=y
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CONFIG_CPU_SUBTYPE_SH7269=y
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CONFIG_MEMORY_START=0x0c000000
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CONFIG_MEMORY_SIZE=0x02000000
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CONFIG_FLATMEM_MANUAL=y
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CONFIG_CPU_BIG_ENDIAN=y
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CONFIG_SH_RSK=y
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# CONFIG_SH_TIMER_MTU2 is not set
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CONFIG_SH_PCLK_FREQ=66700000
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CONFIG_BINFMT_FLAT=y
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CONFIG_NET=y
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CONFIG_INET=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
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# CONFIG_INET_XFRM_MODE_TUNNEL is not set
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# CONFIG_INET_XFRM_MODE_BEET is not set
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# CONFIG_INET_LRO is not set
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# CONFIG_INET_DIAG is not set
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# CONFIG_IPV6 is not set
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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# CONFIG_FW_LOADER is not set
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CONFIG_SCSI=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_NETDEVICES=y
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CONFIG_SMSC911X=y
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CONFIG_SMSC_PHY=y
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# CONFIG_INPUT_MOUSEDEV is not set
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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# CONFIG_SERIO is not set
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CONFIG_SERIAL_SH_SCI=y
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CONFIG_SERIAL_SH_SCI_NR_UARTS=8
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CONFIG_SERIAL_SH_SCI_CONSOLE=y
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# CONFIG_HWMON is not set
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CONFIG_USB=y
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CONFIG_USB_DEBUG=y
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CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
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# CONFIG_USB_DEVICE_CLASS is not set
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CONFIG_USB_R8A66597_HCD=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_STORAGE_DEBUG=y
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CONFIG_USB_LIBUSUAL=y
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CONFIG_EXT2_FS=y
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CONFIG_EXT3_FS=y
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# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
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CONFIG_VFAT_FS=y
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CONFIG_NFS_FS=y
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CONFIG_NFS_V3=y
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CONFIG_ROOT_NFS=y
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CONFIG_PARTITION_ADVANCED=y
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ISO8859_1=y
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# CONFIG_ENABLE_MUST_CHECK is not set
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CONFIG_SYSCTL_SYSCALL_CHECK=y
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# CONFIG_FTRACE is not set
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@ -18,7 +18,8 @@ enum cpu_type {
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CPU_SH7619,
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/* SH-2A types */
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CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_MXG,
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CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269,
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CPU_MXG,
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/* SH-3 types */
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CPU_SH7705, CPU_SH7706, CPU_SH7707,
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201
arch/sh/include/cpu-sh2a/cpu/sh7269.h
Normal file
201
arch/sh/include/cpu-sh2a/cpu/sh7269.h
Normal file
@ -0,0 +1,201 @@
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#ifndef __ASM_SH7269_H__
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#define __ASM_SH7269_H__
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enum {
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/* Port A */
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GPIO_PA1, GPIO_PA0,
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/* Port B */
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GPIO_PB22, GPIO_PB21, GPIO_PB20,
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GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16,
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GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12,
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GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8,
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GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
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GPIO_PB3, GPIO_PB2, GPIO_PB1,
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/* Port C */
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GPIO_PC8,
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GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
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GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
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/* Port D */
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GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12,
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GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8,
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GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
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GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
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/* Port E */
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GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4,
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GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
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/* Port F */
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GPIO_PF23, GPIO_PF22, GPIO_PF21, GPIO_PF20,
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GPIO_PF19, GPIO_PF18, GPIO_PF17, GPIO_PF16,
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GPIO_PF15, GPIO_PF14, GPIO_PF13, GPIO_PF12,
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GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8,
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GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
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GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
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/* Port G */
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GPIO_PG27, GPIO_PG26, GPIO_PG25, GPIO_PG24,
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GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20,
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GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16,
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GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12,
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GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8,
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GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
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GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
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/* Port H */
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GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
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GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
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/* Port I - not on device */
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/* Port J */
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GPIO_PJ31, GPIO_PJ30, GPIO_PJ29, GPIO_PJ28,
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GPIO_PJ27, GPIO_PJ26, GPIO_PJ25, GPIO_PJ24,
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GPIO_PJ23, GPIO_PJ22, GPIO_PJ21, GPIO_PJ20,
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GPIO_PJ19, GPIO_PJ18, GPIO_PJ17, GPIO_PJ16,
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GPIO_PJ15, GPIO_PJ14, GPIO_PJ13, GPIO_PJ12,
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GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8,
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GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
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GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
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/* INTC: IRQ and PINT */
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GPIO_FN_IRQ7_PG, GPIO_FN_IRQ6_PG, GPIO_FN_IRQ5_PG, GPIO_FN_IRQ4_PG,
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GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PG, GPIO_FN_IRQ0_PG,
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GPIO_FN_IRQ7_PF, GPIO_FN_IRQ6_PF, GPIO_FN_IRQ5_PF, GPIO_FN_IRQ4_PF,
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GPIO_FN_IRQ3_PJ, GPIO_FN_IRQ2_PJ, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ,
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GPIO_FN_IRQ1_PC, GPIO_FN_IRQ0_PC,
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GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG,
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GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG, GPIO_FN_PINT0_PG,
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GPIO_FN_PINT7_PH, GPIO_FN_PINT6_PH, GPIO_FN_PINT5_PH, GPIO_FN_PINT4_PH,
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GPIO_FN_PINT3_PH, GPIO_FN_PINT2_PH, GPIO_FN_PINT1_PH, GPIO_FN_PINT0_PH,
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GPIO_FN_PINT7_PJ, GPIO_FN_PINT6_PJ, GPIO_FN_PINT5_PJ, GPIO_FN_PINT4_PJ,
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||||
GPIO_FN_PINT3_PJ, GPIO_FN_PINT2_PJ, GPIO_FN_PINT1_PJ, GPIO_FN_PINT0_PJ,
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||||
|
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/* WDT */
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GPIO_FN_WDTOVF,
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||||
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||||
/* CAN */
|
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GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
|
||||
GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2,
|
||||
|
||||
/* DMAC */
|
||||
GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
|
||||
GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1,
|
||||
|
||||
/* ADC */
|
||||
GPIO_FN_ADTRG,
|
||||
|
||||
/* BSC */
|
||||
GPIO_FN_A25, GPIO_FN_A24,
|
||||
GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
|
||||
GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
|
||||
GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
|
||||
GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
|
||||
GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
|
||||
GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
|
||||
GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
|
||||
GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
|
||||
GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
|
||||
GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
|
||||
|
||||
GPIO_FN_BS,
|
||||
GPIO_FN_CS4, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_CS1, GPIO_FN_CS0,
|
||||
GPIO_FN_CS5CE1A,
|
||||
GPIO_FN_CE2A, GPIO_FN_CE2B,
|
||||
GPIO_FN_RD, GPIO_FN_RDWR,
|
||||
GPIO_FN_WE3ICIOWRAHDQMUU, GPIO_FN_WE2ICIORDDQMUL,
|
||||
GPIO_FN_WE1DQMUWE, GPIO_FN_WE0DQML,
|
||||
GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE,
|
||||
GPIO_FN_WAIT, GPIO_FN_BREQ, GPIO_FN_BACK,
|
||||
GPIO_FN_IOIS16,
|
||||
|
||||
/* TMU */
|
||||
GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A,
|
||||
GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A,
|
||||
GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A,
|
||||
GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
|
||||
GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
|
||||
|
||||
/* SSU */
|
||||
GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
|
||||
GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
|
||||
GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
|
||||
GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
|
||||
|
||||
/* SCIF */
|
||||
GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0,
|
||||
GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1,
|
||||
GPIO_FN_SCK2, GPIO_FN_RXD2, GPIO_FN_TXD2,
|
||||
GPIO_FN_SCK3, GPIO_FN_RXD3, GPIO_FN_TXD3,
|
||||
GPIO_FN_SCK4, GPIO_FN_RXD4, GPIO_FN_TXD4,
|
||||
GPIO_FN_SCK5, GPIO_FN_RXD5, GPIO_FN_TXD5, GPIO_FN_RTS5, GPIO_FN_CTS5,
|
||||
GPIO_FN_SCK6, GPIO_FN_RXD6, GPIO_FN_TXD6,
|
||||
GPIO_FN_SCK7, GPIO_FN_RXD7, GPIO_FN_TXD7, GPIO_FN_RTS7, GPIO_FN_CTS7,
|
||||
|
||||
/* RSPI */
|
||||
GPIO_FN_MISO0_PJ19, GPIO_FN_MISO0_PB20,
|
||||
GPIO_FN_MOSI0_PJ18, GPIO_FN_MOSI0_PB19,
|
||||
GPIO_FN_SSL00_PJ17, GPIO_FN_SSL00_PB18,
|
||||
GPIO_FN_RSPCK0_PJ16, GPIO_FN_RSPCK0_PB17,
|
||||
GPIO_FN_RSPCK1, GPIO_FN_MOSI1,
|
||||
GPIO_FN_MISO1, GPIO_FN_SSL10,
|
||||
|
||||
/* IIC3 */
|
||||
GPIO_FN_SCL0, GPIO_FN_SCL1, GPIO_FN_SCL2,
|
||||
GPIO_FN_SDA2, GPIO_FN_SDA1, GPIO_FN_SDA0,
|
||||
|
||||
/* SSI */
|
||||
GPIO_FN_SSISCK0, GPIO_FN_SSIWS0, GPIO_FN_SSITXD0, GPIO_FN_SSIRXD0,
|
||||
GPIO_FN_SSIWS1, GPIO_FN_SSIWS2, GPIO_FN_SSIWS3,
|
||||
GPIO_FN_SSISCK1, GPIO_FN_SSISCK2, GPIO_FN_SSISCK3,
|
||||
GPIO_FN_SSIDATA1, GPIO_FN_SSIDATA2, GPIO_FN_SSIDATA3,
|
||||
GPIO_FN_AUDIO_CLK,
|
||||
GPIO_FN_AUDIO_XOUT,
|
||||
|
||||
/* SIOF */
|
||||
GPIO_FN_SIOFTXD, GPIO_FN_SIOFRXD, GPIO_FN_SIOFSYNC, GPIO_FN_SIOFSCK,
|
||||
|
||||
/* SPDIF */
|
||||
GPIO_FN_SPDIF_IN,
|
||||
GPIO_FN_SPDIF_OUT,
|
||||
|
||||
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
|
||||
GPIO_FN_FCE,
|
||||
GPIO_FN_FRB,
|
||||
|
||||
/* VDC */
|
||||
GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
|
||||
GPIO_FN_DV_DATA23, GPIO_FN_DV_DATA22,
|
||||
GPIO_FN_DV_DATA21, GPIO_FN_DV_DATA20,
|
||||
GPIO_FN_DV_DATA19, GPIO_FN_DV_DATA18,
|
||||
GPIO_FN_DV_DATA17, GPIO_FN_DV_DATA16,
|
||||
GPIO_FN_DV_DATA15, GPIO_FN_DV_DATA14,
|
||||
GPIO_FN_DV_DATA13, GPIO_FN_DV_DATA12,
|
||||
GPIO_FN_DV_DATA11, GPIO_FN_DV_DATA10,
|
||||
GPIO_FN_DV_DATA9, GPIO_FN_DV_DATA8,
|
||||
GPIO_FN_DV_DATA7, GPIO_FN_DV_DATA6,
|
||||
GPIO_FN_DV_DATA5, GPIO_FN_DV_DATA4,
|
||||
GPIO_FN_DV_DATA3, GPIO_FN_DV_DATA2,
|
||||
GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0,
|
||||
GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK,
|
||||
GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE,
|
||||
GPIO_FN_LCD_DATA23, GPIO_FN_LCD_DATA22,
|
||||
GPIO_FN_LCD_DATA21, GPIO_FN_LCD_DATA20,
|
||||
GPIO_FN_LCD_DATA19, GPIO_FN_LCD_DATA18,
|
||||
GPIO_FN_LCD_DATA17, GPIO_FN_LCD_DATA16,
|
||||
GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
|
||||
GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
|
||||
GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
|
||||
GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
|
||||
GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
|
||||
GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
|
||||
GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
|
||||
GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
|
||||
GPIO_FN_LCD_M_DISP,
|
||||
};
|
||||
|
||||
#endif /* __ASM_SH7269_H__ */
|
||||
@ -7,7 +7,7 @@
|
||||
static const char *cpu_name[] = {
|
||||
[CPU_SH7201] = "SH7201",
|
||||
[CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
|
||||
[CPU_SH7264] = "SH7264",
|
||||
[CPU_SH7264] = "SH7264", [CPU_SH7269] = "SH7269",
|
||||
[CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
|
||||
[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
|
||||
[CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
|
||||
|
||||
@ -13,10 +13,12 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7264) += setup-sh7264.o clock-sh7264.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7269) += setup-sh7269.o clock-sh7269.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
|
||||
|
||||
# Pinmux setup
|
||||
pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o
|
||||
pinmux-$(CONFIG_CPU_SUBTYPE_SH7264) := pinmux-sh7264.o
|
||||
pinmux-$(CONFIG_CPU_SUBTYPE_SH7269) := pinmux-sh7269.o
|
||||
|
||||
obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y)
|
||||
|
||||
184
arch/sh/kernel/cpu/sh2a/clock-sh7269.c
Normal file
184
arch/sh/kernel/cpu/sh2a/clock-sh7269.c
Normal file
@ -0,0 +1,184 @@
|
||||
/*
|
||||
* arch/sh/kernel/cpu/sh2a/clock-sh7269.c
|
||||
*
|
||||
* SH7269 clock framework support
|
||||
*
|
||||
* Copyright (C) 2012 Phil Edworthy
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <asm/clock.h>
|
||||
|
||||
/* SH7269 registers */
|
||||
#define FRQCR 0xfffe0010
|
||||
#define STBCR3 0xfffe0408
|
||||
#define STBCR4 0xfffe040c
|
||||
#define STBCR5 0xfffe0410
|
||||
#define STBCR6 0xfffe0414
|
||||
#define STBCR7 0xfffe0418
|
||||
|
||||
#define PLL_RATE 20
|
||||
|
||||
/* Fixed 32 KHz root clock for RTC */
|
||||
static struct clk r_clk = {
|
||||
.rate = 32768,
|
||||
};
|
||||
|
||||
/*
|
||||
* Default rate for the root input clock, reset this with clk_set_rate()
|
||||
* from the platform code.
|
||||
*/
|
||||
static struct clk extal_clk = {
|
||||
.rate = 13340000,
|
||||
};
|
||||
|
||||
static unsigned long pll_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate * PLL_RATE;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops pll_clk_ops = {
|
||||
.recalc = pll_recalc,
|
||||
};
|
||||
|
||||
static struct clk pll_clk = {
|
||||
.ops = &pll_clk_ops,
|
||||
.parent = &extal_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
|
||||
static unsigned long peripheral0_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / 8;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops peripheral0_clk_ops = {
|
||||
.recalc = peripheral0_recalc,
|
||||
};
|
||||
|
||||
static struct clk peripheral0_clk = {
|
||||
.ops = &peripheral0_clk_ops,
|
||||
.parent = &pll_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
|
||||
static unsigned long peripheral1_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / 4;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops peripheral1_clk_ops = {
|
||||
.recalc = peripheral1_recalc,
|
||||
};
|
||||
|
||||
static struct clk peripheral1_clk = {
|
||||
.ops = &peripheral1_clk_ops,
|
||||
.parent = &pll_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
|
||||
struct clk *main_clks[] = {
|
||||
&r_clk,
|
||||
&extal_clk,
|
||||
&pll_clk,
|
||||
&peripheral0_clk,
|
||||
&peripheral1_clk,
|
||||
};
|
||||
|
||||
static int div2[] = { 1, 2, 0, 4 };
|
||||
|
||||
static struct clk_div_mult_table div4_div_mult_table = {
|
||||
.divisors = div2,
|
||||
.nr_divisors = ARRAY_SIZE(div2),
|
||||
};
|
||||
|
||||
static struct clk_div4_table div4_table = {
|
||||
.div_mult_table = &div4_div_mult_table,
|
||||
};
|
||||
|
||||
enum { DIV4_I, DIV4_B,
|
||||
DIV4_NR };
|
||||
|
||||
#define DIV4(_reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
|
||||
|
||||
/* The mask field specifies the div2 entries that are valid */
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
|
||||
| CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT
|
||||
| CLK_ENABLE_ON_INIT),
|
||||
};
|
||||
|
||||
enum { MSTP72,
|
||||
MSTP60,
|
||||
MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
|
||||
MSTP35, MSTP32, MSTP30,
|
||||
MSTP_NR };
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP72] = SH_CLK_MSTP8(&peripheral0_clk, STBCR7, 2, 0), /* CMT */
|
||||
[MSTP60] = SH_CLK_MSTP8(&peripheral1_clk, STBCR6, 0, 0), /* USB */
|
||||
[MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
|
||||
[MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
|
||||
[MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
|
||||
[MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
|
||||
[MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
|
||||
[MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
|
||||
[MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
|
||||
[MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
|
||||
[MSTP35] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 5, 0), /* MTU2 */
|
||||
[MSTP32] = SH_CLK_MSTP8(&peripheral1_clk, STBCR3, 2, 0), /* ADC */
|
||||
[MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("rclk", &r_clk),
|
||||
CLKDEV_CON_ID("extal", &extal_clk),
|
||||
CLKDEV_CON_ID("pll_clk", &pll_clk),
|
||||
CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
||||
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
|
||||
|
||||
/* MSTP clocks */
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
|
||||
CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP72]),
|
||||
CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
|
||||
CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP35]),
|
||||
CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
|
||||
CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
|
||||
};
|
||||
|
||||
int __init arch_clk_init(void)
|
||||
{
|
||||
int k, ret = 0;
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
||||
|
||||
return ret;
|
||||
}
|
||||
2799
arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
Normal file
2799
arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -32,6 +32,9 @@ void __cpuinit cpu_probe(void)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7264)
|
||||
boot_cpu_data.type = CPU_SH7264;
|
||||
boot_cpu_data.flags |= CPU_HAS_FPU;
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7269)
|
||||
boot_cpu_data.type = CPU_SH7269;
|
||||
boot_cpu_data.flags |= CPU_HAS_FPU;
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
boot_cpu_data.type = CPU_SH7206;
|
||||
boot_cpu_data.flags |= CPU_HAS_DSP;
|
||||
|
||||
615
arch/sh/kernel/cpu/sh2a/setup-sh7269.c
Normal file
615
arch/sh/kernel/cpu/sh2a/setup-sh7269.c
Normal file
@ -0,0 +1,615 @@
|
||||
/*
|
||||
* SH7269 Setup
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Electronics Europe Ltd
|
||||
* Copyright (C) 2012 Phil Edworthy
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/usb/r8a66597.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
enum {
|
||||
UNUSED = 0,
|
||||
|
||||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
|
||||
|
||||
DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
|
||||
DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
|
||||
USB, VDC4, CMT0, CMT1, BSC, WDT,
|
||||
MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
|
||||
MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
|
||||
PWMT1, PWMT2, ADC_ADI,
|
||||
SSIF0, SSII1, SSII2, SSII3, SSII4, SSII5,
|
||||
RSPDIF,
|
||||
IIC30, IIC31, IIC32, IIC33,
|
||||
SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
|
||||
SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
|
||||
SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
|
||||
SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
|
||||
SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
|
||||
SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
|
||||
SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
|
||||
SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
|
||||
RCAN0, RCAN1, RCAN2,
|
||||
RSPIC0, RSPIC1,
|
||||
IEBC, CD_ROMD,
|
||||
NFMC,
|
||||
SDHI0, SDHI1,
|
||||
RTC,
|
||||
SRCC0, SRCC1, SRCC2,
|
||||
|
||||
/* interrupt groups */
|
||||
PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
|
||||
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
|
||||
INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
|
||||
INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
|
||||
|
||||
INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
|
||||
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
|
||||
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
|
||||
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
|
||||
|
||||
INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
|
||||
INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
|
||||
INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
|
||||
INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
|
||||
INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
|
||||
INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
|
||||
INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
|
||||
INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
|
||||
INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
|
||||
INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
|
||||
INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
|
||||
INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
|
||||
INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
|
||||
INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
|
||||
INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
|
||||
INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
|
||||
|
||||
INTC_IRQ(USB, 170),
|
||||
|
||||
INTC_IRQ(VDC4, 171), INTC_IRQ(VDC4, 172),
|
||||
INTC_IRQ(VDC4, 173), INTC_IRQ(VDC4, 174),
|
||||
INTC_IRQ(VDC4, 175), INTC_IRQ(VDC4, 176),
|
||||
INTC_IRQ(VDC4, 177), INTC_IRQ(VDC4, 177),
|
||||
|
||||
INTC_IRQ(CMT0, 188), INTC_IRQ(CMT1, 189),
|
||||
|
||||
INTC_IRQ(BSC, 190), INTC_IRQ(WDT, 191),
|
||||
|
||||
INTC_IRQ(MTU0_ABCD, 192), INTC_IRQ(MTU0_ABCD, 193),
|
||||
INTC_IRQ(MTU0_ABCD, 194), INTC_IRQ(MTU0_ABCD, 195),
|
||||
INTC_IRQ(MTU0_VEF, 196), INTC_IRQ(MTU0_VEF, 197),
|
||||
INTC_IRQ(MTU0_VEF, 198),
|
||||
INTC_IRQ(MTU1_AB, 199), INTC_IRQ(MTU1_AB, 200),
|
||||
INTC_IRQ(MTU1_VU, 201), INTC_IRQ(MTU1_VU, 202),
|
||||
INTC_IRQ(MTU2_AB, 203), INTC_IRQ(MTU2_AB, 204),
|
||||
INTC_IRQ(MTU2_VU, 205), INTC_IRQ(MTU2_VU, 206),
|
||||
INTC_IRQ(MTU3_ABCD, 207), INTC_IRQ(MTU3_ABCD, 208),
|
||||
INTC_IRQ(MTU3_ABCD, 209), INTC_IRQ(MTU3_ABCD, 210),
|
||||
INTC_IRQ(MTU3_TCI3V, 211),
|
||||
INTC_IRQ(MTU4_ABCD, 212), INTC_IRQ(MTU4_ABCD, 213),
|
||||
INTC_IRQ(MTU4_ABCD, 214), INTC_IRQ(MTU4_ABCD, 215),
|
||||
INTC_IRQ(MTU4_TCI4V, 216),
|
||||
|
||||
INTC_IRQ(PWMT1, 217), INTC_IRQ(PWMT2, 218),
|
||||
|
||||
INTC_IRQ(ADC_ADI, 223),
|
||||
|
||||
INTC_IRQ(SSIF0, 224), INTC_IRQ(SSIF0, 225),
|
||||
INTC_IRQ(SSIF0, 226),
|
||||
INTC_IRQ(SSII1, 227), INTC_IRQ(SSII1, 228),
|
||||
INTC_IRQ(SSII2, 229), INTC_IRQ(SSII2, 230),
|
||||
INTC_IRQ(SSII3, 231), INTC_IRQ(SSII3, 232),
|
||||
INTC_IRQ(SSII4, 233), INTC_IRQ(SSII4, 234),
|
||||
INTC_IRQ(SSII5, 235), INTC_IRQ(SSII5, 236),
|
||||
|
||||
INTC_IRQ(RSPDIF, 237),
|
||||
|
||||
INTC_IRQ(IIC30, 238), INTC_IRQ(IIC30, 239),
|
||||
INTC_IRQ(IIC30, 240), INTC_IRQ(IIC30, 241),
|
||||
INTC_IRQ(IIC30, 242),
|
||||
INTC_IRQ(IIC31, 243), INTC_IRQ(IIC31, 244),
|
||||
INTC_IRQ(IIC31, 245), INTC_IRQ(IIC31, 246),
|
||||
INTC_IRQ(IIC31, 247),
|
||||
INTC_IRQ(IIC32, 248), INTC_IRQ(IIC32, 249),
|
||||
INTC_IRQ(IIC32, 250), INTC_IRQ(IIC32, 251),
|
||||
INTC_IRQ(IIC32, 252),
|
||||
INTC_IRQ(IIC33, 253), INTC_IRQ(IIC33, 254),
|
||||
INTC_IRQ(IIC33, 255), INTC_IRQ(IIC33, 256),
|
||||
INTC_IRQ(IIC33, 257),
|
||||
|
||||
INTC_IRQ(SCIF0_BRI, 258), INTC_IRQ(SCIF0_ERI, 259),
|
||||
INTC_IRQ(SCIF0_RXI, 260), INTC_IRQ(SCIF0_TXI, 261),
|
||||
INTC_IRQ(SCIF1_BRI, 262), INTC_IRQ(SCIF1_ERI, 263),
|
||||
INTC_IRQ(SCIF1_RXI, 264), INTC_IRQ(SCIF1_TXI, 265),
|
||||
INTC_IRQ(SCIF2_BRI, 266), INTC_IRQ(SCIF2_ERI, 267),
|
||||
INTC_IRQ(SCIF2_RXI, 268), INTC_IRQ(SCIF2_TXI, 269),
|
||||
INTC_IRQ(SCIF3_BRI, 270), INTC_IRQ(SCIF3_ERI, 271),
|
||||
INTC_IRQ(SCIF3_RXI, 272), INTC_IRQ(SCIF3_TXI, 273),
|
||||
INTC_IRQ(SCIF4_BRI, 274), INTC_IRQ(SCIF4_ERI, 275),
|
||||
INTC_IRQ(SCIF4_RXI, 276), INTC_IRQ(SCIF4_TXI, 277),
|
||||
INTC_IRQ(SCIF5_BRI, 278), INTC_IRQ(SCIF5_ERI, 279),
|
||||
INTC_IRQ(SCIF5_RXI, 280), INTC_IRQ(SCIF5_TXI, 281),
|
||||
INTC_IRQ(SCIF6_BRI, 282), INTC_IRQ(SCIF6_ERI, 283),
|
||||
INTC_IRQ(SCIF6_RXI, 284), INTC_IRQ(SCIF6_TXI, 285),
|
||||
INTC_IRQ(SCIF7_BRI, 286), INTC_IRQ(SCIF7_ERI, 287),
|
||||
INTC_IRQ(SCIF7_RXI, 288), INTC_IRQ(SCIF7_TXI, 289),
|
||||
|
||||
INTC_IRQ(RCAN0, 291), INTC_IRQ(RCAN0, 292),
|
||||
INTC_IRQ(RCAN0, 293), INTC_IRQ(RCAN0, 294),
|
||||
INTC_IRQ(RCAN0, 295),
|
||||
INTC_IRQ(RCAN1, 296), INTC_IRQ(RCAN1, 297),
|
||||
INTC_IRQ(RCAN1, 298), INTC_IRQ(RCAN1, 299),
|
||||
INTC_IRQ(RCAN1, 300),
|
||||
INTC_IRQ(RCAN2, 301), INTC_IRQ(RCAN2, 302),
|
||||
INTC_IRQ(RCAN2, 303), INTC_IRQ(RCAN2, 304),
|
||||
INTC_IRQ(RCAN2, 305),
|
||||
|
||||
INTC_IRQ(RSPIC0, 306), INTC_IRQ(RSPIC0, 307),
|
||||
INTC_IRQ(RSPIC0, 308),
|
||||
INTC_IRQ(RSPIC1, 309), INTC_IRQ(RSPIC1, 310),
|
||||
INTC_IRQ(RSPIC1, 311),
|
||||
|
||||
INTC_IRQ(IEBC, 318),
|
||||
|
||||
INTC_IRQ(CD_ROMD, 319), INTC_IRQ(CD_ROMD, 320),
|
||||
INTC_IRQ(CD_ROMD, 321), INTC_IRQ(CD_ROMD, 322),
|
||||
INTC_IRQ(CD_ROMD, 323), INTC_IRQ(CD_ROMD, 324),
|
||||
|
||||
INTC_IRQ(NFMC, 325), INTC_IRQ(NFMC, 326),
|
||||
INTC_IRQ(NFMC, 327), INTC_IRQ(NFMC, 328),
|
||||
|
||||
INTC_IRQ(SDHI0, 332), INTC_IRQ(SDHI0, 333),
|
||||
INTC_IRQ(SDHI0, 334),
|
||||
INTC_IRQ(SDHI1, 335), INTC_IRQ(SDHI1, 336),
|
||||
INTC_IRQ(SDHI1, 337),
|
||||
|
||||
INTC_IRQ(RTC, 338), INTC_IRQ(RTC, 339),
|
||||
INTC_IRQ(RTC, 340),
|
||||
|
||||
INTC_IRQ(SRCC0, 341), INTC_IRQ(SRCC0, 342),
|
||||
INTC_IRQ(SRCC0, 343), INTC_IRQ(SRCC0, 344),
|
||||
INTC_IRQ(SRCC0, 345),
|
||||
INTC_IRQ(SRCC1, 346), INTC_IRQ(SRCC1, 347),
|
||||
INTC_IRQ(SRCC1, 348), INTC_IRQ(SRCC1, 349),
|
||||
INTC_IRQ(SRCC1, 350),
|
||||
INTC_IRQ(SRCC2, 351), INTC_IRQ(SRCC2, 352),
|
||||
INTC_IRQ(SRCC2, 353), INTC_IRQ(SRCC2, 354),
|
||||
INTC_IRQ(SRCC2, 355),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
|
||||
PINT4, PINT5, PINT6, PINT7),
|
||||
INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
|
||||
INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
|
||||
INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
|
||||
INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
|
||||
INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
|
||||
INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
|
||||
INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
|
||||
{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
|
||||
{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
|
||||
{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
|
||||
DMAC10, DMAC11 } },
|
||||
{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
|
||||
DMAC14, DMAC15 } },
|
||||
{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC4, VDC4, VDC4 } },
|
||||
{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { CMT0, CMT1, BSC, WDT } },
|
||||
{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU0_ABCD, MTU0_VEF,
|
||||
MTU1_AB, MTU1_VU } },
|
||||
{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { MTU2_AB, MTU2_VU,
|
||||
MTU3_ABCD, MTU3_TCI3V } },
|
||||
{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { MTU4_ABCD, MTU4_TCI4V,
|
||||
PWMT1, PWMT2 } },
|
||||
{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { ADC_ADI, SSIF0, SSII1, SSII2 } },
|
||||
{ 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SSII3, SSII4, SSII5, RSPDIF} },
|
||||
{ 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { IIC30, IIC31, IIC32, IIC33 } },
|
||||
{ 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
|
||||
{ 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
|
||||
{ 0xfffe0c20, 0, 16, 4, /* IPR22 */ { 0, RCAN0, RCAN1, RCAN2 } },
|
||||
{ 0xfffe0c22, 0, 16, 4, /* IPR23 */ { RSPIC0, RSPIC1, 0, 0 } },
|
||||
{ 0xfffe0c24, 0, 16, 4, /* IPR24 */ { IEBC, CD_ROMD, NFMC, 0 } },
|
||||
{ 0xfffe0c26, 0, 16, 4, /* IPR25 */ { SDHI0, SDHI1, RTC, 0 } },
|
||||
{ 0xfffe0c28, 0, 16, 4, /* IPR26 */ { SRCC0, SRCC1, SRCC2, 0 } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xfffe0808, 0, 16, /* PINTER */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.mapbase = 0xe8007000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 259, 260, 261, 258 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif0_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &scif0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif1_platform_data = {
|
||||
.mapbase = 0xe8007800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 263, 264, 265, 262 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif1_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &scif1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif2_platform_data = {
|
||||
.mapbase = 0xe8008000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 267, 268, 269, 266 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif2_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
.platform_data = &scif2_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif3_platform_data = {
|
||||
.mapbase = 0xe8008800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 271, 272, 273, 270 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif3_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 3,
|
||||
.dev = {
|
||||
.platform_data = &scif3_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif4_platform_data = {
|
||||
.mapbase = 0xe8009000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 275, 276, 277, 274 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif4_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 4,
|
||||
.dev = {
|
||||
.platform_data = &scif4_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif5_platform_data = {
|
||||
.mapbase = 0xe8009800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 279, 280, 281, 278 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif5_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 5,
|
||||
.dev = {
|
||||
.platform_data = &scif5_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif6_platform_data = {
|
||||
.mapbase = 0xe800a000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 283, 284, 285, 282 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif6_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 6,
|
||||
.dev = {
|
||||
.platform_data = &scif6_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif7_platform_data = {
|
||||
.mapbase = 0xe800a800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 287, 288, 289, 286 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif7_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 7,
|
||||
.dev = {
|
||||
.platform_data = &scif7_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_timer_config cmt0_platform_data = {
|
||||
.channel_offset = 0x02,
|
||||
.timer_bit = 0,
|
||||
.clockevent_rating = 125,
|
||||
.clocksource_rating = 0, /* disabled due to code generation issues */
|
||||
};
|
||||
|
||||
static struct resource cmt0_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffec002,
|
||||
.end = 0xfffec007,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 188,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device cmt0_device = {
|
||||
.name = "sh_cmt",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &cmt0_platform_data,
|
||||
},
|
||||
.resource = cmt0_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt0_resources),
|
||||
};
|
||||
|
||||
static struct sh_timer_config cmt1_platform_data = {
|
||||
.channel_offset = 0x08,
|
||||
.timer_bit = 1,
|
||||
.clockevent_rating = 125,
|
||||
.clocksource_rating = 0, /* disabled due to code generation issues */
|
||||
};
|
||||
|
||||
static struct resource cmt1_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffec008,
|
||||
.end = 0xfffec00d,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 189,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device cmt1_device = {
|
||||
.name = "sh_cmt",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &cmt1_platform_data,
|
||||
},
|
||||
.resource = cmt1_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt1_resources),
|
||||
};
|
||||
|
||||
static struct sh_timer_config mtu2_0_platform_data = {
|
||||
.channel_offset = -0x80,
|
||||
.timer_bit = 0,
|
||||
.clockevent_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource mtu2_0_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffe4300,
|
||||
.end = 0xfffe4326,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 192,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device mtu2_0_device = {
|
||||
.name = "sh_mtu2",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &mtu2_0_platform_data,
|
||||
},
|
||||
.resource = mtu2_0_resources,
|
||||
.num_resources = ARRAY_SIZE(mtu2_0_resources),
|
||||
};
|
||||
|
||||
static struct sh_timer_config mtu2_1_platform_data = {
|
||||
.channel_offset = -0x100,
|
||||
.timer_bit = 1,
|
||||
.clockevent_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource mtu2_1_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffe4380,
|
||||
.end = 0xfffe4390,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 203,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device mtu2_1_device = {
|
||||
.name = "sh_mtu2",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &mtu2_1_platform_data,
|
||||
},
|
||||
.resource = mtu2_1_resources,
|
||||
.num_resources = ARRAY_SIZE(mtu2_1_resources),
|
||||
};
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffe6000,
|
||||
.end = 0xfffe6000 + 0x30 - 1,
|
||||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 338,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device rtc_device = {
|
||||
.name = "sh-rtc",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resource = rtc_resources,
|
||||
};
|
||||
|
||||
/* USB Host */
|
||||
static struct r8a66597_platdata r8a66597_data = {
|
||||
.on_chip = 1,
|
||||
.endian = 1,
|
||||
};
|
||||
|
||||
static struct resource r8a66597_usb_host_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xe8010000,
|
||||
.end = 0xe80100e4,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 170,
|
||||
.end = 170,
|
||||
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device r8a66597_usb_host_device = {
|
||||
.name = "r8a66597_hcd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = NULL, /* not use dma */
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
.platform_data = &r8a66597_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
|
||||
.resource = r8a66597_usb_host_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *sh7269_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&scif6_device,
|
||||
&scif7_device,
|
||||
&cmt0_device,
|
||||
&cmt1_device,
|
||||
&mtu2_0_device,
|
||||
&mtu2_1_device,
|
||||
&rtc_device,
|
||||
&r8a66597_usb_host_device,
|
||||
};
|
||||
|
||||
static int __init sh7269_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7269_devices,
|
||||
ARRAY_SIZE(sh7269_devices));
|
||||
}
|
||||
arch_initcall(sh7269_devices_setup);
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
static struct platform_device *sh7269_early_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&scif6_device,
|
||||
&scif7_device,
|
||||
&cmt0_device,
|
||||
&cmt1_device,
|
||||
&mtu2_0_device,
|
||||
&mtu2_1_device,
|
||||
};
|
||||
|
||||
void __init plat_early_device_setup(void)
|
||||
{
|
||||
early_platform_add_devices(sh7269_early_devices,
|
||||
ARRAY_SIZE(sh7269_early_devices));
|
||||
}
|
||||
@ -52,6 +52,7 @@ MIGOR SH_MIGOR
|
||||
RSK7201 SH_RSK7201
|
||||
RSK7203 SH_RSK7203
|
||||
RSK7264 SH_RSK7264
|
||||
RSK7269 SH_RSK7269
|
||||
AP325RXA SH_AP325RXA
|
||||
SH2007 SH_SH2007
|
||||
SH7757LCR SH_SH7757LCR
|
||||
|
||||
@ -1138,6 +1138,7 @@ config ZVM_WATCHDOG
|
||||
config SH_WDT
|
||||
tristate "SuperH Watchdog"
|
||||
depends on SUPERH && (CPU_SH3 || CPU_SH4)
|
||||
select WATCHDOG_CORE
|
||||
help
|
||||
This driver adds watchdog support for the integrated watchdog in the
|
||||
SuperH processors. If you have one of these processors and wish
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* Watchdog driver for integrated watchdog in the SuperH processors.
|
||||
*
|
||||
* Copyright (C) 2001 - 2010 Paul Mundt <lethal@linux-sh.org>
|
||||
* Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
@ -25,16 +25,15 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/watchdog.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/clk.h>
|
||||
#include <asm/watchdog.h>
|
||||
|
||||
#define DRV_NAME "sh-wdt"
|
||||
@ -69,10 +68,6 @@
|
||||
static int clock_division_ratio = WTCSR_CKS_4096;
|
||||
#define next_ping_period(cks) (jiffies + msecs_to_jiffies(cks - 4))
|
||||
|
||||
static const struct watchdog_info sh_wdt_info;
|
||||
static struct platform_device *sh_wdt_dev;
|
||||
static DEFINE_SPINLOCK(shwdt_lock);
|
||||
|
||||
#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
|
||||
static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
|
||||
static bool nowayout = WATCHDOG_NOWAYOUT;
|
||||
@ -81,19 +76,22 @@ static unsigned long next_heartbeat;
|
||||
struct sh_wdt {
|
||||
void __iomem *base;
|
||||
struct device *dev;
|
||||
struct clk *clk;
|
||||
spinlock_t lock;
|
||||
|
||||
struct timer_list timer;
|
||||
|
||||
unsigned long enabled;
|
||||
char expect_close;
|
||||
};
|
||||
|
||||
static void sh_wdt_start(struct sh_wdt *wdt)
|
||||
static int sh_wdt_start(struct watchdog_device *wdt_dev)
|
||||
{
|
||||
struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
|
||||
unsigned long flags;
|
||||
u8 csr;
|
||||
|
||||
spin_lock_irqsave(&shwdt_lock, flags);
|
||||
pm_runtime_get_sync(wdt->dev);
|
||||
clk_enable(wdt->clk);
|
||||
|
||||
spin_lock_irqsave(&wdt->lock, flags);
|
||||
|
||||
next_heartbeat = jiffies + (heartbeat * HZ);
|
||||
mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
|
||||
@ -122,15 +120,18 @@ static void sh_wdt_start(struct sh_wdt *wdt)
|
||||
csr &= ~RSTCSR_RSTS;
|
||||
sh_wdt_write_rstcsr(csr);
|
||||
#endif
|
||||
spin_unlock_irqrestore(&shwdt_lock, flags);
|
||||
spin_unlock_irqrestore(&wdt->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sh_wdt_stop(struct sh_wdt *wdt)
|
||||
static int sh_wdt_stop(struct watchdog_device *wdt_dev)
|
||||
{
|
||||
struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
|
||||
unsigned long flags;
|
||||
u8 csr;
|
||||
|
||||
spin_lock_irqsave(&shwdt_lock, flags);
|
||||
spin_lock_irqsave(&wdt->lock, flags);
|
||||
|
||||
del_timer(&wdt->timer);
|
||||
|
||||
@ -138,28 +139,39 @@ static void sh_wdt_stop(struct sh_wdt *wdt)
|
||||
csr &= ~WTCSR_TME;
|
||||
sh_wdt_write_csr(csr);
|
||||
|
||||
spin_unlock_irqrestore(&shwdt_lock, flags);
|
||||
spin_unlock_irqrestore(&wdt->lock, flags);
|
||||
|
||||
clk_disable(wdt->clk);
|
||||
pm_runtime_put_sync(wdt->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void sh_wdt_keepalive(struct sh_wdt *wdt)
|
||||
static int sh_wdt_keepalive(struct watchdog_device *wdt_dev)
|
||||
{
|
||||
struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&shwdt_lock, flags);
|
||||
spin_lock_irqsave(&wdt->lock, flags);
|
||||
next_heartbeat = jiffies + (heartbeat * HZ);
|
||||
spin_unlock_irqrestore(&shwdt_lock, flags);
|
||||
spin_unlock_irqrestore(&wdt->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_wdt_set_heartbeat(int t)
|
||||
static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t)
|
||||
{
|
||||
struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
|
||||
unsigned long flags;
|
||||
|
||||
if (unlikely(t < 1 || t > 3600)) /* arbitrary upper limit */
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&shwdt_lock, flags);
|
||||
spin_lock_irqsave(&wdt->lock, flags);
|
||||
heartbeat = t;
|
||||
spin_unlock_irqrestore(&shwdt_lock, flags);
|
||||
wdt_dev->timeout = t;
|
||||
spin_unlock_irqrestore(&wdt->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -168,7 +180,7 @@ static void sh_wdt_ping(unsigned long data)
|
||||
struct sh_wdt *wdt = (struct sh_wdt *)data;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&shwdt_lock, flags);
|
||||
spin_lock_irqsave(&wdt->lock, flags);
|
||||
if (time_before(jiffies, next_heartbeat)) {
|
||||
u8 csr;
|
||||
|
||||
@ -182,137 +194,9 @@ static void sh_wdt_ping(unsigned long data)
|
||||
} else
|
||||
dev_warn(wdt->dev, "Heartbeat lost! Will not ping "
|
||||
"the watchdog\n");
|
||||
spin_unlock_irqrestore(&shwdt_lock, flags);
|
||||
spin_unlock_irqrestore(&wdt->lock, flags);
|
||||
}
|
||||
|
||||
static int sh_wdt_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
struct sh_wdt *wdt = platform_get_drvdata(sh_wdt_dev);
|
||||
|
||||
if (test_and_set_bit(0, &wdt->enabled))
|
||||
return -EBUSY;
|
||||
if (nowayout)
|
||||
__module_get(THIS_MODULE);
|
||||
|
||||
file->private_data = wdt;
|
||||
|
||||
sh_wdt_start(wdt);
|
||||
|
||||
return nonseekable_open(inode, file);
|
||||
}
|
||||
|
||||
static int sh_wdt_close(struct inode *inode, struct file *file)
|
||||
{
|
||||
struct sh_wdt *wdt = file->private_data;
|
||||
|
||||
if (wdt->expect_close == 42) {
|
||||
sh_wdt_stop(wdt);
|
||||
} else {
|
||||
dev_crit(wdt->dev, "Unexpected close, not "
|
||||
"stopping watchdog!\n");
|
||||
sh_wdt_keepalive(wdt);
|
||||
}
|
||||
|
||||
clear_bit(0, &wdt->enabled);
|
||||
wdt->expect_close = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ssize_t sh_wdt_write(struct file *file, const char *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct sh_wdt *wdt = file->private_data;
|
||||
|
||||
if (count) {
|
||||
if (!nowayout) {
|
||||
size_t i;
|
||||
|
||||
wdt->expect_close = 0;
|
||||
|
||||
for (i = 0; i != count; i++) {
|
||||
char c;
|
||||
if (get_user(c, buf + i))
|
||||
return -EFAULT;
|
||||
if (c == 'V')
|
||||
wdt->expect_close = 42;
|
||||
}
|
||||
}
|
||||
sh_wdt_keepalive(wdt);
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static long sh_wdt_ioctl(struct file *file, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct sh_wdt *wdt = file->private_data;
|
||||
int new_heartbeat;
|
||||
int options, retval = -EINVAL;
|
||||
|
||||
switch (cmd) {
|
||||
case WDIOC_GETSUPPORT:
|
||||
return copy_to_user((struct watchdog_info *)arg,
|
||||
&sh_wdt_info, sizeof(sh_wdt_info)) ? -EFAULT : 0;
|
||||
case WDIOC_GETSTATUS:
|
||||
case WDIOC_GETBOOTSTATUS:
|
||||
return put_user(0, (int *)arg);
|
||||
case WDIOC_SETOPTIONS:
|
||||
if (get_user(options, (int *)arg))
|
||||
return -EFAULT;
|
||||
|
||||
if (options & WDIOS_DISABLECARD) {
|
||||
sh_wdt_stop(wdt);
|
||||
retval = 0;
|
||||
}
|
||||
|
||||
if (options & WDIOS_ENABLECARD) {
|
||||
sh_wdt_start(wdt);
|
||||
retval = 0;
|
||||
}
|
||||
|
||||
return retval;
|
||||
case WDIOC_KEEPALIVE:
|
||||
sh_wdt_keepalive(wdt);
|
||||
return 0;
|
||||
case WDIOC_SETTIMEOUT:
|
||||
if (get_user(new_heartbeat, (int *)arg))
|
||||
return -EFAULT;
|
||||
|
||||
if (sh_wdt_set_heartbeat(new_heartbeat))
|
||||
return -EINVAL;
|
||||
|
||||
sh_wdt_keepalive(wdt);
|
||||
/* Fall */
|
||||
case WDIOC_GETTIMEOUT:
|
||||
return put_user(heartbeat, (int *)arg);
|
||||
default:
|
||||
return -ENOTTY;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_wdt_notify_sys(struct notifier_block *this,
|
||||
unsigned long code, void *unused)
|
||||
{
|
||||
struct sh_wdt *wdt = platform_get_drvdata(sh_wdt_dev);
|
||||
|
||||
if (code == SYS_DOWN || code == SYS_HALT)
|
||||
sh_wdt_stop(wdt);
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static const struct file_operations sh_wdt_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.llseek = no_llseek,
|
||||
.write = sh_wdt_write,
|
||||
.unlocked_ioctl = sh_wdt_ioctl,
|
||||
.open = sh_wdt_open,
|
||||
.release = sh_wdt_close,
|
||||
};
|
||||
|
||||
static const struct watchdog_info sh_wdt_info = {
|
||||
.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
|
||||
WDIOF_MAGICCLOSE,
|
||||
@ -320,14 +204,17 @@ static const struct watchdog_info sh_wdt_info = {
|
||||
.identity = "SH WDT",
|
||||
};
|
||||
|
||||
static struct notifier_block sh_wdt_notifier = {
|
||||
.notifier_call = sh_wdt_notify_sys,
|
||||
static const struct watchdog_ops sh_wdt_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.start = sh_wdt_start,
|
||||
.stop = sh_wdt_stop,
|
||||
.ping = sh_wdt_keepalive,
|
||||
.set_timeout = sh_wdt_set_heartbeat,
|
||||
};
|
||||
|
||||
static struct miscdevice sh_wdt_miscdev = {
|
||||
.minor = WATCHDOG_MINOR,
|
||||
.name = "watchdog",
|
||||
.fops = &sh_wdt_fops,
|
||||
static struct watchdog_device sh_wdt_dev = {
|
||||
.info = &sh_wdt_info,
|
||||
.ops = &sh_wdt_ops,
|
||||
};
|
||||
|
||||
static int __devinit sh_wdt_probe(struct platform_device *pdev)
|
||||
@ -347,39 +234,49 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev)
|
||||
if (unlikely(!res))
|
||||
return -EINVAL;
|
||||
|
||||
if (!devm_request_mem_region(&pdev->dev, res->start,
|
||||
resource_size(res), DRV_NAME))
|
||||
return -EBUSY;
|
||||
|
||||
wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL);
|
||||
if (unlikely(!wdt)) {
|
||||
rc = -ENOMEM;
|
||||
goto out_release;
|
||||
}
|
||||
if (unlikely(!wdt))
|
||||
return -ENOMEM;
|
||||
|
||||
wdt->dev = &pdev->dev;
|
||||
|
||||
wdt->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
|
||||
wdt->clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(wdt->clk)) {
|
||||
/*
|
||||
* Clock framework support is optional, continue on
|
||||
* anyways if we don't find a matching clock.
|
||||
*/
|
||||
wdt->clk = NULL;
|
||||
}
|
||||
|
||||
wdt->base = devm_request_and_ioremap(wdt->dev, res);
|
||||
if (unlikely(!wdt->base)) {
|
||||
rc = -ENXIO;
|
||||
goto out_err;
|
||||
rc = -EADDRNOTAVAIL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
rc = register_reboot_notifier(&sh_wdt_notifier);
|
||||
watchdog_set_nowayout(&sh_wdt_dev, nowayout);
|
||||
watchdog_set_drvdata(&sh_wdt_dev, wdt);
|
||||
|
||||
spin_lock_init(&wdt->lock);
|
||||
|
||||
rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat);
|
||||
if (unlikely(rc)) {
|
||||
dev_err(&pdev->dev,
|
||||
"Can't register reboot notifier (err=%d)\n", rc);
|
||||
goto out_unmap;
|
||||
/* Default timeout if invalid */
|
||||
sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT);
|
||||
|
||||
dev_warn(&pdev->dev,
|
||||
"heartbeat value must be 1<=x<=3600, using %d\n",
|
||||
sh_wdt_dev.timeout);
|
||||
}
|
||||
|
||||
sh_wdt_miscdev.parent = wdt->dev;
|
||||
dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n",
|
||||
sh_wdt_dev.timeout, nowayout);
|
||||
|
||||
rc = misc_register(&sh_wdt_miscdev);
|
||||
rc = watchdog_register_device(&sh_wdt_dev);
|
||||
if (unlikely(rc)) {
|
||||
dev_err(&pdev->dev,
|
||||
"Can't register miscdev on minor=%d (err=%d)\n",
|
||||
sh_wdt_miscdev.minor, rc);
|
||||
goto out_unreg;
|
||||
dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc);
|
||||
goto err;
|
||||
}
|
||||
|
||||
init_timer(&wdt->timer);
|
||||
@ -388,20 +285,15 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev)
|
||||
wdt->timer.expires = next_ping_period(clock_division_ratio);
|
||||
|
||||
platform_set_drvdata(pdev, wdt);
|
||||
sh_wdt_dev = pdev;
|
||||
|
||||
dev_info(&pdev->dev, "initialized.\n");
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
|
||||
out_unreg:
|
||||
unregister_reboot_notifier(&sh_wdt_notifier);
|
||||
out_unmap:
|
||||
devm_iounmap(&pdev->dev, wdt->base);
|
||||
out_err:
|
||||
devm_kfree(&pdev->dev, wdt);
|
||||
out_release:
|
||||
devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
|
||||
err:
|
||||
clk_put(wdt->clk);
|
||||
|
||||
return rc;
|
||||
}
|
||||
@ -409,36 +301,35 @@ out_release:
|
||||
static int __devexit sh_wdt_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_wdt *wdt = platform_get_drvdata(pdev);
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
misc_deregister(&sh_wdt_miscdev);
|
||||
watchdog_unregister_device(&sh_wdt_dev);
|
||||
|
||||
sh_wdt_dev = NULL;
|
||||
|
||||
unregister_reboot_notifier(&sh_wdt_notifier);
|
||||
devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
|
||||
devm_iounmap(&pdev->dev, wdt->base);
|
||||
devm_kfree(&pdev->dev, wdt);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
clk_put(wdt->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sh_wdt_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
sh_wdt_stop(&sh_wdt_dev);
|
||||
}
|
||||
|
||||
static struct platform_driver sh_wdt_driver = {
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
|
||||
.probe = sh_wdt_probe,
|
||||
.remove = __devexit_p(sh_wdt_remove),
|
||||
.probe = sh_wdt_probe,
|
||||
.remove = __devexit_p(sh_wdt_remove),
|
||||
.shutdown = sh_wdt_shutdown,
|
||||
};
|
||||
|
||||
static int __init sh_wdt_init(void)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (unlikely(clock_division_ratio < 0x5 ||
|
||||
clock_division_ratio > 0x7)) {
|
||||
clock_division_ratio = WTCSR_CKS_4096;
|
||||
@ -447,17 +338,6 @@ static int __init sh_wdt_init(void)
|
||||
clock_division_ratio);
|
||||
}
|
||||
|
||||
rc = sh_wdt_set_heartbeat(heartbeat);
|
||||
if (unlikely(rc)) {
|
||||
heartbeat = WATCHDOG_HEARTBEAT;
|
||||
|
||||
pr_info("heartbeat value must be 1<=x<=3600, using %d\n",
|
||||
heartbeat);
|
||||
}
|
||||
|
||||
pr_info("configured with heartbeat=%d sec (nowayout=%d)\n",
|
||||
heartbeat, nowayout);
|
||||
|
||||
return platform_driver_register(&sh_wdt_driver);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user