forked from Minki/linux
Merge series "spi: Fixes for FSI-attached controller" from Eddie James <eajames@linux.ibm.com>:
This series implements a number of fixes for the FSI-attached SPI
controller driver.
Changes since v1:
- Switch to a new compatible string for the restricted version of the
SPI controller, rather than a new boolean parameter.
Brad Bishop (3):
spi: fsi: Handle 9 to 15 byte transfers lengths
spi: fsi: Fix clock running too fast
spi: fsi: Fix use of the bneq+ sequencer instruction
Eddie James (3):
dt-bindings: fsi: fsi2spi: Add compatible string for restricted
version
spi: fsi: Implement restricted size for certain controllers
spi: fsi: Check mux status before transfers
.../devicetree/bindings/fsi/ibm,fsi2spi.yaml | 1 +
drivers/spi/spi-fsi.c | 139 ++++++++++++++----
2 files changed, 109 insertions(+), 31 deletions(-)
--
2.26.2
This commit is contained in:
Mark Brown
commit
bc3d924399
@ -19,6 +19,7 @@ properties:
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compatible:
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enum:
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- ibm,fsi2spi
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- ibm,fsi2spi-restricted
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reg:
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items:
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@ -12,6 +12,7 @@
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#define FSI_ENGID_SPI 0x23
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#define FSI_MBOX_ROOT_CTRL_8 0x2860
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#define FSI_MBOX_ROOT_CTRL_8_SPI_MUX 0xf0000000
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#define FSI2SPI_DATA0 0x00
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#define FSI2SPI_DATA1 0x04
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@ -24,11 +25,16 @@
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#define SPI_FSI_BASE 0x70000
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#define SPI_FSI_INIT_TIMEOUT_MS 1000
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#define SPI_FSI_MAX_TRANSFER_SIZE 2048
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#define SPI_FSI_MAX_XFR_SIZE 2048
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#define SPI_FSI_MAX_XFR_SIZE_RESTRICTED 32
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#define SPI_FSI_ERROR 0x0
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#define SPI_FSI_COUNTER_CFG 0x1
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#define SPI_FSI_COUNTER_CFG_LOOPS(x) (((u64)(x) & 0xffULL) << 32)
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#define SPI_FSI_COUNTER_CFG_N2_RX BIT_ULL(8)
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#define SPI_FSI_COUNTER_CFG_N2_TX BIT_ULL(9)
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#define SPI_FSI_COUNTER_CFG_N2_IMPLICIT BIT_ULL(10)
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#define SPI_FSI_COUNTER_CFG_N2_RELOAD BIT_ULL(11)
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#define SPI_FSI_CFG1 0x2
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#define SPI_FSI_CLOCK_CFG 0x3
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#define SPI_FSI_CLOCK_CFG_MM_ENABLE BIT_ULL(32)
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@ -61,7 +67,7 @@
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#define SPI_FSI_STATUS_RDR_OVERRUN BIT_ULL(62)
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#define SPI_FSI_STATUS_RDR_FULL BIT_ULL(63)
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#define SPI_FSI_STATUS_ANY_ERROR \
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(SPI_FSI_STATUS_ERROR | SPI_FSI_STATUS_TDR_UNDERRUN | \
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(SPI_FSI_STATUS_ERROR | \
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SPI_FSI_STATUS_TDR_OVERRUN | SPI_FSI_STATUS_RDR_UNDERRUN | \
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SPI_FSI_STATUS_RDR_OVERRUN)
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#define SPI_FSI_PORT_CTRL 0x9
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@ -70,6 +76,8 @@ struct fsi_spi {
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struct device *dev; /* SPI controller device */
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struct fsi_device *fsi; /* FSI2SPI CFAM engine device */
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u32 base;
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size_t max_xfr_size;
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bool restricted;
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};
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struct fsi_spi_sequence {
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@ -77,6 +85,26 @@ struct fsi_spi_sequence {
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u64 data;
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};
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static int fsi_spi_check_mux(struct fsi_device *fsi, struct device *dev)
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{
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int rc;
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u32 root_ctrl_8;
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__be32 root_ctrl_8_be;
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rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8_be,
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sizeof(root_ctrl_8_be));
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if (rc)
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return rc;
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root_ctrl_8 = be32_to_cpu(root_ctrl_8_be);
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dev_dbg(dev, "Root control register 8: %08x\n", root_ctrl_8);
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if ((root_ctrl_8 & FSI_MBOX_ROOT_CTRL_8_SPI_MUX) ==
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FSI_MBOX_ROOT_CTRL_8_SPI_MUX)
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return 0;
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return -ENOLINK;
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}
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static int fsi_spi_check_status(struct fsi_spi *ctx)
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{
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int rc;
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@ -205,8 +233,12 @@ static int fsi_spi_reset(struct fsi_spi *ctx)
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if (rc)
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return rc;
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return fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
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SPI_FSI_CLOCK_CFG_RESET2);
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rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
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SPI_FSI_CLOCK_CFG_RESET2);
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if (rc)
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return rc;
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return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL);
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}
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static int fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val)
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@ -214,8 +246,8 @@ static int fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val)
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/*
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* Add the next byte of instruction to the 8-byte sequence register.
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* Then decrement the counter so that the next instruction will go in
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* the right place. Return the number of "slots" left in the sequence
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* register.
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* the right place. Return the index of the slot we just filled in the
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* sequence register.
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*/
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seq->data |= (u64)val << seq->bit;
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seq->bit -= 8;
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@ -233,40 +265,71 @@ static int fsi_spi_sequence_transfer(struct fsi_spi *ctx,
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struct fsi_spi_sequence *seq,
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struct spi_transfer *transfer)
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{
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bool docfg = false;
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int loops;
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int idx;
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int rc;
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u8 val = 0;
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u8 len = min(transfer->len, 8U);
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u8 rem = transfer->len % len;
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u64 cfg = 0ULL;
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loops = transfer->len / len;
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if (transfer->tx_buf) {
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idx = fsi_spi_sequence_add(seq,
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SPI_FSI_SEQUENCE_SHIFT_OUT(len));
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val = SPI_FSI_SEQUENCE_SHIFT_OUT(len);
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idx = fsi_spi_sequence_add(seq, val);
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if (rem)
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rem = SPI_FSI_SEQUENCE_SHIFT_OUT(rem);
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} else if (transfer->rx_buf) {
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idx = fsi_spi_sequence_add(seq,
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SPI_FSI_SEQUENCE_SHIFT_IN(len));
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val = SPI_FSI_SEQUENCE_SHIFT_IN(len);
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idx = fsi_spi_sequence_add(seq, val);
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if (rem)
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rem = SPI_FSI_SEQUENCE_SHIFT_IN(rem);
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} else {
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return -EINVAL;
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}
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if (ctx->restricted) {
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const int eidx = rem ? 5 : 6;
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while (loops > 1 && idx <= eidx) {
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idx = fsi_spi_sequence_add(seq, val);
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loops--;
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docfg = true;
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}
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if (loops > 1) {
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dev_warn(ctx->dev, "No sequencer slots; aborting.\n");
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return -EINVAL;
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}
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}
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if (loops > 1) {
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fsi_spi_sequence_add(seq, SPI_FSI_SEQUENCE_BRANCH(idx));
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docfg = true;
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}
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if (rem)
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fsi_spi_sequence_add(seq, rem);
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if (docfg) {
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cfg = SPI_FSI_COUNTER_CFG_LOOPS(loops - 1);
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if (transfer->rx_buf)
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cfg |= SPI_FSI_COUNTER_CFG_N2_RX |
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SPI_FSI_COUNTER_CFG_N2_TX |
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SPI_FSI_COUNTER_CFG_N2_IMPLICIT |
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SPI_FSI_COUNTER_CFG_N2_RELOAD;
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rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG,
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SPI_FSI_COUNTER_CFG_LOOPS(loops - 1));
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rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, cfg);
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if (rc)
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return rc;
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} else {
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fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL);
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}
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if (rem)
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fsi_spi_sequence_add(seq, rem);
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return 0;
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}
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@ -275,6 +338,7 @@ static int fsi_spi_transfer_data(struct fsi_spi *ctx,
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{
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int rc = 0;
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u64 status = 0ULL;
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u64 cfg = 0ULL;
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if (transfer->tx_buf) {
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int nb;
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@ -312,6 +376,16 @@ static int fsi_spi_transfer_data(struct fsi_spi *ctx,
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u64 in = 0ULL;
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u8 *rx = transfer->rx_buf;
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rc = fsi_spi_read_reg(ctx, SPI_FSI_COUNTER_CFG, &cfg);
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if (rc)
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return rc;
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if (cfg & SPI_FSI_COUNTER_CFG_N2_IMPLICIT) {
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rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, 0);
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if (rc)
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return rc;
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}
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while (transfer->len > recv) {
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do {
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rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS,
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@ -350,7 +424,7 @@ static int fsi_spi_transfer_init(struct fsi_spi *ctx)
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u64 status = 0ULL;
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u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE |
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SPI_FSI_CLOCK_CFG_SCK_NO_DEL |
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FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 4);
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FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19);
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end = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS);
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do {
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@ -396,18 +470,22 @@ static int fsi_spi_transfer_init(struct fsi_spi *ctx)
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static int fsi_spi_transfer_one_message(struct spi_controller *ctlr,
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struct spi_message *mesg)
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{
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int rc = 0;
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int rc;
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u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(mesg->spi->chip_select + 1);
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struct spi_transfer *transfer;
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struct fsi_spi *ctx = spi_controller_get_devdata(ctlr);
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rc = fsi_spi_check_mux(ctx->fsi, ctx->dev);
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if (rc)
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return rc;
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list_for_each_entry(transfer, &mesg->transfers, transfer_list) {
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struct fsi_spi_sequence seq;
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struct spi_transfer *next = NULL;
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/* Sequencer must do shift out (tx) first. */
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if (!transfer->tx_buf ||
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transfer->len > SPI_FSI_MAX_TRANSFER_SIZE) {
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transfer->len > (ctx->max_xfr_size + 8)) {
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rc = -EINVAL;
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goto error;
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}
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@ -431,7 +509,7 @@ static int fsi_spi_transfer_one_message(struct spi_controller *ctlr,
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/* Sequencer can only do shift in (rx) after tx. */
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if (next->rx_buf) {
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if (next->len > SPI_FSI_MAX_TRANSFER_SIZE) {
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if (next->len > ctx->max_xfr_size) {
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rc = -EINVAL;
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goto error;
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}
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@ -476,30 +554,21 @@ error:
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static size_t fsi_spi_max_transfer_size(struct spi_device *spi)
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{
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return SPI_FSI_MAX_TRANSFER_SIZE;
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struct fsi_spi *ctx = spi_controller_get_devdata(spi->controller);
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return ctx->max_xfr_size;
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}
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static int fsi_spi_probe(struct device *dev)
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{
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int rc;
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u32 root_ctrl_8;
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struct device_node *np;
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int num_controllers_registered = 0;
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struct fsi_device *fsi = to_fsi_dev(dev);
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/*
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* Check the SPI mux before attempting to probe. If the mux isn't set
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* then the SPI controllers can't access their slave devices.
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*/
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rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8,
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sizeof(root_ctrl_8));
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rc = fsi_spi_check_mux(fsi, dev);
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if (rc)
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return rc;
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if (!root_ctrl_8) {
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dev_dbg(dev, "SPI mux not set, aborting probe.\n");
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return -ENODEV;
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}
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for_each_available_child_of_node(dev->of_node, np) {
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u32 base;
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@ -524,6 +593,14 @@ static int fsi_spi_probe(struct device *dev)
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ctx->fsi = fsi;
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ctx->base = base + SPI_FSI_BASE;
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if (of_device_is_compatible(np, "ibm,fsi2spi-restricted")) {
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ctx->restricted = true;
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ctx->max_xfr_size = SPI_FSI_MAX_XFR_SIZE_RESTRICTED;
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} else {
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ctx->restricted = false;
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ctx->max_xfr_size = SPI_FSI_MAX_XFR_SIZE;
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}
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rc = devm_spi_register_controller(dev, ctlr);
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if (rc)
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spi_controller_put(ctlr);
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