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ARM: OMAP4+: Make secondary_startup function name more consistent

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Current code has rather inconsistent function names for 'secondary_startup'
routines. Update it to make it more consistent.

Suggested by Kevin Hilman as part of OMAP5 PM patch review.

Cc: Kevin Hilman <khilman@deeprootsystems.com>

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
Santosh Shilimkar 2013-04-05 18:29:02 +05:30 committed by Kevin Hilman
parent 9f192cf7da
commit baf4b7d343
4 changed files with 12 additions and 12 deletions
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4
arch/arm/mach-omap2/common.h
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@ -230,8 +230,8 @@ extern void omap_do_wfi(void);
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
/* Needed for secondary core boot */ /* Needed for secondary core boot */
extern void omap_secondary_startup(void); extern void omap4_secondary_startup(void);
extern void omap_secondary_startup_4460(void); extern void omap4460_secondary_startup(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
extern void omap_auxcoreboot_addr(u32 cpu_addr); extern void omap_auxcoreboot_addr(u32 cpu_addr);
extern u32 omap_read_auxcoreboot0(void); extern u32 omap_read_auxcoreboot0(void);

8
arch/arm/mach-omap2/omap-headsmp.S
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@ -49,7 +49,7 @@ END(omap5_secondary_startup)
* The primary core will update this flag using a hardware * The primary core will update this flag using a hardware
* register AuxCoreBoot0. * register AuxCoreBoot0.
*/ */
ENTRY(omap_secondary_startup) ENTRY(omap4_secondary_startup)
hold: ldr r12,=0x103 hold: ldr r12,=0x103
dsb dsb
smc #0 @ read from AuxCoreBoot0 smc #0 @ read from AuxCoreBoot0
@ -64,9 +64,9 @@ hold: ldr r12,=0x103
* should now contain the SVC stack for this core * should now contain the SVC stack for this core
*/ */
b secondary_startup b secondary_startup
ENDPROC(omap_secondary_startup) ENDPROC(omap4_secondary_startup)
ENTRY(omap_secondary_startup_4460) ENTRY(omap4460_secondary_startup)
hold_2: ldr r12,=0x103 hold_2: ldr r12,=0x103
dsb dsb
smc #0 @ read from AuxCoreBoot0 smc #0 @ read from AuxCoreBoot0
@ -101,4 +101,4 @@ hold_2: ldr r12,=0x103
* should now contain the SVC stack for this core * should now contain the SVC stack for this core
*/ */
b secondary_startup b secondary_startup
ENDPROC(omap_secondary_startup_4460) ENDPROC(omap4460_secondary_startup)

6
arch/arm/mach-omap2/omap-mpuss-lowpower.c
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@ -324,7 +324,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
/* /*
* CPU never retuns back if targeted power state is OFF mode. * CPU never retuns back if targeted power state is OFF mode.
* CPU ONLINE follows normal CPU ONLINE ptah via * CPU ONLINE follows normal CPU ONLINE ptah via
* omap_secondary_startup(). * omap4_secondary_startup().
*/ */
omap_pm_ops.finish_suspend(cpu_state); omap_pm_ops.finish_suspend(cpu_state);
@ -370,9 +370,9 @@ int __init omap4_mpuss_init(void)
pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
if (cpu_is_omap446x()) if (cpu_is_omap446x())
pm_info->secondary_startup = omap_secondary_startup_4460; pm_info->secondary_startup = omap4460_secondary_startup;
else else
pm_info->secondary_startup = omap_secondary_startup; pm_info->secondary_startup = omap4_secondary_startup;
pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
if (!pm_info->pwrdm) { if (!pm_info->pwrdm) {

6
arch/arm/mach-omap2/omap-smp.c
View File

@ -93,7 +93,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
/* /*
* Update the AuxCoreBoot0 with boot state for secondary core. * Update the AuxCoreBoot0 with boot state for secondary core.
* omap_secondary_startup() routine will hold the secondary core till * omap4_secondary_startup() routine will hold the secondary core till
* the AuxCoreBoot1 register is updated with cpu state * the AuxCoreBoot1 register is updated with cpu state
* A barrier is added to ensure that write buffer is drained * A barrier is added to ensure that write buffer is drained
*/ */
@ -199,7 +199,7 @@ static void __init omap4_smp_init_cpus(void)
static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
{ {
void *startup_addr = omap_secondary_startup; void *startup_addr = omap4_secondary_startup;
void __iomem *base = omap_get_wakeupgen_base(); void __iomem *base = omap_get_wakeupgen_base();
/* /*
@ -210,7 +210,7 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
scu_enable(scu_base); scu_enable(scu_base);
if (cpu_is_omap446x()) { if (cpu_is_omap446x()) {
startup_addr = omap_secondary_startup_4460; startup_addr = omap4460_secondary_startup;
pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
} }