forked from Minki/linux
mbxfb: Improvements and new features
This contains the following changes: * Overlay surface alpha is configured separately from the overlay. This prevents display glitches (configure and fill the overlay first, set alpha to a visible value next) * Added an ioctl for configuring transparency of the Overlay and graphics planes. Blend mode, colorkey mode and global alpha mode are supported. * Added an ioctl for setting the plane order. The overlay plance can be placed over or under the graphics plane. * Added an ioctl for setting and reading chip registers, with mask. * Updated copyright for 2007 [adaplas] * Coding style changes Signed-off-by: Raphael Assenat <raph@8d.com> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Raphael Assenat
Linus Torvalds
parent
eb78f9b3fa
commit
ba282daa91
@ -1,7 +1,7 @@
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/*
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* linux/drivers/video/mbx/mbxfb.c
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*
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* Copyright (C) 2006 8D Technologies inc
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* Copyright (C) 2006-2007 8D Technologies inc
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* Raphael Assenat <raph@8d.com>
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* - Added video overlay support
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* - Various improvements
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@ -334,8 +334,8 @@ static int mbxfb_blank(int blank, struct fb_info *info)
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static int mbxfb_setupOverlay(struct mbxfb_overlaySetup *set)
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{
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u32 vsctrl, vbbase, vscadr, vsadr;
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u32 sssize, spoctrl, svctrl, shctrl;
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u32 vsctrl, vscadr, vsadr;
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u32 sssize, spoctrl, shctrl;
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u32 vubase, vvbase;
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u32 vovrclk;
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@ -349,13 +349,11 @@ static int mbxfb_setupOverlay(struct mbxfb_overlaySetup *set)
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vscadr = readl(VSCADR);
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vubase = readl(VUBASE);
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vvbase = readl(VVBASE);
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shctrl = readl(SHCTRL);
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spoctrl = readl(SPOCTRL);
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sssize = readl(SSSIZE);
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vbbase = Vbbase_Glalpha(set->alpha);
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vsctrl &= ~( FMsk(VSCTRL_VSWIDTH) |
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FMsk(VSCTRL_VSHEIGHT) |
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FMsk(VSCTRL_VPIXFMT) |
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@ -364,18 +362,21 @@ static int mbxfb_setupOverlay(struct mbxfb_overlaySetup *set)
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vsctrl |= Vsctrl_Width(set->width) | Vsctrl_Height(set->height) |
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VSCTRL_CSC_EN;
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vscadr &= ~(VSCADR_STR_EN | VSCADR_COLKEY_EN | VSCADR_COLKEYSRC |
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FMsk(VSCADR_BLEND_M) | FMsk(VSCADR_BLEND_POS) |
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FMsk(VSCADR_VBASE_ADR) );
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vscadr &= ~(VSCADR_STR_EN | FMsk(VSCADR_VBASE_ADR) );
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vubase &= ~(VUBASE_UVHALFSTR | FMsk(VUBASE_UBASE_ADR));
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vvbase &= ~(FMsk(VVBASE_VBASE_ADR));
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switch (set->fmt)
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{
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switch (set->fmt) {
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case MBXFB_FMT_YUV16:
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vsctrl |= VSCTRL_VPIXFMT_YUV12;
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set->Y_stride = ((set->width) + 0xf ) & ~0xf;
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break;
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case MBXFB_FMT_YUV12:
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vsctrl |= VSCTRL_VPIXFMT_YUV12;
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set->Y_stride = ((set->width) + 0xf ) & ~0xf;
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vubase |= VUBASE_UVHALFSTR;
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break;
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case MBXFB_FMT_UY0VY1:
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@ -417,8 +418,7 @@ static int mbxfb_setupOverlay(struct mbxfb_overlaySetup *set)
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(0x60000 + set->mem_offset + set->V_offset)>>3);
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vscadr |= VSCADR_BLEND_VID | VSCADR_BLEND_GLOB |
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Vscadr_Vbase_Adr((0x60000 + set->mem_offset)>>4);
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vscadr |= Vscadr_Vbase_Adr((0x60000 + set->mem_offset)>>4);
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if (set->enable)
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vscadr |= VSCADR_STR_EN;
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@ -433,9 +433,8 @@ static int mbxfb_setupOverlay(struct mbxfb_overlaySetup *set)
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spoctrl &= ~(SPOCTRL_H_SC_BP | SPOCTRL_V_SC_BP |
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SPOCTRL_HV_SC_OR | SPOCTRL_VS_UR_C |
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FMsk(SPOCTRL_VORDER) | FMsk(SPOCTRL_VPITCH));
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spoctrl = Spoctrl_Vpitch((set->height<<11)/set->scaled_height)
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| SPOCTRL_VORDER_2TAP;
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FMsk(SPOCTRL_VPITCH));
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spoctrl |= Spoctrl_Vpitch((set->height<<11)/set->scaled_height);
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/* Bypass horiz/vert scaler when same size */
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if (set->scaled_width == set->width)
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@ -443,14 +442,11 @@ static int mbxfb_setupOverlay(struct mbxfb_overlaySetup *set)
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if (set->scaled_height == set->height)
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spoctrl |= SPOCTRL_V_SC_BP;
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svctrl = Svctrl_Initial1(1<<10) | Svctrl_Initial2(1<<10);
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shctrl = Shctrl_Hinitial(4<<11)
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| Shctrl_Hpitch((set->width<<11)/set->scaled_width);
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shctrl &= ~(FMsk(SHCTRL_HPITCH) | SHCTRL_HDECIM);
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shctrl |= Shctrl_Hpitch((set->width<<11)/set->scaled_width);
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/* Video plane registers */
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write_reg(vsctrl, VSCTRL);
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write_reg(vbbase, VBBASE);
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write_reg(vscadr, VSCADR);
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write_reg(vubase, VUBASE);
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write_reg(vvbase, VVBASE);
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@ -459,28 +455,8 @@ static int mbxfb_setupOverlay(struct mbxfb_overlaySetup *set)
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/* Video scaler registers */
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write_reg(sssize, SSSIZE);
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write_reg(spoctrl, SPOCTRL);
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write_reg(svctrl, SVCTRL);
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write_reg(shctrl, SHCTRL);
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/* RAPH: Using those coefficients, the scaled
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* image is quite blurry. I dont know how
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* to improve them ; The chip documentation
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* was not helpful.. */
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write_reg(0x21212121, VSCOEFF0);
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write_reg(0x21212121, VSCOEFF1);
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write_reg(0x21212121, VSCOEFF2);
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write_reg(0x21212121, VSCOEFF3);
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write_reg(0x21212121, VSCOEFF4);
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write_reg(0x00000000, HSCOEFF0);
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write_reg(0x00000000, HSCOEFF1);
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write_reg(0x00000000, HSCOEFF2);
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write_reg(0x03020201, HSCOEFF3);
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write_reg(0x09070604, HSCOEFF4);
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write_reg(0x0f0e0c0a, HSCOEFF5);
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write_reg(0x15141211, HSCOEFF6);
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write_reg(0x19181716, HSCOEFF7);
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write_reg(0x00000019, HSCOEFF8);
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/* Clock */
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if (set->enable)
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vovrclk |= 1;
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@ -492,14 +468,150 @@ static int mbxfb_setupOverlay(struct mbxfb_overlaySetup *set)
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return 0;
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}
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static int mbxfb_ioctl_planeorder(struct mbxfb_planeorder *porder)
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{
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unsigned long gscadr, vscadr;
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if (porder->bottom == porder->top)
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return -EINVAL;
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gscadr = readl(GSCADR);
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vscadr = readl(VSCADR);
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gscadr &= ~(FMsk(GSCADR_BLEND_POS));
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vscadr &= ~(FMsk(VSCADR_BLEND_POS));
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switch (porder->bottom) {
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case MBXFB_PLANE_GRAPHICS:
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gscadr |= GSCADR_BLEND_GFX;
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break;
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case MBXFB_PLANE_VIDEO:
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vscadr |= VSCADR_BLEND_GFX;
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break;
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default:
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return -EINVAL;
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}
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switch (porder->top) {
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case MBXFB_PLANE_GRAPHICS:
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gscadr |= GSCADR_BLEND_VID;
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break;
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case MBXFB_PLANE_VIDEO:
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vscadr |= GSCADR_BLEND_VID;
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break;
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default:
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return -EINVAL;
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}
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write_reg_dly(vscadr, VSCADR);
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write_reg_dly(gscadr, GSCADR);
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return 0;
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}
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static int mbxfb_ioctl_alphactl(struct mbxfb_alphaCtl *alpha)
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{
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unsigned long vscadr, vbbase, vcmsk;
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unsigned long gscadr, gbbase, gdrctrl;
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vbbase = Vbbase_Glalpha(alpha->overlay_global_alpha) |
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Vbbase_Colkey(alpha->overlay_colorkey);
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gbbase = Gbbase_Glalpha(alpha->graphics_global_alpha) |
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Gbbase_Colkey(alpha->graphics_colorkey);
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vcmsk = readl(VCMSK);
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vcmsk &= ~(FMsk(VCMSK_COLKEY_M));
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vcmsk |= Vcmsk_colkey_m(alpha->overlay_colorkey_mask);
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gdrctrl = readl(GDRCTRL);
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gdrctrl &= ~(FMsk(GDRCTRL_COLKEYM));
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gdrctrl |= Gdrctrl_Colkeym(alpha->graphics_colorkey_mask);
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vscadr = readl(VSCADR);
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vscadr &= ~(FMsk(VSCADR_BLEND_M) | VSCADR_COLKEYSRC | VSCADR_COLKEY_EN);
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gscadr = readl(GSCADR);
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gscadr &= ~(FMsk(GSCADR_BLEND_M) | GSCADR_COLKEY_EN | GSCADR_COLKEYSRC);
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switch (alpha->overlay_colorkey_mode) {
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case MBXFB_COLORKEY_DISABLED:
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break;
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case MBXFB_COLORKEY_PREVIOUS:
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vscadr |= VSCADR_COLKEY_EN;
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break;
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case MBXFB_COLORKEY_CURRENT:
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vscadr |= VSCADR_COLKEY_EN | VSCADR_COLKEYSRC;
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break;
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default:
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return -EINVAL;
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}
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switch (alpha->overlay_blend_mode) {
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case MBXFB_ALPHABLEND_NONE:
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vscadr |= VSCADR_BLEND_NONE;
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break;
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case MBXFB_ALPHABLEND_GLOBAL:
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vscadr |= VSCADR_BLEND_GLOB;
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break;
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case MBXFB_ALPHABLEND_PIXEL:
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vscadr |= VSCADR_BLEND_PIX;
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break;
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default:
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return -EINVAL;
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}
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switch (alpha->graphics_colorkey_mode) {
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case MBXFB_COLORKEY_DISABLED:
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break;
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case MBXFB_COLORKEY_PREVIOUS:
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gscadr |= GSCADR_COLKEY_EN;
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break;
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case MBXFB_COLORKEY_CURRENT:
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gscadr |= GSCADR_COLKEY_EN | GSCADR_COLKEYSRC;
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break;
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default:
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return -EINVAL;
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}
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switch (alpha->graphics_blend_mode) {
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case MBXFB_ALPHABLEND_NONE:
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gscadr |= GSCADR_BLEND_NONE;
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break;
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case MBXFB_ALPHABLEND_GLOBAL:
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gscadr |= GSCADR_BLEND_GLOB;
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break;
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case MBXFB_ALPHABLEND_PIXEL:
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gscadr |= GSCADR_BLEND_PIX;
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break;
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default:
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return -EINVAL;
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}
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write_reg_dly(vbbase, VBBASE);
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write_reg_dly(gbbase, GBBASE);
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write_reg_dly(vcmsk, VCMSK);
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write_reg_dly(gdrctrl, GDRCTRL);
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write_reg_dly(gscadr, GSCADR);
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write_reg_dly(vscadr, VSCADR);
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return 0;
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}
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static int mbxfb_ioctl(struct fb_info *info, unsigned int cmd,
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unsigned long arg)
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{
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struct mbxfb_overlaySetup setup;
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struct mbxfb_planeorder porder;
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struct mbxfb_alphaCtl alpha;
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struct mbxfb_reg reg;
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int res;
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__u32 tmp;
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if (cmd == MBXFB_IOCX_OVERLAY)
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switch (cmd)
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{
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case MBXFB_IOCX_OVERLAY:
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if (copy_from_user(&setup, (void __user*)arg,
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sizeof(struct mbxfb_overlaySetup)))
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return -EFAULT;
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@ -513,6 +625,49 @@ static int mbxfb_ioctl(struct fb_info *info, unsigned int cmd,
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return -EFAULT;
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return 0;
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case MBXFB_IOCS_PLANEORDER:
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if (copy_from_user(&porder, (void __user*)arg,
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sizeof(struct mbxfb_planeorder)))
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return -EFAULT;
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return mbxfb_ioctl_planeorder(&porder);
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case MBXFB_IOCS_ALPHA:
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if (copy_from_user(&alpha, (void __user*)arg,
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sizeof(struct mbxfb_alphaCtl)))
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return -EFAULT;
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return mbxfb_ioctl_alphactl(&alpha);
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case MBXFB_IOCS_REG:
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if (copy_from_user(®, (void __user*)arg,
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sizeof(struct mbxfb_reg)))
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return -EFAULT;
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if (reg.addr >= 0x10000) /* regs are from 0x3fe0000 to 0x3feffff */
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return -EINVAL;
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tmp = readl(virt_base_2700 + reg.addr);
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tmp &= ~reg.mask;
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tmp |= reg.val & reg.mask;
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writel(tmp, virt_base_2700 + reg.addr);
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return 0;
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case MBXFB_IOCX_REG:
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if (copy_from_user(®, (void __user*)arg,
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sizeof(struct mbxfb_reg)))
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return -EFAULT;
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if (reg.addr >= 0x10000) /* regs are from 0x3fe0000 to 0x3feffff */
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return -EINVAL;
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reg.val = readl(virt_base_2700 + reg.addr);
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if (copy_to_user((void __user*)arg, ®,
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sizeof(struct mbxfb_reg)))
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return -EFAULT;
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return 0;
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}
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return -EINVAL;
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}
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@ -558,7 +713,6 @@ static void __devinit setup_memc(struct fb_info *fbi)
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LMTYPE);
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/* enable memory controller */
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write_reg_dly(LMPWR_MC_PWR_ACT, LMPWR);
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/* perform dummy reads */
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for ( i = 0; i < 16; i++ ) {
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tmp = readl(fbi->screen_base);
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@ -588,8 +742,8 @@ static void enable_clocks(struct fb_info *fbi)
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write_reg_dly(0x00000000, VOVRCLK);
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write_reg_dly(PIXCLK_EN, PIXCLK);
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write_reg_dly(MEMCLK_EN, MEMCLK);
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write_reg_dly(0x00000006, M24CLK);
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write_reg_dly(0x00000006, MBXCLK);
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write_reg_dly(0x00000001, M24CLK);
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write_reg_dly(0x00000001, MBXCLK);
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write_reg_dly(SDCLK_EN, SDCLK);
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write_reg_dly(0x00000001, PIXCLKDIV);
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}
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@ -597,6 +751,7 @@ static void enable_clocks(struct fb_info *fbi)
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static void __devinit setup_graphics(struct fb_info *fbi)
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{
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unsigned long gsctrl;
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unsigned long vscadr;
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gsctrl = GSCTRL_GAMMA_EN | Gsctrl_Width(fbi->var.xres) |
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Gsctrl_Height(fbi->var.yres);
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@ -620,6 +775,11 @@ static void __devinit setup_graphics(struct fb_info *fbi)
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write_reg_dly(0x00ffffff, GDRCTRL);
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write_reg_dly((GSCADR_STR_EN | Gscadr_Gbase_Adr(0x6000)), GSCADR);
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write_reg_dly(0x00000000, GPLUT);
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vscadr = readl(VSCADR);
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vscadr &= ~(FMsk(VSCADR_BLEND_POS) | FMsk(VSCADR_BLEND_M));
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vscadr |= VSCADR_BLEND_VID | VSCADR_BLEND_NONE;
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write_reg_dly(vscadr, VSCADR);
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}
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static void __devinit setup_display(struct fb_info *fbi)
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@ -638,13 +798,47 @@ static void __devinit setup_display(struct fb_info *fbi)
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static void __devinit enable_controller(struct fb_info *fbi)
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{
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u32 svctrl, shctrl;
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write_reg_dly(SYSRST_RST, SYSRST);
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/* setup a timeout, raise drive strength */
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write_reg_dly(0xffffff0c, SYSCFG);
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enable_clocks(fbi);
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setup_memc(fbi);
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setup_graphics(fbi);
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setup_display(fbi);
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shctrl = readl(SHCTRL);
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shctrl &= ~(FMsk(SHCTRL_HINITIAL));
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shctrl |= Shctrl_Hinitial(4<<11);
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writel(shctrl, SHCTRL);
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svctrl = Svctrl_Initial1(1<<10) | Svctrl_Initial2(1<<10);
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writel(svctrl, SVCTRL);
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writel(SPOCTRL_H_SC_BP | SPOCTRL_V_SC_BP | SPOCTRL_VORDER_4TAP
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, SPOCTRL);
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/* Those coefficients are good for scaling up. For scaling
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* down, the application has to calculate them. */
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write_reg(0xff000100, VSCOEFF0);
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write_reg(0xfdfcfdfe, VSCOEFF1);
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write_reg(0x170d0500, VSCOEFF2);
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write_reg(0x3d372d22, VSCOEFF3);
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write_reg(0x00000040, VSCOEFF4);
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write_reg(0xff010100, HSCOEFF0);
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write_reg(0x00000000, HSCOEFF1);
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write_reg(0x02010000, HSCOEFF2);
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write_reg(0x01020302, HSCOEFF3);
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write_reg(0xf9fbfe00, HSCOEFF4);
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write_reg(0xfbf7f6f7, HSCOEFF5);
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write_reg(0x1c110700, HSCOEFF6);
|
||||
write_reg(0x3e393127, HSCOEFF7);
|
||||
write_reg(0x00000040, HSCOEFF8);
|
||||
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
@ -215,7 +215,7 @@
|
||||
/* GSCADR graphics stream control address register fields */
|
||||
#define GSCADR_STR_EN (1 << 31)
|
||||
#define GSCADR_COLKEY_EN (1 << 30)
|
||||
#define GSCADR_COLKEYSCR (1 << 29)
|
||||
#define GSCADR_COLKEYSRC (1 << 29)
|
||||
#define GSCADR_BLEND_M Fld(2,27)
|
||||
#define GSCADR_BLEND_NONE ((0x0) << FShft(GSCADR_BLEND_M))
|
||||
#define GSCADR_BLEND_INV ((0x1) << FShft(GSCADR_BLEND_M))
|
||||
@ -303,6 +303,67 @@
|
||||
#define VSADR_YSTART Fld(11,0)
|
||||
#define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART))
|
||||
|
||||
/* VSCTRL - Video Surface Control Register */
|
||||
#define VSCTRL_VPIXFMT Fld(4,27)
|
||||
#define VSCTRL_VPIXFMT_YUV12 ((0x9) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_VPIXFMT_UY0VY1 ((0xc) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_VPIXFMT_VY0UY1 ((0xd) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_VPIXFMT_Y0UY1V ((0xe) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_VPIXFMT_Y0VY1U ((0xf) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_GAMMA_EN (1 << 26)
|
||||
#define VSCTRL_CSC_EN (1 << 25)
|
||||
#define VSCTRL_COSITED (1 << 22)
|
||||
#define VSCTRL_VSWIDTH Fld(11,11)
|
||||
#define Vsctrl_Width(Pixels) /* Video Width [1-2048] */ \
|
||||
(((Pixels) - 1) << FShft(VSCTRL_VSWIDTH))
|
||||
#define VSCTRL_VSHEIGHT Fld(11,0)
|
||||
#define Vsctrl_Height(Pixels) /* Video Height [1-2048] */ \
|
||||
(((Pixels) - 1) << FShft(VSCTRL_VSHEIGHT))
|
||||
|
||||
/* VBBASE - Video Blending Base Register */
|
||||
#define VBBASE_GLALPHA Fld(8,24)
|
||||
#define Vbbase_Glalpha(x) ((x) << FShft(VBBASE_GLALPHA))
|
||||
|
||||
#define VBBASE_COLKEY Fld(24,0)
|
||||
#define Vbbase_Colkey(x) ((x) << FShft(VBBASE_COLKEY))
|
||||
|
||||
/* VCMSK - Video Color Key Mask Register */
|
||||
#define VCMSK_COLKEY_M Fld(24,0)
|
||||
#define Vcmsk_colkey_m(x) ((x) << FShft(VCMSK_COLKEY_M))
|
||||
|
||||
/* VSCADR - Video Stream Control Rddress Register */
|
||||
#define VSCADR_STR_EN (1 << 31)
|
||||
#define VSCADR_COLKEY_EN (1 << 30)
|
||||
#define VSCADR_COLKEYSRC (1 << 29)
|
||||
#define VSCADR_BLEND_M Fld(2,27)
|
||||
#define VSCADR_BLEND_NONE ((0x0) << FShft(VSCADR_BLEND_M))
|
||||
#define VSCADR_BLEND_INV ((0x1) << FShft(VSCADR_BLEND_M))
|
||||
#define VSCADR_BLEND_GLOB ((0x2) << FShft(VSCADR_BLEND_M))
|
||||
#define VSCADR_BLEND_PIX ((0x3) << FShft(VSCADR_BLEND_M))
|
||||
#define VSCADR_BLEND_POS Fld(2,24)
|
||||
#define VSCADR_BLEND_GFX ((0x0) << FShft(VSCADR_BLEND_POS))
|
||||
#define VSCADR_BLEND_VID ((0x1) << FShft(VSCADR_BLEND_POS))
|
||||
#define VSCADR_BLEND_CUR ((0x2) << FShft(VSCADR_BLEND_POS))
|
||||
#define VSCADR_VBASE_ADR Fld(23,0)
|
||||
#define Vscadr_Vbase_Adr(x) ((x) << FShft(VSCADR_VBASE_ADR))
|
||||
|
||||
/* VUBASE - Video U Base Register */
|
||||
#define VUBASE_UVHALFSTR (1 << 31)
|
||||
#define VUBASE_UBASE_ADR Fld(24,0)
|
||||
#define Vubase_Ubase_Adr(x) ((x) << FShft(VUBASE_UBASE_ADR))
|
||||
|
||||
/* VVBASE - Video V Base Register */
|
||||
#define VVBASE_VBASE_ADR Fld(24,0)
|
||||
#define Vvbase_Vbase_Adr(x) ((x) << FShft(VVBASE_VBASE_ADR))
|
||||
|
||||
/* VSADR - Video Stride Address Register */
|
||||
#define VSADR_SRCSTRIDE Fld(10,22)
|
||||
#define Vsadr_Srcstride(x) ((x) << FShft(VSADR_SRCSTRIDE))
|
||||
#define VSADR_XSTART Fld(11,11)
|
||||
#define Vsadr_Xstart(x) ((x) << FShft(VSADR_XSTART))
|
||||
#define VSADR_YSTART Fld(11,0)
|
||||
#define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART))
|
||||
|
||||
/* HCCTRL - Hardware Cursor Register fields */
|
||||
#define HCCTRL_CUR_EN (1 << 31)
|
||||
#define HCCTRL_COLKEY_EN (1 << 29)
|
||||
@ -479,6 +540,30 @@
|
||||
#define DINTRE_HBLNK1_EN (1 << 1)
|
||||
#define DINTRE_HBLNK0_EN (1 << 0)
|
||||
|
||||
/* DINTRS - Display Interrupt Status Register */
|
||||
#define DINTRS_CUR_OR_S (1 << 18)
|
||||
#define DINTRS_STR2_OR_S (1 << 17)
|
||||
#define DINTRS_STR1_OR_S (1 << 16)
|
||||
#define DINTRS_CUR_UR_S (1 << 6)
|
||||
#define DINTRS_STR2_UR_S (1 << 5)
|
||||
#define DINTRS_STR1_UR_S (1 << 4)
|
||||
#define DINTRS_VEVENT1_S (1 << 3)
|
||||
#define DINTRS_VEVENT0_S (1 << 2)
|
||||
#define DINTRS_HBLNK1_S (1 << 1)
|
||||
#define DINTRS_HBLNK0_S (1 << 0)
|
||||
|
||||
/* DINTRE - Display Interrupt Enable Register */
|
||||
#define DINTRE_CUR_OR_EN (1 << 18)
|
||||
#define DINTRE_STR2_OR_EN (1 << 17)
|
||||
#define DINTRE_STR1_OR_EN (1 << 16)
|
||||
#define DINTRE_CUR_UR_EN (1 << 6)
|
||||
#define DINTRE_STR2_UR_EN (1 << 5)
|
||||
#define DINTRE_STR1_UR_EN (1 << 4)
|
||||
#define DINTRE_VEVENT1_EN (1 << 3)
|
||||
#define DINTRE_VEVENT0_EN (1 << 2)
|
||||
#define DINTRE_HBLNK1_EN (1 << 1)
|
||||
#define DINTRE_HBLNK0_EN (1 << 0)
|
||||
|
||||
|
||||
/* DLSTS - display load status register */
|
||||
#define DLSTS_RLD_ADONE (1 << 23)
|
||||
|
||||
@ -30,7 +30,7 @@
|
||||
#define VOVRCLK __REG_2700G(0x00000044)
|
||||
#define PIXCLK __REG_2700G(0x00000048)
|
||||
#define MEMCLK __REG_2700G(0x0000004c)
|
||||
#define M24CLK __REG_2700G(0x00000054)
|
||||
#define M24CLK __REG_2700G(0x00000050)
|
||||
#define MBXCLK __REG_2700G(0x00000054)
|
||||
#define SDCLK __REG_2700G(0x00000058)
|
||||
#define PIXCLKDIV __REG_2700G(0x0000005c)
|
||||
|
||||
@ -29,18 +29,18 @@ struct mbxfb_platform_data {
|
||||
};
|
||||
|
||||
/* planar */
|
||||
#define MBXFB_FMT_YUV12 0
|
||||
#define MBXFB_FMT_YUV16 0
|
||||
#define MBXFB_FMT_YUV12 1
|
||||
|
||||
/* packed */
|
||||
#define MBXFB_FMT_UY0VY1 1
|
||||
#define MBXFB_FMT_VY0UY1 2
|
||||
#define MBXFB_FMT_Y0UY1V 3
|
||||
#define MBXFB_FMT_Y0VY1U 4
|
||||
#define MBXFB_FMT_UY0VY1 2
|
||||
#define MBXFB_FMT_VY0UY1 3
|
||||
#define MBXFB_FMT_Y0UY1V 4
|
||||
#define MBXFB_FMT_Y0VY1U 5
|
||||
struct mbxfb_overlaySetup {
|
||||
__u32 enable;
|
||||
__u32 x, y;
|
||||
__u32 width, height;
|
||||
__u32 alpha;
|
||||
__u32 fmt;
|
||||
__u32 mem_offset;
|
||||
__u32 scaled_width;
|
||||
@ -54,6 +54,45 @@ struct mbxfb_overlaySetup {
|
||||
__u16 UV_stride;
|
||||
};
|
||||
|
||||
#define MBXFB_ALPHABLEND_NONE 0
|
||||
#define MBXFB_ALPHABLEND_GLOBAL 1
|
||||
#define MBXFB_ALPHABLEND_PIXEL 2
|
||||
|
||||
#define MBXFB_COLORKEY_DISABLED 0
|
||||
#define MBXFB_COLORKEY_PREVIOUS 1
|
||||
#define MBXFB_COLORKEY_CURRENT 2
|
||||
struct mbxfb_alphaCtl {
|
||||
__u8 overlay_blend_mode;
|
||||
__u8 overlay_colorkey_mode;
|
||||
__u8 overlay_global_alpha;
|
||||
__u32 overlay_colorkey;
|
||||
__u32 overlay_colorkey_mask;
|
||||
|
||||
__u8 graphics_blend_mode;
|
||||
__u8 graphics_colorkey_mode;
|
||||
__u8 graphics_global_alpha;
|
||||
__u32 graphics_colorkey;
|
||||
__u32 graphics_colorkey_mask;
|
||||
};
|
||||
|
||||
#define MBXFB_PLANE_GRAPHICS 0
|
||||
#define MBXFB_PLANE_VIDEO 1
|
||||
struct mbxfb_planeorder {
|
||||
__u8 bottom;
|
||||
__u8 top;
|
||||
};
|
||||
|
||||
struct mbxfb_reg {
|
||||
__u32 addr; /* offset from 0x03fe 0000 */
|
||||
__u32 val; /* value */
|
||||
__u32 mask; /* which bits to touch (for write) */
|
||||
};
|
||||
|
||||
#define MBXFB_IOCX_OVERLAY _IOWR(0xF4, 0x00,struct mbxfb_overlaySetup)
|
||||
#define MBXFB_IOCG_ALPHA _IOR(0xF4, 0x01,struct mbxfb_alphaCtl)
|
||||
#define MBXFB_IOCS_ALPHA _IOW(0xF4, 0x02,struct mbxfb_alphaCtl)
|
||||
#define MBXFB_IOCS_PLANEORDER _IOR(0xF4, 0x03,struct mbxfb_planeorder)
|
||||
#define MBXFB_IOCS_REG _IOW(0xF4, 0x04,struct mbxfb_reg)
|
||||
#define MBXFB_IOCX_REG _IOWR(0xF4, 0x05,struct mbxfb_reg)
|
||||
|
||||
#endif /* __MBX_FB_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user