forked from Minki/linux
perf/x86/uncore: add SNB/IVB/HSW client uncore memory controller support
This patch adds a new uncore PMU for Intel SNB/IVB/HSW client CPUs. It adds the Integrated Memory Controller (IMC) PMU. This new PMU provides a set of events to measure memory bandwidth utilization. The IMC on those processor is PCI-space based. This patch exposes a new uncore PMU on those processor: uncore_imc Two new events are defined: - name: data_reads - code: 0x1 - unit: 64 bytes - number of full cacheline read requests to the IMC - name: data_writes - code: 0x2 - unit: 64 bytes - number of full cacheline write requests to the IMC Documentation available at: http://software.intel.com/en-us/articles/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel Cc: mingo@elte.hu Cc: acme@redhat.com Cc: ak@linux.intel.com Cc: zheng.z.yan@intel.com Cc: peterz@infradead.org Signed-off-by: Stephane Eranian <eranian@google.com> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1392132015-14521-7-git-send-email-eranian@google.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Stephane Eranian
Thomas Gleixner
parent
001e413f7e
commit
b9e1ab6d4c
@ -66,6 +66,11 @@ DEFINE_UNCORE_FORMAT_ATTR(mask_vnw, mask_vnw, "config2:3-4");
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DEFINE_UNCORE_FORMAT_ATTR(mask0, mask0, "config2:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(mask1, mask1, "config2:32-63");
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static void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
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static void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
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static void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
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static void uncore_pmu_event_read(struct perf_event *event);
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static struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
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{
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return container_of(event->pmu, struct intel_uncore_pmu, pmu);
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@ -1667,6 +1672,344 @@ static struct intel_uncore_type *snb_msr_uncores[] = {
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&snb_uncore_cbox,
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NULL,
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};
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enum {
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SNB_PCI_UNCORE_IMC,
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};
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static struct uncore_event_desc snb_uncore_imc_events[] = {
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INTEL_UNCORE_EVENT_DESC(data_reads, "event=0x01"),
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INTEL_UNCORE_EVENT_DESC(data_reads.scale, "64"),
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INTEL_UNCORE_EVENT_DESC(data_reads.unit, "bytes"),
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INTEL_UNCORE_EVENT_DESC(data_writes, "event=0x02"),
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INTEL_UNCORE_EVENT_DESC(data_writes.scale, "64"),
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INTEL_UNCORE_EVENT_DESC(data_writes.unit, "bytes"),
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{ /* end: all zeroes */ },
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};
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#define SNB_UNCORE_PCI_IMC_EVENT_MASK 0xff
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#define SNB_UNCORE_PCI_IMC_BAR_OFFSET 0x48
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/* page size multiple covering all config regs */
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#define SNB_UNCORE_PCI_IMC_MAP_SIZE 0x6000
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#define SNB_UNCORE_PCI_IMC_DATA_READS 0x1
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#define SNB_UNCORE_PCI_IMC_DATA_READS_BASE 0x5050
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#define SNB_UNCORE_PCI_IMC_DATA_WRITES 0x2
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#define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054
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#define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE
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static struct attribute *snb_uncore_imc_formats_attr[] = {
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&format_attr_event.attr,
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NULL,
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};
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static struct attribute_group snb_uncore_imc_format_group = {
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.name = "format",
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.attrs = snb_uncore_imc_formats_attr,
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};
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static void snb_uncore_imc_init_box(struct intel_uncore_box *box)
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{
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struct pci_dev *pdev = box->pci_dev;
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u32 addr_lo, addr_hi;
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resource_size_t addr;
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pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET, &addr_lo);
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addr = addr_lo;
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET+4, &addr_hi);
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addr = ((resource_size_t)addr_hi << 32) | addr_lo;
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#endif
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addr &= ~(PAGE_SIZE - 1);
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box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
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}
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static void snb_uncore_imc_enable_box(struct intel_uncore_box *box)
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{}
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static void snb_uncore_imc_disable_box(struct intel_uncore_box *box)
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{}
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static void snb_uncore_imc_enable_event(struct intel_uncore_box *box, struct perf_event *event)
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{}
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static void snb_uncore_imc_disable_event(struct intel_uncore_box *box, struct perf_event *event)
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{}
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static u64 snb_uncore_imc_read_counter(struct intel_uncore_box *box, struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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return (u64)*(unsigned int *)(box->io_addr + hwc->event_base);
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}
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/*
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* custom event_init() function because we define our own fixed, free
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* running counters, so we do not want to conflict with generic uncore
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* logic. Also simplifies processing
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*/
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static int snb_uncore_imc_event_init(struct perf_event *event)
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{
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struct intel_uncore_pmu *pmu;
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struct intel_uncore_box *box;
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struct hw_perf_event *hwc = &event->hw;
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u64 cfg = event->attr.config & SNB_UNCORE_PCI_IMC_EVENT_MASK;
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int idx, base;
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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pmu = uncore_event_to_pmu(event);
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/* no device found for this pmu */
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if (pmu->func_id < 0)
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return -ENOENT;
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/* Sampling not supported yet */
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if (hwc->sample_period)
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return -EINVAL;
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/* unsupported modes and filters */
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if (event->attr.exclude_user ||
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event->attr.exclude_kernel ||
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event->attr.exclude_hv ||
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event->attr.exclude_idle ||
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event->attr.exclude_host ||
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event->attr.exclude_guest ||
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event->attr.sample_period) /* no sampling */
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return -EINVAL;
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/*
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* Place all uncore events for a particular physical package
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* onto a single cpu
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*/
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if (event->cpu < 0)
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return -EINVAL;
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/* check only supported bits are set */
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if (event->attr.config & ~SNB_UNCORE_PCI_IMC_EVENT_MASK)
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return -EINVAL;
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box = uncore_pmu_to_box(pmu, event->cpu);
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if (!box || box->cpu < 0)
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return -EINVAL;
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event->cpu = box->cpu;
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event->hw.idx = -1;
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event->hw.last_tag = ~0ULL;
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event->hw.extra_reg.idx = EXTRA_REG_NONE;
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event->hw.branch_reg.idx = EXTRA_REG_NONE;
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/*
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* check event is known (whitelist, determines counter)
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*/
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switch (cfg) {
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case SNB_UNCORE_PCI_IMC_DATA_READS:
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base = SNB_UNCORE_PCI_IMC_DATA_READS_BASE;
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idx = UNCORE_PMC_IDX_FIXED;
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break;
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case SNB_UNCORE_PCI_IMC_DATA_WRITES:
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base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
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idx = UNCORE_PMC_IDX_FIXED + 1;
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break;
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default:
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return -EINVAL;
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}
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/* must be done before validate_group */
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event->hw.event_base = base;
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event->hw.config = cfg;
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event->hw.idx = idx;
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/* no group validation needed, we have free running counters */
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return 0;
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}
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static int snb_uncore_imc_hw_config(struct intel_uncore_box *box, struct perf_event *event)
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{
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return 0;
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}
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static void snb_uncore_imc_event_start(struct perf_event *event, int flags)
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{
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struct intel_uncore_box *box = uncore_event_to_box(event);
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u64 count;
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if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
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return;
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event->hw.state = 0;
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box->n_active++;
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list_add_tail(&event->active_entry, &box->active_list);
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count = snb_uncore_imc_read_counter(box, event);
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local64_set(&event->hw.prev_count, count);
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if (box->n_active == 1)
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uncore_pmu_start_hrtimer(box);
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}
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static void snb_uncore_imc_event_stop(struct perf_event *event, int flags)
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{
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struct intel_uncore_box *box = uncore_event_to_box(event);
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struct hw_perf_event *hwc = &event->hw;
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if (!(hwc->state & PERF_HES_STOPPED)) {
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box->n_active--;
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WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
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hwc->state |= PERF_HES_STOPPED;
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list_del(&event->active_entry);
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if (box->n_active == 0)
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uncore_pmu_cancel_hrtimer(box);
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}
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if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
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/*
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* Drain the remaining delta count out of a event
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* that we are disabling:
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*/
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uncore_perf_event_update(box, event);
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hwc->state |= PERF_HES_UPTODATE;
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}
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}
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static int snb_uncore_imc_event_add(struct perf_event *event, int flags)
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{
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struct intel_uncore_box *box = uncore_event_to_box(event);
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struct hw_perf_event *hwc = &event->hw;
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if (!box)
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return -ENODEV;
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hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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if (!(flags & PERF_EF_START))
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hwc->state |= PERF_HES_ARCH;
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snb_uncore_imc_event_start(event, 0);
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box->n_events++;
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return 0;
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}
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static void snb_uncore_imc_event_del(struct perf_event *event, int flags)
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{
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struct intel_uncore_box *box = uncore_event_to_box(event);
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int i;
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snb_uncore_imc_event_stop(event, PERF_EF_UPDATE);
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for (i = 0; i < box->n_events; i++) {
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if (event == box->event_list[i]) {
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--box->n_events;
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break;
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}
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}
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}
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static int snb_pci2phy_map_init(int devid)
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{
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struct pci_dev *dev = NULL;
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int bus;
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dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, dev);
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if (!dev)
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return -ENOTTY;
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bus = dev->bus->number;
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pcibus_to_physid[bus] = 0;
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pci_dev_put(dev);
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return 0;
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}
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static struct pmu snb_uncore_imc_pmu = {
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.task_ctx_nr = perf_invalid_context,
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.event_init = snb_uncore_imc_event_init,
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.add = snb_uncore_imc_event_add,
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.del = snb_uncore_imc_event_del,
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.start = snb_uncore_imc_event_start,
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.stop = snb_uncore_imc_event_stop,
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.read = uncore_pmu_event_read,
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};
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static struct intel_uncore_ops snb_uncore_imc_ops = {
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.init_box = snb_uncore_imc_init_box,
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.enable_box = snb_uncore_imc_enable_box,
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.disable_box = snb_uncore_imc_disable_box,
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.disable_event = snb_uncore_imc_disable_event,
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.enable_event = snb_uncore_imc_enable_event,
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.hw_config = snb_uncore_imc_hw_config,
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.read_counter = snb_uncore_imc_read_counter,
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};
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static struct intel_uncore_type snb_uncore_imc = {
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.name = "imc",
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.num_counters = 2,
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.num_boxes = 1,
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.fixed_ctr_bits = 32,
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.fixed_ctr = SNB_UNCORE_PCI_IMC_CTR_BASE,
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.event_descs = snb_uncore_imc_events,
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.format_group = &snb_uncore_imc_format_group,
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.perf_ctr = SNB_UNCORE_PCI_IMC_DATA_READS_BASE,
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.event_mask = SNB_UNCORE_PCI_IMC_EVENT_MASK,
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.ops = &snb_uncore_imc_ops,
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.pmu = &snb_uncore_imc_pmu,
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};
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static struct intel_uncore_type *snb_pci_uncores[] = {
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[SNB_PCI_UNCORE_IMC] = &snb_uncore_imc,
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NULL,
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};
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static DEFINE_PCI_DEVICE_TABLE(snb_uncore_pci_ids) = {
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{ /* IMC */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SNB_IMC),
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.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
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},
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};
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static DEFINE_PCI_DEVICE_TABLE(ivb_uncore_pci_ids) = {
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{ /* IMC */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_IMC),
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.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
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},
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};
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static DEFINE_PCI_DEVICE_TABLE(hsw_uncore_pci_ids) = {
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{ /* IMC */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_IMC),
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.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
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},
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};
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static struct pci_driver snb_uncore_pci_driver = {
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.name = "snb_uncore",
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.id_table = snb_uncore_pci_ids,
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};
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static struct pci_driver ivb_uncore_pci_driver = {
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.name = "ivb_uncore",
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.id_table = ivb_uncore_pci_ids,
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};
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static struct pci_driver hsw_uncore_pci_driver = {
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.name = "hsw_uncore",
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.id_table = hsw_uncore_pci_ids,
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};
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/* end of Sandy Bridge uncore support */
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/* Nehalem uncore support */
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@ -3501,6 +3844,28 @@ static int __init uncore_pci_init(void)
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pci_uncores = ivt_pci_uncores;
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uncore_pci_driver = &ivt_uncore_pci_driver;
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break;
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case 42: /* Sandy Bridge */
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ret = snb_pci2phy_map_init(PCI_DEVICE_ID_INTEL_SNB_IMC);
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if (ret)
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return ret;
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pci_uncores = snb_pci_uncores;
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uncore_pci_driver = &snb_uncore_pci_driver;
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break;
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case 58: /* Ivy Bridge */
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ret = snb_pci2phy_map_init(PCI_DEVICE_ID_INTEL_IVB_IMC);
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if (ret)
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return ret;
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pci_uncores = snb_pci_uncores;
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uncore_pci_driver = &ivb_uncore_pci_driver;
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break;
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case 60: /* Haswell */
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case 69: /* Haswell Celeron */
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ret = snb_pci2phy_map_init(PCI_DEVICE_ID_INTEL_HSW_IMC);
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if (ret)
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return ret;
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pci_uncores = snb_pci_uncores;
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uncore_pci_driver = &hsw_uncore_pci_driver;
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break;
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default:
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return 0;
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}
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@ -492,6 +492,7 @@ struct intel_uncore_box {
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u64 hrtimer_duration; /* hrtimer timeout for this box */
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struct hrtimer hrtimer;
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struct list_head list;
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void *io_addr;
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struct intel_uncore_extra_reg shared_regs[0];
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};
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